37 	} dot, vco, n, m, m1, m2, p, p1;  member
49 	.m1 = { .min = 18, .max = 26 },
62 	.m1 = { .min = 18, .max = 26 },
75 	.m1 = { .min = 18, .max = 26 },
88 	.m1 = { .min = 8, .max = 18 },
101 	.m1 = { .min = 8, .max = 18 },
115 	.m1 = { .min = 17, .max = 23 },
130 	.m1 = { .min = 16, .max = 23 },
143 	.m1 = { .min = 17, .max = 23 },
157 	.m1 = { .min = 17, .max = 23 },
173 	.m1 = { .min = 0, .max = 0 },
186 	.m1 = { .min = 0, .max = 0 },
196  * We calculate clock using (register_value + 2) for N/M1/M2, so here
204 	.m1 = { .min = 12, .max = 22 },
217 	.m1 = { .min = 12, .max = 22 },
230 	.m1 = { .min = 12, .max = 22 },
244 	.m1 = { .min = 12, .max = 22 },
257 	.m1 = { .min = 12, .max = 22 },
275 	.m1 = { .min = 2, .max = 3 },
291 	.m1 = { .min = 2, .max = 2 },
301 	.m1 = { .min = 2, .max = 2 },
316 /* m1 is reserved as 0 in Pineview, n is a ring counter */
332 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
350 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
363 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
438 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;  in i9xx_crtc_clock_get()
533 	clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);  in vlv_crtc_clock_get()
565 	clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;  in chv_crtc_clock_get()
590 	if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)  in intel_pll_is_valid()
596 		if (clock->m1 <= clock->m2)  in intel_pll_is_valid()
667 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in i9xx_find_best_dpll()
668 	     clock.m1++) {  in i9xx_find_best_dpll()
671 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
725 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in pnv_find_best_dpll()
726 	     clock.m1++) {  in pnv_find_best_dpll()
787 		/* based on hardware requirement, prefer larger m1,m2 */  in g4x_find_best_dpll()
788 		for (clock.m1 = limit->m1.max;  in g4x_find_best_dpll()
789 		     clock.m1 >= limit->m1.min; clock.m1--) {  in g4x_find_best_dpll()
883 				/* based on hardware requirement, prefer bigger m1,m2 values */  in vlv_find_best_dpll()
884 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {  in vlv_find_best_dpll()
888 								     refclk * clock.m1);  in vlv_find_best_dpll()
936 	 * Based on hardware doc, the n always set to 1, and m1 always  in chv_find_best_dpll()
941 	clock.m1 = 2;  in chv_find_best_dpll()
952 						   refclk * clock.m1);  in chv_find_best_dpll()
954 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
990 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
1947 	tmp = DPIO_M1_DIV(clock->m1) |  in vlv_prepare_pll()
2070 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()