Lines Matching +full:1 +full:p1
37 } dot, vco, n, m, m1, m2, p, p1; member
52 .p1 = { .min = 2, .max = 33 },
65 .p1 = { .min = 2, .max = 33 },
78 .p1 = { .min = 1, .max = 6 },
86 .n = { .min = 1, .max = 6 },
91 .p1 = { .min = 1, .max = 8 },
99 .n = { .min = 1, .max = 6 },
104 .p1 = { .min = 1, .max = 8 },
113 .n = { .min = 1, .max = 4 },
118 .p1 = { .min = 1, .max = 3},
128 .n = { .min = 1, .max = 4 },
133 .p1 = { .min = 1, .max = 8},
141 .n = { .min = 1, .max = 3 },
146 .p1 = { .min = 2, .max = 8 },
155 .n = { .min = 1, .max = 3 },
160 .p1 = { .min = 2, .max = 6 },
176 .p1 = { .min = 1, .max = 8 },
189 .p1 = { .min = 1, .max = 8 },
202 .n = { .min = 1, .max = 5 },
207 .p1 = { .min = 1, .max = 8 },
215 .n = { .min = 1, .max = 3 },
220 .p1 = { .min = 2, .max = 8 },
228 .n = { .min = 1, .max = 3 },
233 .p1 = { .min = 2, .max = 8 },
242 .n = { .min = 1, .max = 2 },
247 .p1 = { .min = 2, .max = 8 },
255 .n = { .min = 1, .max = 3 },
260 .p1 = { .min = 2, .max = 6 },
274 .n = { .min = 1, .max = 7 },
277 .p1 = { .min = 2, .max = 3 },
290 .n = { .min = 1, .max = 1 },
293 .p1 = { .min = 2, .max = 4 },
294 .p2 = { .p2_slow = 1, .p2_fast = 14 },
300 .n = { .min = 1, .max = 1 },
304 .p1 = { .min = 2, .max = 4 },
305 .p2 = { .p2_slow = 1, .p2_fast = 20 },
320 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
338 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
351 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
364 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
440 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
449 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
452 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
483 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
492 clock.p1 = 2; in i9xx_crtc_clock_get()
494 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
536 clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp); in vlv_crtc_clock_get()
570 clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13); in chv_crtc_clock_get()
586 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
675 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
676 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
731 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
732 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
792 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
793 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
879 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
881 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
882 clock.p = clock.p1 * clock.p2 * 5; in vlv_find_best_dpll()
936 * Based on hardware doc, the n always set to 1, and m1 always in chv_find_best_dpll()
938 * revisit this because n may not 1 anymore. in chv_find_best_dpll()
940 clock.n = 1; in chv_find_best_dpll()
943 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
946 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
949 clock.p = clock.p1 * clock.p2 * 5; in chv_find_best_dpll()
995 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
1000 return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in i965_dpll_md()
1021 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_dpll()
1032 /* compute bitmask from p1 value */ in i9xx_dpll()
1034 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1035 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_dpll()
1037 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_dpll()
1038 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1040 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1041 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1108 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1110 if (clock->p1 == 2) in i8xx_dpll()
1113 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1117 WARN_ON(reduced_clock->p1 != clock->p1); in i8xx_dpll()
1125 * Enable) must be set to “1” in both the DPLL A Control Register in i8xx_dpll()
1290 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_dpll()
1318 /* compute bitmask from p1 value */ in ilk_dpll()
1319 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
1321 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_dpll()
1857 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i9xx_enable_pll()
1949 DPIO_P1_DIV(clock->p1) | in vlv_prepare_pll()
1952 DPIO_K_DIV(1); in vlv_prepare_pll()
2015 if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
2059 /* p1 and p2 divider */ in chv_prepare_pll()
2062 DPIO_CHV_P1_DIV(clock->p1) | in chv_prepare_pll()
2064 DPIO_CHV_K_DIV(1)); in chv_prepare_pll()
2073 DPIO_CHV_N_DIV(1)); in chv_prepare_pll()
2156 udelay(1); in _chv_enable_pll()
2162 if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
2237 crtc_state->pixel_multiplier = 1; in vlv_force_pll_on()