97 /* DP DSC throughput values used for slice count calculations KPixels/s */
105 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
108 /* Constants for DP DSC configurations */
126  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
127  * @intel_dp: DP struct
129  * If a CPU or PCH DP output is attached to an eDP panel, this function
138 	return dig_port->base.type == INTEL_OUTPUT_EDP;  in intel_dp_is_edp()
146 	return drm_dp_is_uhbr_rate(crtc_state->port_clock);  in intel_dp_is_uhbr()
150  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
154  * rate -> channel coding.
162  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
176 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in max_dprx_rate()
180 		max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);  in max_dprx_rate()
182 		max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);  in max_dprx_rate()
189 	if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {  in max_dprx_rate()
190 		drm_dbg_kms(display->drm,  in max_dprx_rate()
192 			    encoder->base.base.id, encoder->base.name);  in max_dprx_rate()
202 		return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);  in max_dprx_lane_count()
204 	return drm_dp_max_lane_count(intel_dp->dpcd);  in max_dprx_lane_count()
209 	intel_dp->sink_rates[0] = 162000;  in intel_dp_set_default_sink_rates()
210 	intel_dp->num_sink_rates = 1;  in intel_dp_set_default_sink_rates()
222 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {  in intel_dp_set_dpcd_sink_rates()
226 		memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));  in intel_dp_set_dpcd_sink_rates()
227 		intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);  in intel_dp_set_dpcd_sink_rates()
236 	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);  in intel_dp_set_dpcd_sink_rates()
243 		intel_dp->sink_rates[i] = dp_rates[i];  in intel_dp_set_dpcd_sink_rates()
250 	if (drm_dp_128b132b_supported(intel_dp->dpcd)) {  in intel_dp_set_dpcd_sink_rates()
253 		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);  in intel_dp_set_dpcd_sink_rates()
255 		drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_set_dpcd_sink_rates()
258 		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {  in intel_dp_set_dpcd_sink_rates()
260 			if (intel_dp->lttpr_common_caps[0] >= 0x20 &&  in intel_dp_set_dpcd_sink_rates()
261 			    intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -  in intel_dp_set_dpcd_sink_rates()
265 				uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -  in intel_dp_set_dpcd_sink_rates()
274 			intel_dp->sink_rates[i++] = 1000000;  in intel_dp_set_dpcd_sink_rates()
276 			intel_dp->sink_rates[i++] = 1350000;  in intel_dp_set_dpcd_sink_rates()
278 			intel_dp->sink_rates[i++] = 2000000;  in intel_dp_set_dpcd_sink_rates()
281 	intel_dp->num_sink_rates = i;  in intel_dp_set_dpcd_sink_rates()
287 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_sink_rates()  local
289 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_set_sink_rates()
293 	if (intel_dp->num_sink_rates)  in intel_dp_set_sink_rates()
296 	drm_err(display->drm,  in intel_dp_set_sink_rates()
297 		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",  in intel_dp_set_sink_rates()
298 		connector->base.base.id, connector->base.name,  in intel_dp_set_sink_rates()
299 		encoder->base.base.id, encoder->base.name);  in intel_dp_set_sink_rates()
306 	intel_dp->max_sink_lane_count = 1;  in intel_dp_set_default_max_sink_lane_count()
312 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_max_sink_lane_count()  local
314 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_set_max_sink_lane_count()
316 	intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);  in intel_dp_set_max_sink_lane_count()
318 	switch (intel_dp->max_sink_lane_count) {  in intel_dp_set_max_sink_lane_count()
325 	drm_err(display->drm,  in intel_dp_set_max_sink_lane_count()
326 		"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",  in intel_dp_set_max_sink_lane_count()
327 		connector->base.base.id, connector->base.name,  in intel_dp_set_max_sink_lane_count()
328 		encoder->base.base.id, encoder->base.name,  in intel_dp_set_max_sink_lane_count()
329 		intel_dp->max_sink_lane_count);  in intel_dp_set_max_sink_lane_count()
341 		if (rates[len - i - 1] <= max_rate)  in intel_dp_rate_limit_len()
342 			return len - i;  in intel_dp_rate_limit_len()
352 	return intel_dp_rate_limit_len(intel_dp->common_rates,  in intel_dp_common_len_rate_limit()
353 				       intel_dp->num_common_rates, max_rate);  in intel_dp_common_len_rate_limit()
360 	if (drm_WARN_ON(display->drm,  in intel_dp_common_rate()
361 			index < 0 || index >= intel_dp->num_common_rates))  in intel_dp_common_rate()
364 	return intel_dp->common_rates[index];  in intel_dp_common_rate()
370 	return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);  in intel_dp_max_common_rate()
375 	int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);  in intel_dp_max_source_lane_count()
376 	int max_lanes = dig_port->max_lanes;  in intel_dp_max_source_lane_count()
389 	int sink_max = intel_dp->max_sink_lane_count;  in intel_dp_max_common_lane_count()
391 	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);  in intel_dp_max_common_lane_count()
401 	return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));  in forced_lane_count()
408 	if (intel_dp->link.force_lane_count)  in intel_dp_max_lane_count()
411 		lane_count = intel_dp->link.max_lane_count;  in intel_dp_max_lane_count()
426 	if (intel_dp->link.force_lane_count)  in intel_dp_min_lane_count()
447  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
464  * @intel_dp: Intel DP object
469  * account any BW limitations by a DP tunnel attached to @intel_dp.
480 			       drm_dp_tunnel_available_bw(intel_dp->tunnel));  in intel_dp_max_link_data_rate()
489 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_has_joiner()
492 	if (intel_dp->mso_link_count)  in intel_dp_has_joiner()
497 		 encoder->port != PORT_A);  in intel_dp_has_joiner()
507 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in icl_max_source_rate()
526 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in mtl_max_source_rate()
539 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in vbt_max_link_rate()
542 	max_rate = intel_bios_dp_max_link_rate(encoder->devdata);  in vbt_max_link_rate()
545 		struct intel_connector *connector = intel_dp->attached_connector;  in vbt_max_link_rate()  local
546 		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;  in vbt_max_link_rate()
590 	drm_WARN_ON(display->drm,  in intel_dp_set_source_rates()
591 		    intel_dp->source_rates || intel_dp->num_source_rates);  in intel_dp_set_source_rates()
594 		if (display->platform.battlemage) {  in intel_dp_set_source_rates()
605 		if (display->platform.dg2)  in intel_dp_set_source_rates()
607 		else if (display->platform.alderlake_p || display->platform.alderlake_s ||  in intel_dp_set_source_rates()
608 			 display->platform.dg1 || display->platform.rocketlake)  in intel_dp_set_source_rates()
610 		else if (display->platform.jasperlake || display->platform.elkhartlake)  in intel_dp_set_source_rates()
614 	} else if (display->platform.geminilake || display->platform.broxton) {  in intel_dp_set_source_rates()
620 	} else if ((display->platform.haswell && !display->platform.haswell_ulx) ||  in intel_dp_set_source_rates()
621 		   display->platform.broadwell) {  in intel_dp_set_source_rates()
638 	intel_dp->source_rates = source_rates;  in intel_dp_set_source_rates()
639 	intel_dp->num_source_rates = size;  in intel_dp_set_source_rates()
665 /* return index of rate in rates array, or -1 if not found */
674 	return -1;  in intel_dp_rate_index()
680 	return intel_dp_common_rate(intel_dp, lc->link_rate_idx);  in intel_dp_link_config_rate()
685 	return 1 << lc->lane_count_exp;  in intel_dp_link_config_lane_count()
704 		return bw_a - bw_b;  in link_config_cmp_by_bw()
706 	return intel_dp_link_config_rate(intel_dp, lc_a) -  in link_config_cmp_by_bw()
718 	if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))  in intel_dp_link_config_init()
723 	if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >  in intel_dp_link_config_init()
724 				    ARRAY_SIZE(intel_dp->link.configs)))  in intel_dp_link_config_init()
727 	intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;  in intel_dp_link_config_init()
729 	lc = &intel_dp->link.configs[0];  in intel_dp_link_config_init()
730 	for (i = 0; i < intel_dp->num_common_rates; i++) {  in intel_dp_link_config_init()
732 			lc->lane_count_exp = j;  in intel_dp_link_config_init()
733 			lc->link_rate_idx = i;  in intel_dp_link_config_init()
739 	sort_r(intel_dp->link.configs, intel_dp->link.num_configs,  in intel_dp_link_config_init()
740 	       sizeof(intel_dp->link.configs[0]),  in intel_dp_link_config_init()
750 	if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))  in intel_dp_link_config_get()
753 	lc = &intel_dp->link.configs[idx];  in intel_dp_link_config_get()
761 	int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,  in intel_dp_link_config_index()
766 	for (i = 0; i < intel_dp->link.num_configs; i++) {  in intel_dp_link_config_index()
767 		const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];  in intel_dp_link_config_index()
769 		if (lc->lane_count_exp == lane_count_exp &&  in intel_dp_link_config_index()
770 		    lc->link_rate_idx == link_rate_idx)  in intel_dp_link_config_index()
774 	return -1;  in intel_dp_link_config_index()
781 	drm_WARN_ON(display->drm,  in intel_dp_set_common_rates()
782 		    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);  in intel_dp_set_common_rates()
784 	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,  in intel_dp_set_common_rates()
785 						     intel_dp->num_source_rates,  in intel_dp_set_common_rates()
786 						     intel_dp->sink_rates,  in intel_dp_set_common_rates()
787 						     intel_dp->num_sink_rates,  in intel_dp_set_common_rates()
788 						     intel_dp->common_rates);  in intel_dp_set_common_rates()
791 	if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {  in intel_dp_set_common_rates()
792 		intel_dp->common_rates[0] = 162000;  in intel_dp_set_common_rates()
793 		intel_dp->num_common_rates = 1;  in intel_dp_set_common_rates()
805 	 * boot-up.  in intel_dp_link_params_valid()
808 	    link_rate > intel_dp->link.max_rate)  in intel_dp_link_params_valid()
828 	 * The hard-coded 1/0.972261=2.853% overhead factor  in intel_dp_bw_fec_overhead()
829 	 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +  in intel_dp_bw_fec_overhead()
833 	 * lane DP link, with 2 DSC slices and 8 bpp color depth).  in intel_dp_bw_fec_overhead()
856 		drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",  in intel_dp_dsc_nearest_valid_bpp()
861 	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */  in intel_dp_dsc_nearest_valid_bpp()
863 		bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);  in intel_dp_dsc_nearest_valid_bpp()
874 			drm_dbg_kms(display->drm,  in intel_dp_dsc_nearest_valid_bpp()
882 		for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {  in intel_dp_dsc_nearest_valid_bpp()
886 		drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",  in intel_dp_dsc_nearest_valid_bpp()
908 	max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /  in bigjoiner_bw_max_bpp()
970 	 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)  in intel_dp_dsc_get_max_compressed_bpp()
971 	 * for MST -> TimeSlots has to be calculated, based on mode requirements  in intel_dp_dsc_get_max_compressed_bpp()
999 	drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "  in intel_dp_dsc_get_max_compressed_bpp()
1014 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,  in intel_dp_dsc_get_slice_count()  argument
1018 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_get_slice_count()
1033 	if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))  in intel_dp_dsc_get_slice_count()
1036 	max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);  in intel_dp_dsc_get_slice_count()
1038 		drm_dbg_kms(display->drm,  in intel_dp_dsc_get_slice_count()
1039 			    "Unsupported slice width %d by DP DSC Sink device\n",  in intel_dp_dsc_get_slice_count()
1061 		    drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))  in intel_dp_dsc_get_slice_count()
1079 	drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",  in intel_dp_dsc_get_slice_count()
1096 		 * Also, ILK doesn't seem capable of DP YCbCr output.  in source_can_output()
1099 		return !HAS_GMCH(display) && !display->platform.ironlake;  in source_can_output()
1115 	if (!drm_dp_is_branch(intel_dp->dpcd))  in dfp_can_convert_from_rgb()
1119 		return intel_dp->dfp.rgb_to_ycbcr;  in dfp_can_convert_from_rgb()
1122 		return intel_dp->dfp.rgb_to_ycbcr &&  in dfp_can_convert_from_rgb()
1123 			intel_dp->dfp.ycbcr_444_to_420;  in dfp_can_convert_from_rgb()
1132 	if (!drm_dp_is_branch(intel_dp->dpcd))  in dfp_can_convert_from_ycbcr444()
1136 		return intel_dp->dfp.ycbcr_444_to_420;  in dfp_can_convert_from_ycbcr444()
1160 intel_dp_output_format(struct intel_connector *connector,  in intel_dp_output_format()  argument
1163 	struct intel_display *display = to_intel_display(connector);  in intel_dp_output_format()
1164 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_output_format()
1166 		intel_dp->force_dsc_output_format;  in intel_dp_output_format()
1170 		    (!drm_dp_is_branch(intel_dp->dpcd) ||  in intel_dp_output_format()
1175 		drm_dbg_kms(display->drm, "Cannot force DSC output format\n");  in intel_dp_output_format()
1189 	drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));  in intel_dp_output_format()
1216 intel_dp_sink_format(struct intel_connector *connector,  in intel_dp_sink_format()  argument
1219 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_sink_format()
1228 intel_dp_mode_min_output_bpp(struct intel_connector *connector,  in intel_dp_mode_min_output_bpp()  argument
1233 	sink_format = intel_dp_sink_format(connector, mode);  in intel_dp_mode_min_output_bpp()
1235 	output_format = intel_dp_output_format(connector, sink_format);  in intel_dp_mode_min_output_bpp()
1244 	 * Older platforms don't like hdisplay==4096 with DP.  in intel_dp_hdisplay_bad()
1261 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_max_tmds_clock()  local
1262 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_max_tmds_clock()
1263 	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;  in intel_dp_max_tmds_clock()
1266 	if (max_tmds_clock && info->max_tmds_clock)  in intel_dp_max_tmds_clock()
1267 		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);  in intel_dp_max_tmds_clock()
1285 	min_tmds_clock = intel_dp->dfp.min_tmds_clock;  in intel_dp_tmds_clock_valid()
1298 intel_dp_mode_valid_downstream(struct intel_connector *connector,  in intel_dp_mode_valid_downstream()  argument
1302 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_mode_valid_downstream()
1303 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_mode_valid_downstream()
1308 	if (intel_dp->dfp.pcon_max_frl_bw) {  in intel_dp_mode_valid_downstream()
1311 		int bpp = intel_dp_mode_min_output_bpp(connector, mode);  in intel_dp_mode_valid_downstream()
1315 		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;  in intel_dp_mode_valid_downstream()
1326 	if (intel_dp->dfp.max_dotclock &&  in intel_dp_mode_valid_downstream()
1327 	    target_clock > intel_dp->dfp.max_dotclock)  in intel_dp_mode_valid_downstream()
1330 	sink_format = intel_dp_sink_format(connector, mode);  in intel_dp_mode_valid_downstream()
1332 	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */  in intel_dp_mode_valid_downstream()
1338 		    !connector->base.ycbcr_420_allowed ||  in intel_dp_mode_valid_downstream()
1353 			   struct intel_connector *connector,  in intel_dp_needs_joiner()  argument
1367 	return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||  in intel_dp_needs_joiner()
1372 			      struct intel_connector *connector,  in intel_dp_num_joined_pipes()  argument
1377 	if (connector->force_joined_pipes)  in intel_dp_num_joined_pipes()
1378 		return connector->force_joined_pipes;  in intel_dp_num_joined_pipes()
1381 	    intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))  in intel_dp_num_joined_pipes()
1385 	    intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))  in intel_dp_num_joined_pipes()
1391 bool intel_dp_has_dsc(const struct intel_connector *connector)  in intel_dp_has_dsc()  argument
1393 	struct intel_display *display = to_intel_display(connector);  in intel_dp_has_dsc()
1398 	if (connector->mst_port && !HAS_DSC_MST(display))  in intel_dp_has_dsc()
1401 	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&  in intel_dp_has_dsc()
1402 	    connector->panel.vbt.edp.dsc_disable)  in intel_dp_has_dsc()
1405 	if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))  in intel_dp_has_dsc()
1415 	struct intel_display *display = to_intel_display(_connector->dev);  in intel_dp_mode_valid()
1416 	struct intel_connector *connector = to_intel_connector(_connector);  in intel_dp_mode_valid()  local
1417 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_mode_valid()
1418 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);  in intel_dp_mode_valid()
1420 	int target_clock = mode->clock;  in intel_dp_mode_valid()
1422 	int max_dotclk = display->cdclk.max_dotclk_freq;  in intel_dp_mode_valid()
1433 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)  in intel_dp_mode_valid()
1436 	if (mode->clock < 10000)  in intel_dp_mode_valid()
1439 	fixed_mode = intel_panel_fixed_mode(connector, mode);  in intel_dp_mode_valid()
1441 		status = intel_panel_mode_valid(connector, mode);  in intel_dp_mode_valid()
1445 		target_clock = fixed_mode->clock;  in intel_dp_mode_valid()
1448 	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,  in intel_dp_mode_valid()
1449 						     mode->hdisplay, target_clock);  in intel_dp_mode_valid()
1455 	if (intel_dp_hdisplay_bad(display, mode->hdisplay))  in intel_dp_mode_valid()
1464 					   intel_dp_mode_min_output_bpp(connector, mode));  in intel_dp_mode_valid()
1466 	if (intel_dp_has_dsc(connector)) {  in intel_dp_mode_valid()
1470 		sink_format = intel_dp_sink_format(connector, mode);  in intel_dp_mode_valid()
1471 		output_format = intel_dp_output_format(connector, sink_format);  in intel_dp_mode_valid()
1473 		 * TBD pass the connector BPC,  in intel_dp_mode_valid()
1476 		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);  in intel_dp_mode_valid()
1484 				drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;  in intel_dp_mode_valid()
1486 				drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,  in intel_dp_mode_valid()
1488 		} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {  in intel_dp_mode_valid()
1494 								    mode->hdisplay,  in intel_dp_mode_valid()
1499 				intel_dp_dsc_get_slice_count(connector,  in intel_dp_mode_valid()
1501 							     mode->hdisplay,  in intel_dp_mode_valid()
1514 	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);  in intel_dp_mode_valid()
1524 		display->platform.broadwell || display->platform.haswell;  in intel_dp_source_supports_tps3()
1548 	seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates);  in intel_dp_print_rates()
1549 	drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));  in intel_dp_print_rates()
1552 	seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates);  in intel_dp_print_rates()
1553 	drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));  in intel_dp_print_rates()
1556 	seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates);  in intel_dp_print_rates()
1557 	drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));  in intel_dp_print_rates()
1562 	int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);  in forced_link_rate()
1567 	return intel_dp_common_rate(intel_dp, len - 1);  in forced_link_rate()
1575 	if (intel_dp->link.force_rate)  in intel_dp_max_link_rate()
1578 	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);  in intel_dp_max_link_rate()
1580 	return intel_dp_common_rate(intel_dp, len - 1);  in intel_dp_max_link_rate()
1586 	if (intel_dp->link.force_rate)  in intel_dp_min_link_rate()
1595 	int i = intel_dp_rate_index(intel_dp->sink_rates,  in intel_dp_rate_select()
1596 				    intel_dp->num_sink_rates, rate);  in intel_dp_rate_select()
1598 	if (drm_WARN_ON(display->drm, i < 0))  in intel_dp_rate_select()
1608 	if (intel_dp->use_rate_select) {  in intel_dp_compute_rate()
1620 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_has_hdmi_sink()  local
1622 	return connector->base.display_info.is_hdmi;  in intel_dp_has_hdmi_sink()
1629 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_source_supports_fec()
1634 	if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&  in intel_dp_source_supports_fec()
1642 			   const struct intel_connector *connector,  in intel_dp_supports_fec()  argument
1646 		drm_dp_sink_supports_fec(connector->dp.fec_capability);  in intel_dp_supports_fec()
1650 			   const struct intel_connector *connector,  in intel_dp_supports_dsc()  argument
1653 	if (!intel_dp_has_dsc(connector))  in intel_dp_supports_dsc()
1657 	    !intel_dp_supports_fec(intel_dp, connector, crtc_state))  in intel_dp_supports_dsc()
1667 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;  in intel_dp_hdmi_compute_bpc()
1684 	for (; bpc >= 8; bpc -= 2) {  in intel_dp_hdmi_compute_bpc()
1687 		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,  in intel_dp_hdmi_compute_bpc()
1692 	return -EINVAL;  in intel_dp_hdmi_compute_bpc()
1700 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_max_bpp()  local
1703 	bpc = crtc_state->pipe_bpp / 3;  in intel_dp_max_bpp()
1705 	if (intel_dp->dfp.max_bpc)  in intel_dp_max_bpp()
1706 		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);  in intel_dp_max_bpp()
1708 	if (intel_dp->dfp.min_tmds_clock) {  in intel_dp_max_bpp()
1722 		if (connector->base.display_info.bpc == 0 &&  in intel_dp_max_bpp()
1723 		    connector->panel.vbt.edp.bpp &&  in intel_dp_max_bpp()
1724 		    connector->panel.vbt.edp.bpp < bpp) {  in intel_dp_max_bpp()
1725 			drm_dbg_kms(display->drm,  in intel_dp_max_bpp()
1726 				    "clamping bpp for eDP panel to BIOS-provided %i\n",  in intel_dp_max_bpp()
1727 				    connector->panel.vbt.edp.bpp);  in intel_dp_max_bpp()
1728 			bpp = connector->panel.vbt.edp.bpp;  in intel_dp_max_bpp()
1735 static bool has_seamless_m_n(struct intel_connector *connector)  in has_seamless_m_n()  argument
1737 	struct intel_display *display = to_intel_display(connector);  in has_seamless_m_n()
1744 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;  in has_seamless_m_n()
1750 	struct intel_connector *connector = to_intel_connector(conn_state->connector);  in intel_dp_mode_clock()  local
1751 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_dp_mode_clock()
1754 	if (has_seamless_m_n(connector))  in intel_dp_mode_clock()
1755 		return intel_panel_highest_mode(connector, adjusted_mode)->clock;  in intel_dp_mode_clock()
1757 		return adjusted_mode->crtc_clock;  in intel_dp_mode_clock()
1770 	for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);  in intel_dp_compute_link_config_wide()
1771 	     bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);  in intel_dp_compute_link_config_wide()
1772 	     bpp -= 2 * 3) {  in intel_dp_compute_link_config_wide()
1773 		int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);  in intel_dp_compute_link_config_wide()
1777 		for (i = 0; i < intel_dp->num_common_rates; i++) {  in intel_dp_compute_link_config_wide()
1779 			if (link_rate < limits->min_rate ||  in intel_dp_compute_link_config_wide()
1780 			    link_rate > limits->max_rate)  in intel_dp_compute_link_config_wide()
1783 			for (lane_count = limits->min_lane_count;  in intel_dp_compute_link_config_wide()
1784 			     lane_count <= limits->max_lane_count;  in intel_dp_compute_link_config_wide()
1792 					pipe_config->lane_count = lane_count;  in intel_dp_compute_link_config_wide()
1793 					pipe_config->pipe_bpp = bpp;  in intel_dp_compute_link_config_wide()
1794 					pipe_config->port_clock = link_rate;  in intel_dp_compute_link_config_wide()
1802 	return -EINVAL;  in intel_dp_compute_link_config_wide()
1816 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,  in intel_dp_dsc_compute_max_bpp()  argument
1819 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_compute_max_bpp()
1831 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,  in intel_dp_dsc_compute_max_bpp()
1848 	return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>  in intel_dp_sink_dsc_version_minor()
1874 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,  in intel_dp_dsc_compute_params()  argument
1877 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_compute_params()
1878 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dp_dsc_compute_params()
1887 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;  in intel_dp_dsc_compute_params()
1888 	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;  in intel_dp_dsc_compute_params()
1890 	vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);  in intel_dp_dsc_compute_params()
1896 	vdsc_cfg->dsc_version_major =  in intel_dp_dsc_compute_params()
1897 		(connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1899 	vdsc_cfg->dsc_version_minor =  in intel_dp_dsc_compute_params()
1901 		    intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));  in intel_dp_dsc_compute_params()
1902 	if (vdsc_cfg->convert_rgb)  in intel_dp_dsc_compute_params()
1903 		vdsc_cfg->convert_rgb =  in intel_dp_dsc_compute_params()
1904 			connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1907 	vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,  in intel_dp_dsc_compute_params()
1908 				       drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));  in intel_dp_dsc_compute_params()
1909 	if (!vdsc_cfg->line_buf_depth) {  in intel_dp_dsc_compute_params()
1910 		drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_params()
1912 		return -EINVAL;  in intel_dp_dsc_compute_params()
1915 	vdsc_cfg->block_pred_enable =  in intel_dp_dsc_compute_params()
1916 		connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1922 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,  in intel_dp_dsc_supports_format()  argument
1925 	struct intel_display *display = to_intel_display(connector);  in intel_dp_dsc_supports_format()
1937 			intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)  in intel_dp_dsc_supports_format()
1945 	return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);  in intel_dp_dsc_supports_format()
1967 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in dsc_compute_link_config()
1971 	for (i = 0; i < intel_dp->num_common_rates; i++) {  in dsc_compute_link_config()
1973 		if (link_rate < limits->min_rate || link_rate > limits->max_rate)  in dsc_compute_link_config()
1976 		for (lane_count = limits->min_lane_count;  in dsc_compute_link_config()
1977 		     lane_count <= limits->max_lane_count;  in dsc_compute_link_config()
1980 							     lane_count, adjusted_mode->clock,  in dsc_compute_link_config()
1981 							     pipe_config->output_format,  in dsc_compute_link_config()
1985 			pipe_config->lane_count = lane_count;  in dsc_compute_link_config()
1986 			pipe_config->port_clock = link_rate;  in dsc_compute_link_config()
1992 	return -EINVAL;  in dsc_compute_link_config()
1996 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,  in intel_dp_dsc_max_sink_compressed_bppx16()  argument
2000 	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);  in intel_dp_dsc_max_sink_compressed_bppx16()
2006 	 * values as given in spec Table 2-157 DP v2.0  in intel_dp_dsc_max_sink_compressed_bppx16()
2008 	switch (pipe_config->output_format) {  in intel_dp_dsc_max_sink_compressed_bppx16()
2015 		MISSING_CASE(pipe_config->output_format);  in intel_dp_dsc_max_sink_compressed_bppx16()
2024 	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */  in intel_dp_dsc_sink_min_compressed_bpp()
2025 	switch (pipe_config->output_format) {  in intel_dp_dsc_sink_min_compressed_bpp()
2032 		MISSING_CASE(pipe_config->output_format);  in intel_dp_dsc_sink_min_compressed_bpp()
2039 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,  in intel_dp_dsc_sink_max_compressed_bpp()  argument
2043 	return intel_dp_dsc_max_sink_compressed_bppx16(connector,  in intel_dp_dsc_sink_max_compressed_bpp()
2063 	if (intel_dp->force_dsc_en)  in dsc_src_max_compressed_bpp()
2092 	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);  in icl_dsc_compute_link_config()
2094 	for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) {  in icl_dsc_compute_link_config()
2105 			pipe_config->dsc.compressed_bpp_x16 =  in icl_dsc_compute_link_config()
2111 	return -EINVAL;  in icl_dsc_compute_link_config()
2116  * uncompressed bpp-1. So we start from max compressed bpp and see if any
2122 			      const struct intel_connector *connector,  in xelpd_dsc_compute_link_config()  argument
2131 	u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);  in xelpd_dsc_compute_link_config()
2142 	dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);  in xelpd_dsc_compute_link_config()
2147 	     compressed_bppx16 -= bppx16_step) {  in xelpd_dsc_compute_link_config()
2148 		if (intel_dp->force_dsc_fractional_bpp_en &&  in xelpd_dsc_compute_link_config()
2157 			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;  in xelpd_dsc_compute_link_config()
2158 			if (intel_dp->force_dsc_fractional_bpp_en &&  in xelpd_dsc_compute_link_config()
2160 				drm_dbg_kms(display->drm,  in xelpd_dsc_compute_link_config()
2166 	return -EINVAL;  in xelpd_dsc_compute_link_config()
2170 				      const struct intel_connector *connector,  in dsc_compute_compressed_bpp()  argument
2177 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in dsc_compute_compressed_bpp()
2183 	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);  in dsc_compute_compressed_bpp()
2185 	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,  in dsc_compute_compressed_bpp()
2186 								adjusted_mode->hdisplay,  in dsc_compute_compressed_bpp()
2188 	dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));  in dsc_compute_compressed_bpp()
2191 		return xelpd_dsc_compute_link_config(intel_dp, connector, pipe_config, limits,  in dsc_compute_compressed_bpp()
2207 	return pipe_bpp >= limits->pipe.min_bpp &&  in is_dsc_pipe_bpp_sufficient()
2208 	       pipe_bpp <= limits->pipe.max_bpp;  in is_dsc_pipe_bpp_sufficient()
2218 	if (!intel_dp->force_dsc_bpc)  in intel_dp_force_dsc_pipe_bpp()
2221 	forced_bpp = intel_dp->force_dsc_bpc * 3;  in intel_dp_force_dsc_pipe_bpp()
2224 		drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",  in intel_dp_force_dsc_pipe_bpp()
2225 			    intel_dp->force_dsc_bpc);  in intel_dp_force_dsc_pipe_bpp()
2229 	drm_dbg_kms(display->drm,  in intel_dp_force_dsc_pipe_bpp()
2231 		    intel_dp->force_dsc_bpc);  in intel_dp_force_dsc_pipe_bpp()
2242 	const struct intel_connector *connector =  in intel_dp_dsc_compute_pipe_bpp()  local
2243 		to_intel_connector(conn_state->connector);  in intel_dp_dsc_compute_pipe_bpp()
2253 		ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,  in intel_dp_dsc_compute_pipe_bpp()
2256 			pipe_config->pipe_bpp = forced_bpp;  in intel_dp_dsc_compute_pipe_bpp()
2261 	dsc_max_bpp = limits->pipe.max_bpp;  in intel_dp_dsc_compute_pipe_bpp()
2262 	dsc_min_bpp = limits->pipe.min_bpp;  in intel_dp_dsc_compute_pipe_bpp()
2268 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);  in intel_dp_dsc_compute_pipe_bpp()
2275 		ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config,  in intel_dp_dsc_compute_pipe_bpp()
2278 			pipe_config->pipe_bpp = pipe_bpp;  in intel_dp_dsc_compute_pipe_bpp()
2283 	return -EINVAL;  in intel_dp_dsc_compute_pipe_bpp()
2292 	struct intel_connector *connector =  in intel_edp_dsc_compute_pipe_bpp()  local
2293 		to_intel_connector(conn_state->connector);  in intel_edp_dsc_compute_pipe_bpp()
2303 		int max_bpc = limits->pipe.max_bpp / 3;  in intel_edp_dsc_compute_pipe_bpp()
2306 		pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);  in intel_edp_dsc_compute_pipe_bpp()
2308 			drm_dbg_kms(display->drm,  in intel_edp_dsc_compute_pipe_bpp()
2310 			return -EINVAL;  in intel_edp_dsc_compute_pipe_bpp()
2313 	pipe_config->port_clock = limits->max_rate;  in intel_edp_dsc_compute_pipe_bpp()
2314 	pipe_config->lane_count = limits->max_lane_count;  in intel_edp_dsc_compute_pipe_bpp()
2316 	dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);  in intel_edp_dsc_compute_pipe_bpp()
2318 	dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16);  in intel_edp_dsc_compute_pipe_bpp()
2321 	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);  in intel_edp_dsc_compute_pipe_bpp()
2323 	pipe_config->dsc.compressed_bpp_x16 =  in intel_edp_dsc_compute_pipe_bpp()
2326 	pipe_config->pipe_bpp = pipe_bpp;  in intel_edp_dsc_compute_pipe_bpp()
2334 	if (crtc_state->fec_enable)  in intel_dp_fec_compute_config()
2338 	 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.  in intel_dp_fec_compute_config()
2348 	crtc_state->fec_enable = true;  in intel_dp_fec_compute_config()
2359 	const struct intel_connector *connector =  in intel_dp_dsc_compute_config()  local
2360 		to_intel_connector(conn_state->connector);  in intel_dp_dsc_compute_config()
2362 		&pipe_config->hw.adjusted_mode;  in intel_dp_dsc_compute_config()
2368 	if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))  in intel_dp_dsc_compute_config()
2369 		return -EINVAL;  in intel_dp_dsc_compute_config()
2372 	 * compute pipe bpp is set to false for DP MST DSC case  in intel_dp_dsc_compute_config()
2385 			drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_config()
2393 		pipe_config->dsc.slice_count =  in intel_dp_dsc_compute_config()
2394 			drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,  in intel_dp_dsc_compute_config()
2396 		if (!pipe_config->dsc.slice_count) {  in intel_dp_dsc_compute_config()
2397 			drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_config()
2399 				    pipe_config->dsc.slice_count);  in intel_dp_dsc_compute_config()
2400 			return -EINVAL;  in intel_dp_dsc_compute_config()
2406 			intel_dp_dsc_get_slice_count(connector,  in intel_dp_dsc_compute_config()
2407 						     adjusted_mode->crtc_clock,  in intel_dp_dsc_compute_config()
2408 						     adjusted_mode->crtc_hdisplay,  in intel_dp_dsc_compute_config()
2411 			drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_config()
2413 			return -EINVAL;  in intel_dp_dsc_compute_config()
2416 		pipe_config->dsc.slice_count = dsc_dp_slice_count;  in intel_dp_dsc_compute_config()
2425 	if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&  in intel_dp_dsc_compute_config()
2426 	    pipe_config->dsc.slice_count == 12)  in intel_dp_dsc_compute_config()
2427 		pipe_config->dsc.num_streams = 3;  in intel_dp_dsc_compute_config()
2428 	else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)  in intel_dp_dsc_compute_config()
2429 		pipe_config->dsc.num_streams = 2;  in intel_dp_dsc_compute_config()
2431 		pipe_config->dsc.num_streams = 1;  in intel_dp_dsc_compute_config()
2433 	ret = intel_dp_dsc_compute_params(connector, pipe_config);  in intel_dp_dsc_compute_config()
2435 		drm_dbg_kms(display->drm,  in intel_dp_dsc_compute_config()
2438 			    pipe_config->pipe_bpp,  in intel_dp_dsc_compute_config()
2439 			    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));  in intel_dp_dsc_compute_config()
2443 	pipe_config->dsc.compression_enable = true;  in intel_dp_dsc_compute_config()
2444 	drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "  in intel_dp_dsc_compute_config()
2446 		    pipe_config->pipe_bpp,  in intel_dp_dsc_compute_config()
2447 		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),  in intel_dp_dsc_compute_config()
2448 		    pipe_config->dsc.slice_count);  in intel_dp_dsc_compute_config()
2459 					const struct intel_connector *connector,  in intel_dp_compute_config_link_bpp_limits()  argument
2466 		&crtc_state->hw.adjusted_mode;  in intel_dp_compute_config_link_bpp_limits()
2467 	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_dp_compute_config_link_bpp_limits()
2468 	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_compute_config_link_bpp_limits()
2471 	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,  in intel_dp_compute_config_link_bpp_limits()
2472 			       fxp_q4_from_int(limits->pipe.max_bpp));  in intel_dp_compute_config_link_bpp_limits()
2477 		if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))  in intel_dp_compute_config_link_bpp_limits()
2480 		limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);  in intel_dp_compute_config_link_bpp_limits()
2488 		limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);  in intel_dp_compute_config_link_bpp_limits()
2491 		dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,  in intel_dp_compute_config_link_bpp_limits()
2493 									limits->pipe.max_bpp / 3);  in intel_dp_compute_config_link_bpp_limits()
2500 	limits->link.max_bpp_x16 = max_link_bpp_x16;  in intel_dp_compute_config_link_bpp_limits()
2502 	drm_dbg_kms(display->drm,  in intel_dp_compute_config_link_bpp_limits()
2503 …"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d ma…  in intel_dp_compute_config_link_bpp_limits()
2504 		    encoder->base.base.id, encoder->base.name,  in intel_dp_compute_config_link_bpp_limits()
2505 		    crtc->base.base.id, crtc->base.name,  in intel_dp_compute_config_link_bpp_limits()
2506 		    adjusted_mode->crtc_clock,  in intel_dp_compute_config_link_bpp_limits()
2508 		    limits->max_lane_count,  in intel_dp_compute_config_link_bpp_limits()
2509 		    limits->max_rate,  in intel_dp_compute_config_link_bpp_limits()
2510 		    limits->pipe.max_bpp,  in intel_dp_compute_config_link_bpp_limits()
2511 		    FXP_Q4_ARGS(limits->link.max_bpp_x16));  in intel_dp_compute_config_link_bpp_limits()
2524 	limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);  in intel_dp_dsc_compute_pipe_bpp_limits()
2525 	limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);  in intel_dp_dsc_compute_pipe_bpp_limits()
2537 	limits->min_rate = intel_dp_min_link_rate(intel_dp);  in intel_dp_compute_config_limits()
2538 	limits->max_rate = intel_dp_max_link_rate(intel_dp);  in intel_dp_compute_config_limits()
2542 		limits->max_rate = min(limits->max_rate, 810000);  in intel_dp_compute_config_limits()
2543 	limits->min_rate = min(limits->min_rate, limits->max_rate);  in intel_dp_compute_config_limits()
2545 	limits->min_lane_count = intel_dp_min_lane_count(intel_dp);  in intel_dp_compute_config_limits()
2546 	limits->max_lane_count = intel_dp_max_lane_count(intel_dp);  in intel_dp_compute_config_limits()
2548 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);  in intel_dp_compute_config_limits()
2558 		limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);  in intel_dp_compute_config_limits()
2560 		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,  in intel_dp_compute_config_limits()
2567 	if (is_mst || intel_dp->use_max_params) {  in intel_dp_compute_config_limits()
2569 		 * For MST we always configure max link bw - the spec doesn't  in intel_dp_compute_config_limits()
2579 		limits->min_lane_count = limits->max_lane_count;  in intel_dp_compute_config_limits()
2580 		limits->min_rate = limits->max_rate;  in intel_dp_compute_config_limits()
2586 						       intel_dp->attached_connector,  in intel_dp_compute_config_limits()
2595 		&crtc_state->hw.adjusted_mode;  in intel_dp_config_required_rate()
2596 	int bpp = crtc_state->dsc.compression_enable ?  in intel_dp_config_required_rate()
2597 		fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :  in intel_dp_config_required_rate()
2598 		crtc_state->pipe_bpp;  in intel_dp_config_required_rate()
2600 	return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);  in intel_dp_config_required_rate()
2623 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_dp_compute_link_config()
2624 	struct intel_connector *connector =  in intel_dp_compute_link_config()  local
2625 		to_intel_connector(conn_state->connector);  in intel_dp_compute_link_config()
2627 		&pipe_config->hw.adjusted_mode;  in intel_dp_compute_link_config()
2634 	if (pipe_config->fec_enable &&  in intel_dp_compute_link_config()
2635 	    !intel_dp_supports_fec(intel_dp, connector, pipe_config))  in intel_dp_compute_link_config()
2636 		return -EINVAL;  in intel_dp_compute_link_config()
2638 	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,  in intel_dp_compute_link_config()
2639 						     adjusted_mode->crtc_hdisplay,  in intel_dp_compute_link_config()
2640 						     adjusted_mode->crtc_clock);  in intel_dp_compute_link_config()
2642 		pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);  in intel_dp_compute_link_config()
2646 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||  in intel_dp_compute_link_config()
2662 							     pipe_config->pipe_bpp,  in intel_dp_compute_link_config()
2663 							     pipe_config->pipe_bpp,  in intel_dp_compute_link_config()
2670 	if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {  in intel_dp_compute_link_config()
2671 		drm_dbg_kms(display->drm, "DSC required but not available\n");  in intel_dp_compute_link_config()
2672 		return -EINVAL;  in intel_dp_compute_link_config()
2676 		drm_dbg_kms(display->drm,  in intel_dp_compute_link_config()
2679 			    str_yes_no(intel_dp->force_dsc_en));  in intel_dp_compute_link_config()
2685 			return -EINVAL;  in intel_dp_compute_link_config()
2693 	drm_dbg_kms(display->drm,  in intel_dp_compute_link_config()
2694 …"DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available …  in intel_dp_compute_link_config()
2695 		    pipe_config->lane_count, pipe_config->port_clock,  in intel_dp_compute_link_config()
2696 		    pipe_config->pipe_bpp,  in intel_dp_compute_link_config()
2697 		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),  in intel_dp_compute_link_config()
2700 						pipe_config->port_clock,  in intel_dp_compute_link_config()
2701 						pipe_config->lane_count));  in intel_dp_compute_link_config()
2712 		&crtc_state->hw.adjusted_mode;  in intel_dp_limited_color_range()
2716 	 * crtc_state->limited_color_range only applies to RGB,  in intel_dp_limited_color_range()
2721 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in intel_dp_limited_color_range()
2724 	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {  in intel_dp_limited_color_range()
2727 		 * CEA-861-E - 5.1 Default Encoding Parameters  in intel_dp_limited_color_range()
2728 		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry  in intel_dp_limited_color_range()
2730 		return crtc_state->pipe_bpp != 18 &&  in intel_dp_limited_color_range()
2734 		return intel_conn_state->broadcast_rgb ==  in intel_dp_limited_color_range()
2741 	if (display->platform.g4x)  in intel_dp_port_has_audio()
2755 	if (crtc_state->has_panel_replay) {  in intel_dp_compute_vsc_colorimetry()
2757 		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223  in intel_dp_compute_vsc_colorimetry()
2761 		vsc->revision = 0x7;  in intel_dp_compute_vsc_colorimetry()
2764 		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118  in intel_dp_compute_vsc_colorimetry()
2768 		vsc->revision = 0x5;  in intel_dp_compute_vsc_colorimetry()
2771 	vsc->length = 0x13;  in intel_dp_compute_vsc_colorimetry()
2773 	/* DP 1.4a spec, Table 2-120 */  in intel_dp_compute_vsc_colorimetry()
2774 	switch (crtc_state->output_format) {  in intel_dp_compute_vsc_colorimetry()
2776 		vsc->pixelformat = DP_PIXELFORMAT_YUV444;  in intel_dp_compute_vsc_colorimetry()
2779 		vsc->pixelformat = DP_PIXELFORMAT_YUV420;  in intel_dp_compute_vsc_colorimetry()
2783 		vsc->pixelformat = DP_PIXELFORMAT_RGB;  in intel_dp_compute_vsc_colorimetry()
2786 	switch (conn_state->colorspace) {  in intel_dp_compute_vsc_colorimetry()
2788 		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;  in intel_dp_compute_vsc_colorimetry()
2791 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;  in intel_dp_compute_vsc_colorimetry()
2794 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;  in intel_dp_compute_vsc_colorimetry()
2797 		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;  in intel_dp_compute_vsc_colorimetry()
2800 		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;  in intel_dp_compute_vsc_colorimetry()
2803 		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;  in intel_dp_compute_vsc_colorimetry()
2806 		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;  in intel_dp_compute_vsc_colorimetry()
2809 		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;  in intel_dp_compute_vsc_colorimetry()
2813 		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;  in intel_dp_compute_vsc_colorimetry()
2817 		 * RGB->YCBCR color conversion uses the BT.709  in intel_dp_compute_vsc_colorimetry()
2820 		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in intel_dp_compute_vsc_colorimetry()
2821 			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;  in intel_dp_compute_vsc_colorimetry()
2823 			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;  in intel_dp_compute_vsc_colorimetry()
2827 	vsc->bpc = crtc_state->pipe_bpp / 3;  in intel_dp_compute_vsc_colorimetry()
2830 	drm_WARN_ON(display->drm,  in intel_dp_compute_vsc_colorimetry()
2831 		    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);  in intel_dp_compute_vsc_colorimetry()
2834 	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;  in intel_dp_compute_vsc_colorimetry()
2835 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;  in intel_dp_compute_vsc_colorimetry()
2841 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;  in intel_dp_compute_as_sdp()
2843 		&crtc_state->hw.adjusted_mode;  in intel_dp_compute_as_sdp()
2845 	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)  in intel_dp_compute_as_sdp()
2848 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);  in intel_dp_compute_as_sdp()
2850 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;  in intel_dp_compute_as_sdp()
2851 	as_sdp->length = 0x9;  in intel_dp_compute_as_sdp()
2852 	as_sdp->duration_incr_ms = 0;  in intel_dp_compute_as_sdp()
2854 	if (crtc_state->cmrr.enable) {  in intel_dp_compute_as_sdp()
2855 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;  in intel_dp_compute_as_sdp()
2856 		as_sdp->vtotal = adjusted_mode->vtotal;  in intel_dp_compute_as_sdp()
2857 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);  in intel_dp_compute_as_sdp()
2858 		as_sdp->target_rr_divider = true;  in intel_dp_compute_as_sdp()
2860 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;  in intel_dp_compute_as_sdp()
2861 		as_sdp->vtotal = adjusted_mode->vtotal;  in intel_dp_compute_as_sdp()
2862 		as_sdp->target_rr = 0;  in intel_dp_compute_as_sdp()
2872 	if ((!intel_dp->colorimetry_support ||  in intel_dp_compute_vsc_sdp()
2874 	    !crtc_state->has_psr)  in intel_dp_compute_vsc_sdp()
2877 	vsc = &crtc_state->infoframes.vsc;  in intel_dp_compute_vsc_sdp()
2879 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);  in intel_dp_compute_vsc_sdp()
2880 	vsc->sdp_type = DP_SDP_VSC;  in intel_dp_compute_vsc_sdp()
2886 	} else if (crtc_state->has_panel_replay) {  in intel_dp_compute_vsc_sdp()
2889 		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223  in intel_dp_compute_vsc_sdp()
2892 		vsc->revision = 0x6;  in intel_dp_compute_vsc_sdp()
2893 		vsc->length = 0x10;  in intel_dp_compute_vsc_sdp()
2894 	} else if (crtc_state->has_sel_update) {  in intel_dp_compute_vsc_sdp()
2897 		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11  in intel_dp_compute_vsc_sdp()
2898 		 * 3D stereo + PSR/PSR2 + Y-coordinate.  in intel_dp_compute_vsc_sdp()
2900 		vsc->revision = 0x4;  in intel_dp_compute_vsc_sdp()
2901 		vsc->length = 0xe;  in intel_dp_compute_vsc_sdp()
2905 		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118  in intel_dp_compute_vsc_sdp()
2909 		vsc->revision = 0x2;  in intel_dp_compute_vsc_sdp()
2910 		vsc->length = 0x8;  in intel_dp_compute_vsc_sdp()
2921 	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2923 	if (!conn_state->hdr_output_metadata)  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2929 		drm_dbg_kms(display->drm,  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2934 	crtc_state->infoframes.enable |=  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2938 static bool can_enable_drrs(struct intel_connector *connector,  in can_enable_drrs()  argument
2942 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in can_enable_drrs()
2944 	if (pipe_config->vrr.enable)  in can_enable_drrs()
2949 	 * as it allows more power-savings by complete shutting down display,  in can_enable_drrs()
2953 	if (pipe_config->has_psr)  in can_enable_drrs()
2957 	if (pipe_config->has_pch_encoder)  in can_enable_drrs()
2960 	if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))  in can_enable_drrs()
2964 		intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;  in can_enable_drrs()
2968 intel_dp_drrs_compute_config(struct intel_connector *connector,  in intel_dp_drrs_compute_config()  argument
2972 	struct intel_display *display = to_intel_display(connector);  in intel_dp_drrs_compute_config()
2973 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_drrs_compute_config()
2975 		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);  in intel_dp_drrs_compute_config()
2982 	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)  in intel_dp_drrs_compute_config()
2983 		pipe_config->update_m_n = true;  in intel_dp_drrs_compute_config()
2985 	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {  in intel_dp_drrs_compute_config()
2986 		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))  in intel_dp_drrs_compute_config()
2987 			intel_zero_m_n(&pipe_config->dp_m2_n2);  in intel_dp_drrs_compute_config()
2991 	if (display->platform.ironlake || display->platform.sandybridge ||  in intel_dp_drrs_compute_config()
2992 	    display->platform.ivybridge)  in intel_dp_drrs_compute_config()
2993 		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;  in intel_dp_drrs_compute_config()
2995 	pipe_config->has_drrs = true;  in intel_dp_drrs_compute_config()
2997 	pixel_clock = downclock_mode->clock;  in intel_dp_drrs_compute_config()
2998 	if (pipe_config->splitter.enable)  in intel_dp_drrs_compute_config()
2999 		pixel_clock /= pipe_config->splitter.link_count;  in intel_dp_drrs_compute_config()
3001 	intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,  in intel_dp_drrs_compute_config()
3002 			       pipe_config->port_clock,  in intel_dp_drrs_compute_config()
3003 			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),  in intel_dp_drrs_compute_config()
3004 			       &pipe_config->dp_m2_n2);  in intel_dp_drrs_compute_config()
3007 	if (pipe_config->splitter.enable)  in intel_dp_drrs_compute_config()
3008 		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;  in intel_dp_drrs_compute_config()
3017 	struct intel_connector *connector =  in intel_dp_has_audio()  local
3018 		to_intel_connector(conn_state->connector);  in intel_dp_has_audio()
3020 	if (!intel_dp_port_has_audio(display, encoder->port))  in intel_dp_has_audio()
3023 	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)  in intel_dp_has_audio()
3024 		return connector->base.display_info.has_audio;  in intel_dp_has_audio()
3026 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;  in intel_dp_has_audio()
3037 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_compute_output_format()  local
3038 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_compute_output_format()
3039 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_dp_compute_output_format()
3045 	if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {  in intel_dp_compute_output_format()
3046 		drm_dbg_kms(display->drm,  in intel_dp_compute_output_format()
3048 		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;  in intel_dp_compute_output_format()
3050 		crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);  in intel_dp_compute_output_format()
3053 	crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);  in intel_dp_compute_output_format()
3058 		if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in intel_dp_compute_output_format()
3059 		    !connector->base.ycbcr_420_allowed ||  in intel_dp_compute_output_format()
3063 		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;  in intel_dp_compute_output_format()
3064 		crtc_state->output_format = intel_dp_output_format(connector,  in intel_dp_compute_output_format()
3065 								   crtc_state->sink_format);  in intel_dp_compute_output_format()
3078 	pipe_config->has_audio =  in intel_dp_audio_compute_config()
3082 	pipe_config->sdp_split_enable = pipe_config->has_audio &&  in intel_dp_audio_compute_config()
3086 static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector)  in intel_dp_queue_modeset_retry_work()  argument
3088 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_queue_modeset_retry_work()
3090 	drm_connector_get(&connector->base);  in intel_dp_queue_modeset_retry_work()
3091 	if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))  in intel_dp_queue_modeset_retry_work()
3092 		drm_connector_put(&connector->base);  in intel_dp_queue_modeset_retry_work()
3100 	struct intel_connector *connector;  in intel_dp_queue_modeset_retry_for_link()  local
3105 	if (intel_dp->needs_modeset_retry)  in intel_dp_queue_modeset_retry_for_link()
3108 	intel_dp->needs_modeset_retry = true;  in intel_dp_queue_modeset_retry_for_link()
3111 		intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);  in intel_dp_queue_modeset_retry_for_link()
3116 	for_each_new_intel_connector_in_state(state, connector, conn_state, i) {  in intel_dp_queue_modeset_retry_for_link()
3117 		if (!conn_state->base.crtc)  in intel_dp_queue_modeset_retry_for_link()
3120 		if (connector->mst_port == intel_dp)  in intel_dp_queue_modeset_retry_for_link()
3121 			intel_dp_queue_modeset_retry_work(connector);  in intel_dp_queue_modeset_retry_for_link()
3131 	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);  in intel_dp_compute_config()
3132 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_dp_compute_config()
3135 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_compute_config()  local
3138 	fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);  in intel_dp_compute_config()
3140 		ret = intel_panel_compute_config(connector, adjusted_mode);  in intel_dp_compute_config()
3145 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)  in intel_dp_compute_config()
3146 		return -EINVAL;  in intel_dp_compute_config()
3148 	if (!connector->base.interlace_allowed &&  in intel_dp_compute_config()
3149 	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)  in intel_dp_compute_config()
3150 		return -EINVAL;  in intel_dp_compute_config()
3152 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)  in intel_dp_compute_config()
3153 		return -EINVAL;  in intel_dp_compute_config()
3155 	if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))  in intel_dp_compute_config()
3156 		return -EINVAL;  in intel_dp_compute_config()
3169 	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {  in intel_dp_compute_config()
3175 	pipe_config->limited_color_range =  in intel_dp_compute_config()
3180 		pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;  in intel_dp_compute_config()
3182 		pipe_config->enhanced_framing =  in intel_dp_compute_config()
3183 			drm_dp_enhanced_frame_cap(intel_dp->dpcd);  in intel_dp_compute_config()
3186 	if (pipe_config->dsc.compression_enable)  in intel_dp_compute_config()
3187 		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;  in intel_dp_compute_config()
3189 		link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,  in intel_dp_compute_config()
3190 								   pipe_config->pipe_bpp));  in intel_dp_compute_config()
3192 	if (intel_dp->mso_link_count) {  in intel_dp_compute_config()
3193 		int n = intel_dp->mso_link_count;  in intel_dp_compute_config()
3194 		int overlap = intel_dp->mso_pixel_overlap;  in intel_dp_compute_config()
3196 		pipe_config->splitter.enable = true;  in intel_dp_compute_config()
3197 		pipe_config->splitter.link_count = n;  in intel_dp_compute_config()
3198 		pipe_config->splitter.pixel_overlap = overlap;  in intel_dp_compute_config()
3200 		drm_dbg_kms(display->drm,  in intel_dp_compute_config()
3204 		adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;  in intel_dp_compute_config()
3205 		adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;  in intel_dp_compute_config()
3206 		adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;  in intel_dp_compute_config()
3207 		adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;  in intel_dp_compute_config()
3208 		adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;  in intel_dp_compute_config()
3209 		adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;  in intel_dp_compute_config()
3210 		adjusted_mode->crtc_clock /= n;  in intel_dp_compute_config()
3217 				       pipe_config->lane_count,  in intel_dp_compute_config()
3218 				       adjusted_mode->crtc_clock,  in intel_dp_compute_config()
3219 				       pipe_config->port_clock,  in intel_dp_compute_config()
3220 				       intel_dp_bw_fec_overhead(pipe_config->fec_enable),  in intel_dp_compute_config()
3221 				       &pipe_config->dp_m_n);  in intel_dp_compute_config()
3225 	if (pipe_config->splitter.enable)  in intel_dp_compute_config()
3226 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;  in intel_dp_compute_config()
3232 	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);  in intel_dp_compute_config()
3236 	return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,  in intel_dp_compute_config()
3243 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));  in intel_dp_set_link_params()
3244 	intel_dp->link_trained = false;  in intel_dp_set_link_params()
3245 	intel_dp->needs_modeset_retry = false;  in intel_dp_set_link_params()
3246 	intel_dp->link_rate = link_rate;  in intel_dp_set_link_params()
3247 	intel_dp->lane_count = lane_count;  in intel_dp_set_link_params()
3252 	intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);  in intel_dp_reset_link_params()
3253 	intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);  in intel_dp_reset_link_params()
3254 	intel_dp->link.mst_probed_lane_count = 0;  in intel_dp_reset_link_params()
3255 	intel_dp->link.mst_probed_rate = 0;  in intel_dp_reset_link_params()
3256 	intel_dp->link.retrain_disabled = false;  in intel_dp_reset_link_params()
3257 	intel_dp->link.seq_train_failures = 0;  in intel_dp_reset_link_params()
3265 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));  in intel_edp_backlight_on()
3270 	drm_dbg_kms(display->drm, "\n");  in intel_edp_backlight_on()
3279 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));  in intel_edp_backlight_off()
3285 	drm_dbg_kms(display->drm, "\n");  in intel_edp_backlight_off()
3301 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&  in downstream_hpd_needs_d0()
3302 		drm_dp_is_branch(intel_dp->dpcd) &&  in downstream_hpd_needs_d0()
3303 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;  in downstream_hpd_needs_d0()
3325 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,  in intel_dp_sink_set_dsc_decompression()  argument
3328 	struct intel_display *display = to_intel_display(connector);  in intel_dp_sink_set_dsc_decompression()
3330 	if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,  in intel_dp_sink_set_dsc_decompression()
3332 		drm_dbg_kms(display->drm,  in intel_dp_sink_set_dsc_decompression()
3338 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,  in intel_dp_sink_set_dsc_passthrough()  argument
3341 	struct intel_display *display = to_intel_display(connector);  in intel_dp_sink_set_dsc_passthrough()
3342 	struct drm_dp_aux *aux = connector->port ?  in intel_dp_sink_set_dsc_passthrough()
3343 				 connector->port->passthrough_aux : NULL;  in intel_dp_sink_set_dsc_passthrough()
3350 		drm_dbg_kms(display->drm,  in intel_dp_sink_set_dsc_passthrough()
3356 				      const struct intel_connector *connector,  in intel_dp_dsc_aux_ref_count()  argument
3367 	 * On SST the decompression AUX device won't be shared, each connector  in intel_dp_dsc_aux_ref_count()
3370 	if (!connector->mst_port)  in intel_dp_dsc_aux_ref_count()
3371 		return connector->dp.dsc_decompression_enabled ? 1 : 0;  in intel_dp_dsc_aux_ref_count()
3373 	for_each_oldnew_connector_in_state(&state->base, _connector_iter,  in intel_dp_dsc_aux_ref_count()
3378 		if (connector_iter->mst_port != connector->mst_port)  in intel_dp_dsc_aux_ref_count()
3381 		if (!connector_iter->dp.dsc_decompression_enabled)  in intel_dp_dsc_aux_ref_count()
3384 		drm_WARN_ON(display->drm,  in intel_dp_dsc_aux_ref_count()
3385 			    (for_get_ref && !new_conn_state->crtc) ||  in intel_dp_dsc_aux_ref_count()
3386 			    (!for_get_ref && !old_conn_state->crtc));  in intel_dp_dsc_aux_ref_count()
3388 		if (connector_iter->dp.dsc_decompression_aux ==  in intel_dp_dsc_aux_ref_count()
3389 		    connector->dp.dsc_decompression_aux)  in intel_dp_dsc_aux_ref_count()
3397 				     struct intel_connector *connector)  in intel_dp_dsc_aux_get_ref()  argument
3399 	bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;  in intel_dp_dsc_aux_get_ref()
3401 	connector->dp.dsc_decompression_enabled = true;  in intel_dp_dsc_aux_get_ref()
3407 				     struct intel_connector *connector)  in intel_dp_dsc_aux_put_ref()  argument
3409 	connector->dp.dsc_decompression_enabled = false;  in intel_dp_dsc_aux_put_ref()
3411 	return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;  in intel_dp_dsc_aux_put_ref()
3415  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3417  * @connector: connector to enable the decompression for
3418  * @new_crtc_state: new state for the CRTC driving @connector
3428 					struct intel_connector *connector,  in intel_dp_sink_enable_decompression()  argument
3433 	if (!new_crtc_state->dsc.compression_enable)  in intel_dp_sink_enable_decompression()
3436 	if (drm_WARN_ON(display->drm,  in intel_dp_sink_enable_decompression()
3437 			!connector->dp.dsc_decompression_aux ||  in intel_dp_sink_enable_decompression()
3438 			connector->dp.dsc_decompression_enabled))  in intel_dp_sink_enable_decompression()
3441 	if (!intel_dp_dsc_aux_get_ref(state, connector))  in intel_dp_sink_enable_decompression()
3444 	intel_dp_sink_set_dsc_passthrough(connector, true);  in intel_dp_sink_enable_decompression()
3445 	intel_dp_sink_set_dsc_decompression(connector, true);  in intel_dp_sink_enable_decompression()
3449  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3451  * @connector: connector to disable the decompression for
3452  * @old_crtc_state: old state for the CRTC driving @connector
3459 					 struct intel_connector *connector,  in intel_dp_sink_disable_decompression()  argument
3464 	if (!old_crtc_state->dsc.compression_enable)  in intel_dp_sink_disable_decompression()
3467 	if (drm_WARN_ON(display->drm,  in intel_dp_sink_disable_decompression()
3468 			!connector->dp.dsc_decompression_aux ||  in intel_dp_sink_disable_decompression()
3469 			!connector->dp.dsc_decompression_enabled))  in intel_dp_sink_disable_decompression()
3472 	if (!intel_dp_dsc_aux_put_ref(state, connector))  in intel_dp_sink_disable_decompression()
3475 	intel_dp_sink_set_dsc_decompression(connector, false);  in intel_dp_sink_disable_decompression()
3476 	intel_dp_sink_set_dsc_passthrough(connector, false);  in intel_dp_sink_disable_decompression()
3486 	if (READ_ONCE(intel_dp->oui_valid))  in intel_dp_init_source_oui()
3489 	WRITE_ONCE(intel_dp->oui_valid, true);  in intel_dp_init_source_oui()
3495 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)  in intel_dp_init_source_oui()
3496 		drm_dbg_kms(display->drm, "Failed to read source OUI\n");  in intel_dp_init_source_oui()
3500 		intel_dp->last_oui_write = jiffies;  in intel_dp_init_source_oui()
3504 	if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {  in intel_dp_init_source_oui()
3505 		drm_dbg_kms(display->drm, "Failed to write source OUI\n");  in intel_dp_init_source_oui()
3506 		WRITE_ONCE(intel_dp->oui_valid, false);  in intel_dp_init_source_oui()
3509 	intel_dp->last_oui_write = jiffies;  in intel_dp_init_source_oui()
3514 	WRITE_ONCE(intel_dp->oui_valid, false);  in intel_dp_invalidate_source_oui()
3520 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_wait_source_oui()  local
3522 	drm_dbg_kms(display->drm,  in intel_dp_wait_source_oui()
3523 		    "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",  in intel_dp_wait_source_oui()
3524 		    connector->base.base.id, connector->base.name,  in intel_dp_wait_source_oui()
3525 		    connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);  in intel_dp_wait_source_oui()
3527 	wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,  in intel_dp_wait_source_oui()
3528 				       connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);  in intel_dp_wait_source_oui()
3535 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_set_power()
3539 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_set_power()
3546 		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);  in intel_dp_set_power()
3560 			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);  in intel_dp_set_power()
3566 		if (ret == 1 && lspcon->active)  in intel_dp_set_power()
3571 		drm_dbg_kms(display->drm,  in intel_dp_set_power()
3573 			    encoder->base.base.id, encoder->base.name,  in intel_dp_set_power()
3581  * intel_dp_sync_state - sync the encoder state during init/resume
3598 	if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {  in intel_dp_sync_state()
3607 		intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);  in intel_dp_sync_state()
3608 		intel_dp->link_trained = true;  in intel_dp_sync_state()
3620 	 * If BIOS has set an unsupported or non-standard link rate for some  in intel_dp_initial_fastset_check()
3623 	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,  in intel_dp_initial_fastset_check()
3624 				crtc_state->port_clock) < 0) {  in intel_dp_initial_fastset_check()
3625 		drm_dbg_kms(display->drm,  in intel_dp_initial_fastset_check()
3627 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3628 		crtc_state->uapi.connectors_changed = true;  in intel_dp_initial_fastset_check()
3636 	 * of crtc_state->dsc, we have no way to ensure reliable fastset.  in intel_dp_initial_fastset_check()
3639 	if (crtc_state->dsc.compression_enable) {  in intel_dp_initial_fastset_check()
3640 		drm_dbg_kms(display->drm,  in intel_dp_initial_fastset_check()
3642 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3643 		crtc_state->uapi.mode_changed = true;  in intel_dp_initial_fastset_check()
3648 		drm_dbg_kms(display->drm,  in intel_dp_initial_fastset_check()
3650 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3651 		crtc_state->uapi.mode_changed = true;  in intel_dp_initial_fastset_check()
3664 	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));  in intel_dp_get_pcon_dsc_cap()
3666 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,  in intel_dp_get_pcon_dsc_cap()
3667 			     intel_dp->pcon_dsc_dpcd,  in intel_dp_get_pcon_dsc_cap()
3668 			     sizeof(intel_dp->pcon_dsc_dpcd)) < 0)  in intel_dp_get_pcon_dsc_cap()
3669 		drm_err(display->drm, "Failed to read DPCD register 0x%x\n",  in intel_dp_get_pcon_dsc_cap()
3672 	drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",  in intel_dp_get_pcon_dsc_cap()
3673 		    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);  in intel_dp_get_pcon_dsc_cap()
3681 	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {  in intel_dp_pcon_get_frl_mask()
3710 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_hdmi_sink_max_frl()  local
3711 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_hdmi_sink_max_frl()
3716 	max_lanes = info->hdmi.max_lanes;  in intel_dp_hdmi_sink_max_frl()
3717 	rate_per_lane = info->hdmi.max_frl_rate_per_lane;  in intel_dp_hdmi_sink_max_frl()
3720 	if (info->hdmi.dsc_cap.v_1p2) {  in intel_dp_hdmi_sink_max_frl()
3721 		max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;  in intel_dp_hdmi_sink_max_frl()
3722 		dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;  in intel_dp_hdmi_sink_max_frl()
3734 	if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&  in intel_dp_pcon_is_frl_trained()
3735 	    drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&  in intel_dp_pcon_is_frl_trained()
3751 	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;  in intel_dp_pcon_start_frl_training()
3752 	drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);  in intel_dp_pcon_start_frl_training()
3755 	drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",  in intel_dp_pcon_start_frl_training()
3761 		return -EINVAL;  in intel_dp_pcon_start_frl_training()
3764 	drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);  in intel_dp_pcon_start_frl_training()
3769 	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);  in intel_dp_pcon_start_frl_training()
3773 	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);  in intel_dp_pcon_start_frl_training()
3776 		return -ETIMEDOUT;  in intel_dp_pcon_start_frl_training()
3778 	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,  in intel_dp_pcon_start_frl_training()
3782 	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,  in intel_dp_pcon_start_frl_training()
3786 	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);  in intel_dp_pcon_start_frl_training()
3798 		return -ETIMEDOUT;  in intel_dp_pcon_start_frl_training()
3801 	drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);  in intel_dp_pcon_start_frl_training()
3802 	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);  in intel_dp_pcon_start_frl_training()
3803 	intel_dp->frl.is_trained = true;  in intel_dp_pcon_start_frl_training()
3804 	drm_dbg(display->drm, "FRL trained with : %d Gbps\n",  in intel_dp_pcon_start_frl_training()
3805 		intel_dp->frl.trained_rate_gbps);  in intel_dp_pcon_start_frl_training()
3812 	if (drm_dp_is_branch(intel_dp->dpcd) &&  in intel_dp_is_hdmi_2_1_sink()
3829 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);  in intel_dp_pcon_set_tmds_mode()
3835 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);  in intel_dp_pcon_set_tmds_mode()
3848 	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)  in intel_dp_check_frl_training()
3849 	 * -sink is HDMI2.1  in intel_dp_check_frl_training()
3851 	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||  in intel_dp_check_frl_training()
3853 	    intel_dp->frl.is_trained)  in intel_dp_check_frl_training()
3859 		drm_dbg(display->drm,  in intel_dp_check_frl_training()
3862 		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);  in intel_dp_check_frl_training()
3865 			drm_dbg(display->drm,  in intel_dp_check_frl_training()
3868 		drm_dbg(display->drm, "FRL training Completed\n");  in intel_dp_check_frl_training()
3875 	int vactive = crtc_state->hw.adjusted_mode.vdisplay;  in intel_dp_pcon_dsc_enc_slice_height()
3884 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_enc_slices()  local
3885 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_pcon_dsc_enc_slices()
3886 	int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice;  in intel_dp_pcon_dsc_enc_slices()
3887 	int hdmi_max_slices = info->hdmi.dsc_cap.max_slices;  in intel_dp_pcon_dsc_enc_slices()
3888 	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_slices()
3889 	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_slices()
3901 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_enc_bpp()  local
3902 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_pcon_dsc_enc_bpp()
3903 	int output_format = crtc_state->output_format;  in intel_dp_pcon_dsc_enc_bpp()
3904 	bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp;  in intel_dp_pcon_dsc_enc_bpp()
3905 	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_bpp()
3907 		info->hdmi.dsc_cap.total_chunk_kbytes * 1024;  in intel_dp_pcon_dsc_enc_bpp()
3919 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_configure()  local
3932 	if (!connector)  in intel_dp_pcon_dsc_configure()
3935 	info = &connector->base.display_info;  in intel_dp_pcon_dsc_configure()
3937 	hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2;  in intel_dp_pcon_dsc_configure()
3939 	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||  in intel_dp_pcon_dsc_configure()
3951 	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,  in intel_dp_pcon_dsc_configure()
3966 	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);  in intel_dp_pcon_dsc_configure()
3968 		drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");  in intel_dp_pcon_dsc_configure()
3979 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)  in intel_dp_configure_protocol_converter()
3982 	if (!drm_dp_is_branch(intel_dp->dpcd))  in intel_dp_configure_protocol_converter()
3987 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_configure_protocol_converter()
3989 		drm_dbg_kms(display->drm,  in intel_dp_configure_protocol_converter()
3993 	if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {  in intel_dp_configure_protocol_converter()
3994 		switch (crtc_state->output_format) {  in intel_dp_configure_protocol_converter()
4005 			MISSING_CASE(crtc_state->output_format);  in intel_dp_configure_protocol_converter()
4008 	} else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {  in intel_dp_configure_protocol_converter()
4009 		switch (crtc_state->output_format) {  in intel_dp_configure_protocol_converter()
4016 			MISSING_CASE(crtc_state->output_format);  in intel_dp_configure_protocol_converter()
4023 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_configure_protocol_converter()
4025 		drm_dbg_kms(display->drm,  in intel_dp_configure_protocol_converter()
4027 			    str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));  in intel_dp_configure_protocol_converter()
4031 	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)  in intel_dp_configure_protocol_converter()
4032 		drm_dbg_kms(display->drm,  in intel_dp_configure_protocol_converter()
4033 			    "Failed to %s protocol converter RGB->YCbCr conversion mode\n",  in intel_dp_configure_protocol_converter()
4041 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,  in intel_dp_get_colorimetry_status()
4052 		drm_err(aux->drm_dev,  in intel_dp_read_dsc_dpcd()
4058 	drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",  in intel_dp_read_dsc_dpcd()
4063 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)  in intel_dp_get_dsc_sink_cap()  argument
4065 	struct intel_display *display = to_intel_display(connector);  in intel_dp_get_dsc_sink_cap()
4071 	memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));  in intel_dp_get_dsc_sink_cap()
4074 	connector->dp.fec_capability = 0;  in intel_dp_get_dsc_sink_cap()
4079 	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,  in intel_dp_get_dsc_sink_cap()
4080 			       connector->dp.dsc_dpcd);  in intel_dp_get_dsc_sink_cap()
4082 	if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,  in intel_dp_get_dsc_sink_cap()
4083 			      &connector->dp.fec_capability) < 0) {  in intel_dp_get_dsc_sink_cap()
4084 		drm_err(display->drm, "Failed to read FEC DPCD register\n");  in intel_dp_get_dsc_sink_cap()
4088 	drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",  in intel_dp_get_dsc_sink_cap()
4089 		    connector->dp.fec_capability);  in intel_dp_get_dsc_sink_cap()
4092 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)  in intel_edp_get_dsc_sink_cap()  argument
4097 	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);  in intel_edp_get_dsc_sink_cap()
4101 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)  in intel_dp_detect_dsc_caps()  argument
4105 	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */  in intel_dp_detect_dsc_caps()
4110 		intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],  in intel_dp_detect_dsc_caps()
4111 					   connector);  in intel_dp_detect_dsc_caps()
4113 		intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],  in intel_dp_detect_dsc_caps()
4114 					  connector);  in intel_dp_detect_dsc_caps()
4117 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,  in intel_edp_mso_mode_fixup()  argument
4120 	struct intel_display *display = to_intel_display(connector);  in intel_edp_mso_mode_fixup()
4121 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_edp_mso_mode_fixup()
4122 	int n = intel_dp->mso_link_count;  in intel_edp_mso_mode_fixup()
4123 	int overlap = intel_dp->mso_pixel_overlap;  in intel_edp_mso_mode_fixup()
4128 	mode->hdisplay = (mode->hdisplay - overlap) * n;  in intel_edp_mso_mode_fixup()
4129 	mode->hsync_start = (mode->hsync_start - overlap) * n;  in intel_edp_mso_mode_fixup()
4130 	mode->hsync_end = (mode->hsync_end - overlap) * n;  in intel_edp_mso_mode_fixup()
4131 	mode->htotal = (mode->htotal - overlap) * n;  in intel_edp_mso_mode_fixup()
4132 	mode->clock *= n;  in intel_edp_mso_mode_fixup()
4136 	drm_dbg_kms(display->drm,  in intel_edp_mso_mode_fixup()
4137 		    "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",  in intel_edp_mso_mode_fixup()
4138 		    connector->base.base.id, connector->base.name,  in intel_edp_mso_mode_fixup()
4146 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_fixup_vbt_bpp()  local
4148 	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {  in intel_edp_fixup_vbt_bpp()
4162 		drm_dbg_kms(display->drm,  in intel_edp_fixup_vbt_bpp()
4163 			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",  in intel_edp_fixup_vbt_bpp()
4164 			    pipe_bpp, connector->panel.vbt.edp.bpp);  in intel_edp_fixup_vbt_bpp()
4165 		connector->panel.vbt.edp.bpp = pipe_bpp;  in intel_edp_fixup_vbt_bpp()
4172 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_mso_init()  local
4173 	struct drm_display_info *info = &connector->base.display_info;  in intel_edp_mso_init()
4176 	if (intel_dp->edp_dpcd[0] < DP_EDP_14)  in intel_edp_mso_init()
4179 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {  in intel_edp_mso_init()
4180 		drm_err(display->drm, "Failed to read MSO cap\n");  in intel_edp_mso_init()
4186 	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {  in intel_edp_mso_init()
4187 		drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);  in intel_edp_mso_init()
4192 		drm_dbg_kms(display->drm,  in intel_edp_mso_init()
4194 			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,  in intel_edp_mso_init()
4195 			    info->mso_pixel_overlap);  in intel_edp_mso_init()
4197 			drm_err(display->drm,  in intel_edp_mso_init()
4203 	intel_dp->mso_link_count = mso;  in intel_edp_mso_init()
4204 	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;  in intel_edp_mso_init()
4211 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_edp_set_sink_rates()
4213 	intel_dp->num_sink_rates = 0;  in intel_edp_set_sink_rates()
4215 	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {  in intel_edp_set_sink_rates()
4219 		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,  in intel_edp_set_sink_rates()
4225 			/* Value read multiplied by 200kHz gives the per-lane  in intel_edp_set_sink_rates()
4241 			if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {  in intel_edp_set_sink_rates()
4242 				drm_dbg_kms(display->drm,  in intel_edp_set_sink_rates()
4244 					    encoder->base.base.id, encoder->base.name);  in intel_edp_set_sink_rates()
4248 			intel_dp->sink_rates[i] = rate;  in intel_edp_set_sink_rates()
4250 		intel_dp->num_sink_rates = i;  in intel_edp_set_sink_rates()
4257 	if (intel_dp->num_sink_rates)  in intel_edp_set_sink_rates()
4258 		intel_dp->use_rate_select = true;  in intel_edp_set_sink_rates()
4264 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)  in intel_edp_init_dpcd()  argument
4269 	drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);  in intel_edp_init_dpcd()
4271 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)  in intel_edp_init_dpcd()
4274 	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,  in intel_edp_init_dpcd()
4275 			 drm_dp_is_branch(intel_dp->dpcd));  in intel_edp_init_dpcd()
4276 	intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);  in intel_edp_init_dpcd()
4278 	intel_dp->colorimetry_support =  in intel_edp_init_dpcd()
4290 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,  in intel_edp_init_dpcd()
4291 			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==  in intel_edp_init_dpcd()
4292 			     sizeof(intel_dp->edp_dpcd)) {  in intel_edp_init_dpcd()
4293 		drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",  in intel_edp_init_dpcd()
4294 			    (int)sizeof(intel_dp->edp_dpcd),  in intel_edp_init_dpcd()
4295 			    intel_dp->edp_dpcd);  in intel_edp_init_dpcd()
4297 		intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;  in intel_edp_init_dpcd()
4301 	 * If needed, program our source OUI so we can make various Intel-specific AUX services  in intel_edp_init_dpcd()
4307 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks  in intel_edp_init_dpcd()
4308 	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]  in intel_edp_init_dpcd()
4316 	intel_dp_detect_dsc_caps(intel_dp, connector);  in intel_edp_init_dpcd()
4324 	if (!intel_dp->attached_connector)  in intel_dp_has_sink_count()
4327 	return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,  in intel_dp_has_sink_count()
4328 					  intel_dp->dpcd,  in intel_dp_has_sink_count()
4329 					  &intel_dp->desc);  in intel_dp_has_sink_count()
4348 	 * Don't clobber cached eDP rates. Also skip re-reading  in intel_dp_get_dpcd()
4352 		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,  in intel_dp_get_dpcd()
4353 				 drm_dp_is_branch(intel_dp->dpcd));  in intel_dp_get_dpcd()
4355 		intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);  in intel_dp_get_dpcd()
4357 		intel_dp->colorimetry_support =  in intel_dp_get_dpcd()
4364 		ret = drm_dp_read_sink_count(&intel_dp->aux);  in intel_dp_get_dpcd()
4373 		intel_dp->sink_count = ret;  in intel_dp_get_dpcd()
4382 		if (!intel_dp->sink_count)  in intel_dp_get_dpcd()
4386 	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,  in intel_dp_get_dpcd()
4387 					   intel_dp->downstream_ports) == 0;  in intel_dp_get_dpcd()
4406 	if (!display->params.enable_dp_mst)  in intel_dp_mst_mode_choose()
4413 	    !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))  in intel_dp_mst_mode_choose()
4423 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_mst_detect()
4427 	sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);  in intel_dp_mst_detect()
4431 	drm_dbg_kms(display->drm,  in intel_dp_mst_detect()
4432 		    "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",  in intel_dp_mst_detect()
4433 		    encoder->base.base.id, encoder->base.name,  in intel_dp_mst_detect()
4436 		    str_yes_no(display->params.enable_dp_mst),  in intel_dp_mst_detect()
4448 	intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;  in intel_dp_mst_configure()
4450 	if (intel_dp->is_mst)  in intel_dp_mst_configure()
4453 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);  in intel_dp_mst_configure()
4456 	intel_dp->mst_detect = DRM_DP_SST;  in intel_dp_mst_configure()
4464 	if (!intel_dp->is_mst)  in intel_dp_mst_disconnect()
4467 	drm_dbg_kms(display->drm,  in intel_dp_mst_disconnect()
4469 		    intel_dp->is_mst, intel_dp->mst_mgr.mst_state);  in intel_dp_mst_disconnect()
4470 	intel_dp->is_mst = false;  in intel_dp_mst_disconnect()
4471 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);  in intel_dp_mst_disconnect()
4477 	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;  in intel_dp_get_sink_irq_esi()
4485 		if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,  in intel_dp_ack_sink_irq_esi()
4498 	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication  in intel_dp_needs_vsc_sdp()
4500 	 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.  in intel_dp_needs_vsc_sdp()
4502 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in intel_dp_needs_vsc_sdp()
4505 	switch (conn_state->colorspace) {  in intel_dp_needs_vsc_sdp()
4525 		return -ENOSPC;  in intel_dp_as_sdp_pack()
4530 	sdp->sdp_header.HB0 = 0;  in intel_dp_as_sdp_pack()
4531 	sdp->sdp_header.HB1 = as_sdp->sdp_type;  in intel_dp_as_sdp_pack()
4532 	sdp->sdp_header.HB2 = 0x02;  in intel_dp_as_sdp_pack()
4533 	sdp->sdp_header.HB3 = as_sdp->length;  in intel_dp_as_sdp_pack()
4536 	sdp->db[0] = as_sdp->mode;  in intel_dp_as_sdp_pack()
4537 	sdp->db[1] = as_sdp->vtotal & 0xFF;  in intel_dp_as_sdp_pack()
4538 	sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;  in intel_dp_as_sdp_pack()
4539 	sdp->db[3] = as_sdp->target_rr & 0xFF;  in intel_dp_as_sdp_pack()
4540 	sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;  in intel_dp_as_sdp_pack()
4542 	if (as_sdp->target_rr_divider)  in intel_dp_as_sdp_pack()
4543 		sdp->db[4] |= 0x20;  in intel_dp_as_sdp_pack()
4560 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4566 		drm_dbg_kms(display->drm,  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4568 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4572 		drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4573 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4578 	 * Prepare VSC Header for SU as per DP 1.4a spec,  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4579 	 * Table 2-100 and Table 2-101  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4582 	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4583 	sdp->sdp_header.HB0 = 0;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4585 	 * Packet Type 80h + Non-audio INFOFRAME Type value  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4587 	 * - 80h + Non-audio INFOFRAME Type value  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4588 	 * - InfoFrame Type: 0x07  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4589 	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4591 	sdp->sdp_header.HB1 = drm_infoframe->type;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4594 	 * infoframe_size - 1  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4596 	sdp->sdp_header.HB2 = 0x1D;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4598 	sdp->sdp_header.HB3 = (0x13 << 2);  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4600 	sdp->db[0] = drm_infoframe->version;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4602 	sdp->db[1] = drm_infoframe->length;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4607 	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4608 	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4612 	 * Size of DP infoframe sdp packet for HDR static metadata consists of  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4613 	 * - DP SDP Header(struct dp_sdp_header): 4 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4614 	 * - Two Data Blocks: 2 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4617 	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4619 	 * Prior to GEN11's GMP register size is identical to DP HDR static metadata  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4635 	if ((crtc_state->infoframes.enable &  in intel_write_dp_sdp()
4641 		len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);  in intel_write_dp_sdp()
4645 							       &crtc_state->infoframes.drm.drm,  in intel_write_dp_sdp()
4649 		len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,  in intel_write_dp_sdp()
4657 	if (drm_WARN_ON(display->drm, len < 0))  in intel_write_dp_sdp()
4660 	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);  in intel_write_dp_sdp()
4669 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);  in intel_dp_set_infoframes()
4687 	if (!enable || !crtc_state->has_psr)  in intel_dp_set_infoframes()
4709 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4713 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_as_sdp_unpack()
4714 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4716 	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)  in intel_dp_as_sdp_unpack()
4717 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4719 	if (sdp->sdp_header.HB2 != 0x02)  in intel_dp_as_sdp_unpack()
4720 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4722 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)  in intel_dp_as_sdp_unpack()
4723 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4725 	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;  in intel_dp_as_sdp_unpack()
4726 	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;  in intel_dp_as_sdp_unpack()
4727 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];  in intel_dp_as_sdp_unpack()
4728 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);  in intel_dp_as_sdp_unpack()
4729 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;  in intel_dp_as_sdp_unpack()
4740 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4744 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_vsc_sdp_unpack()
4745 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4747 	if (sdp->sdp_header.HB1 != DP_SDP_VSC)  in intel_dp_vsc_sdp_unpack()
4748 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4750 	vsc->sdp_type = sdp->sdp_header.HB1;  in intel_dp_vsc_sdp_unpack()
4751 	vsc->revision = sdp->sdp_header.HB2;  in intel_dp_vsc_sdp_unpack()
4752 	vsc->length = sdp->sdp_header.HB3;  in intel_dp_vsc_sdp_unpack()
4754 	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||  in intel_dp_vsc_sdp_unpack()
4755 	    (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||  in intel_dp_vsc_sdp_unpack()
4756 	    (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {  in intel_dp_vsc_sdp_unpack()
4758 		 * - HB2 = 0x2, HB3 = 0x8  in intel_dp_vsc_sdp_unpack()
4760 		 * - HB2 = 0x4, HB3 = 0xe  in intel_dp_vsc_sdp_unpack()
4761 		 *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of  in intel_dp_vsc_sdp_unpack()
4764 		 * - HB2 = 0x6, HB3 = 0x10  in intel_dp_vsc_sdp_unpack()
4768 	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {  in intel_dp_vsc_sdp_unpack()
4770 		 * - HB2 = 0x5, HB3 = 0x13  in intel_dp_vsc_sdp_unpack()
4774 		vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;  in intel_dp_vsc_sdp_unpack()
4775 		vsc->colorimetry = sdp->db[16] & 0xf;  in intel_dp_vsc_sdp_unpack()
4776 		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;  in intel_dp_vsc_sdp_unpack()
4778 		switch (sdp->db[17] & 0x7) {  in intel_dp_vsc_sdp_unpack()
4780 			vsc->bpc = 6;  in intel_dp_vsc_sdp_unpack()
4783 			vsc->bpc = 8;  in intel_dp_vsc_sdp_unpack()
4786 			vsc->bpc = 10;  in intel_dp_vsc_sdp_unpack()
4789 			vsc->bpc = 12;  in intel_dp_vsc_sdp_unpack()
4792 			vsc->bpc = 16;  in intel_dp_vsc_sdp_unpack()
4795 			MISSING_CASE(sdp->db[17] & 0x7);  in intel_dp_vsc_sdp_unpack()
4796 			return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4799 		vsc->content_type = sdp->db[18] & 0x7;  in intel_dp_vsc_sdp_unpack()
4801 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4818 	if ((crtc_state->infoframes.enable &  in intel_read_dp_as_sdp()
4822 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,  in intel_read_dp_as_sdp()
4827 		drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");  in intel_read_dp_as_sdp()
4839 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4841 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4842 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4844 	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4845 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4851 	if (sdp->sdp_header.HB2 != 0x1D)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4852 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4855 	if ((sdp->sdp_header.HB3 & 0x3) != 0)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4856 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4859 	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4860 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4863 	if (sdp->db[0] != 1)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4864 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4867 	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4868 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4870 	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4886 	if ((crtc_state->infoframes.enable &  in intel_read_dp_vsc_sdp()
4890 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));  in intel_read_dp_vsc_sdp()
4895 		drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");  in intel_read_dp_vsc_sdp()
4908 	if ((crtc_state->infoframes.enable &  in intel_read_dp_hdr_metadata_infoframe_sdp()
4912 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,  in intel_read_dp_hdr_metadata_infoframe_sdp()
4919 		drm_dbg_kms(display->drm,  in intel_read_dp_hdr_metadata_infoframe_sdp()
4920 			    "Failed to unpack DP HDR Metadata Infoframe SDP\n");  in intel_read_dp_hdr_metadata_infoframe_sdp()
4930 				      &crtc_state->infoframes.vsc);  in intel_read_dp_sdp()
4934 							 &crtc_state->infoframes.drm.drm);  in intel_read_dp_sdp()
4938 				     &crtc_state->infoframes.as_sdp);  in intel_read_dp_sdp()
4950 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_link_ok()
4951 	bool uhbr = intel_dp->link_rate >= 1000000;  in intel_dp_link_ok()
4956 							  intel_dp->lane_count);  in intel_dp_link_ok()
4958 		ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);  in intel_dp_link_ok()
4964 	drm_dbg_kms(display->drm,  in intel_dp_link_ok()
4966 		    encoder->base.base.id, encoder->base.name,  in intel_dp_link_ok()
4977 	drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);  in intel_dp_mst_hpd_irq()
4980 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);  in intel_dp_mst_hpd_irq()
4988 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_mst_link_status()
4990 	const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;  in intel_dp_mst_link_status()
4992 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,  in intel_dp_mst_link_status()
4994 		drm_err(display->drm,  in intel_dp_mst_link_status()
4996 			encoder->base.base.id, encoder->base.name);  in intel_dp_mst_link_status()
5004  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
5005  * @intel_dp: Intel DP struct
5011  * - %true if pending interrupts were serviced (or no interrupts were
5013  * - %false if an error condition - like AUX failure or a loss of link - is
5014  *   detected, or another condition - like a DP tunnel BW state change - needs
5022 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_check_mst_status()
5026 	drm_WARN_ON_ONCE(display->drm, intel_dp->active_mst_links < 0);  in intel_dp_check_mst_status()
5033 			drm_dbg_kms(display->drm,  in intel_dp_check_mst_status()
5034 				    "failed to get ESI - device may have failed\n");  in intel_dp_check_mst_status()
5040 		drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);  in intel_dp_check_mst_status()
5042 		if (intel_dp->active_mst_links > 0 && link_ok &&  in intel_dp_check_mst_status()
5052 			if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,  in intel_dp_check_mst_status()
5053 						     &intel_dp->aux))  in intel_dp_check_mst_status()
5062 			drm_dbg_kms(display->drm, "Failed to ack ESI\n");  in intel_dp_check_mst_status()
5065 			drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);  in intel_dp_check_mst_status()
5068 	if (!link_ok || intel_dp->link.force_retrain)  in intel_dp_check_mst_status()
5080 	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);  in intel_dp_handle_hdmi_link_status_change()
5081 	if (intel_dp->frl.is_trained && !is_active) {  in intel_dp_handle_hdmi_link_status_change()
5082 		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)  in intel_dp_handle_hdmi_link_status_change()
5086 		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)  in intel_dp_handle_hdmi_link_status_change()
5089 		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);  in intel_dp_handle_hdmi_link_status_change()
5091 		intel_dp->frl.is_trained = false;  in intel_dp_handle_hdmi_link_status_change()
5103 	if (!intel_dp->link_trained)  in intel_dp_needs_link_retrain()
5107 	 * While PSR source HW is enabled, it will control main-link sending  in intel_dp_needs_link_retrain()
5117 	if (intel_dp->link.force_retrain)  in intel_dp_needs_link_retrain()
5120 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,  in intel_dp_needs_link_retrain()
5125 	 * Validate the cached values of intel_dp->link_rate and  in intel_dp_needs_link_retrain()
5126 	 * intel_dp->lane_count before attempting to retrain.  in intel_dp_needs_link_retrain()
5132 	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,  in intel_dp_needs_link_retrain()
5133 					intel_dp->lane_count))  in intel_dp_needs_link_retrain()
5136 	if (intel_dp->link.retrain_disabled)  in intel_dp_needs_link_retrain()
5139 	if (intel_dp->link.seq_train_failures)  in intel_dp_needs_link_retrain()
5154 	if (!conn_state->best_encoder)  in intel_dp_has_connector()
5158 	encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_has_connector()
5159 	if (conn_state->best_encoder == &encoder->base)  in intel_dp_has_connector()
5164 		encoder = &intel_dp->mst_encoders[pipe]->base;  in intel_dp_has_connector()
5165 		if (conn_state->best_encoder == &encoder->base)  in intel_dp_has_connector()
5174 	struct intel_connector *connector = to_intel_connector(conn_state->connector);  in wait_for_connector_hw_done()  local
5175 	struct intel_display *display = to_intel_display(connector);  in wait_for_connector_hw_done()
5177 	drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);  in wait_for_connector_hw_done()
5179 	if (!conn_state->commit)  in wait_for_connector_hw_done()
5182 	drm_WARN_ON(display->drm,  in wait_for_connector_hw_done()
5183 		    !wait_for_completion_timeout(&conn_state->commit->hw_done,  in wait_for_connector_hw_done()
5193 	struct intel_connector *connector;  in intel_dp_get_active_pipes()  local
5198 	drm_connector_list_iter_begin(display->drm, &conn_iter);  in intel_dp_get_active_pipes()
5199 	for_each_intel_connector_iter(connector, &conn_iter) {  in intel_dp_get_active_pipes()
5201 			connector->base.state;  in intel_dp_get_active_pipes()
5208 		crtc = to_intel_crtc(conn_state->crtc);  in intel_dp_get_active_pipes()
5212 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);  in intel_dp_get_active_pipes()
5216 		crtc_state = to_intel_crtc_state(crtc->base.state);  in intel_dp_get_active_pipes()
5218 		drm_WARN_ON(display->drm,  in intel_dp_get_active_pipes()
5221 		if (!crtc_state->hw.active)  in intel_dp_get_active_pipes()
5226 		*pipe_mask |= BIT(crtc->pipe);  in intel_dp_get_active_pipes()
5233 void intel_dp_flush_connector_commits(struct intel_connector *connector)  in intel_dp_flush_connector_commits()  argument
5235 	wait_for_connector_hw_done(connector->base.state);  in intel_dp_flush_connector_commits()
5240 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_is_connected()  local
5242 	return connector->base.status == connector_status_connected ||  in intel_dp_is_connected()
5243 		intel_dp->is_mst;  in intel_dp_is_connected()
5250 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_dp_retrain_link()
5258 	ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,  in intel_dp_retrain_link()
5276 	drm_dbg_kms(display->drm,  in intel_dp_retrain_link()
5278 		    encoder->base.base.id, encoder->base.name,  in intel_dp_retrain_link()
5279 		    str_yes_no(intel_dp->link.force_retrain));  in intel_dp_retrain_link()
5282 	if (ret == -EDEADLK)  in intel_dp_retrain_link()
5285 	intel_dp->link.force_retrain = false;  in intel_dp_retrain_link()
5288 		drm_dbg_kms(display->drm,  in intel_dp_retrain_link()
5290 			    encoder->base.base.id, encoder->base.name,  in intel_dp_retrain_link()
5308 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_check_link_state()
5324 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_check_device_service_irq()
5327 	if (drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_check_device_service_irq()
5331 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);  in intel_dp_check_device_service_irq()
5337 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);  in intel_dp_check_device_service_irq()
5340 		drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");  in intel_dp_check_device_service_irq()
5349 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_check_link_service_irq()
5352 	if (drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_check_link_service_irq()
5357 	    drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,  in intel_dp_check_link_service_irq()
5358 				     &intel_dp->aux))  in intel_dp_check_link_service_irq()
5361 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_check_link_service_irq()
5372  * According to DP spec
5377  *  4. Check link status on receipt of hot-plug interrupt
5379  * intel_dp_short_pulse -  handles short pulse interrupts
5387 	u8 old_sink_count = intel_dp->sink_count;  in intel_dp_short_pulse()
5401 	if ((old_sink_count != intel_dp->sink_count) || !ret) {  in intel_dp_short_pulse()
5410 	drm_dp_cec_irq(&intel_dp->aux);  in intel_dp_short_pulse()
5428 	u8 *dpcd = intel_dp->dpcd;  in intel_dp_detect_dpcd()
5431 	if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))  in intel_dp_detect_dpcd()
5439 	intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);  in intel_dp_detect_dpcd()
5445 	/* If we're HPD-aware, SINK_COUNT changes dynamically */  in intel_dp_detect_dpcd()
5447 	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {  in intel_dp_detect_dpcd()
5448 		return intel_dp->sink_count ?  in intel_dp_detect_dpcd()
5452 	if (intel_dp->mst_detect == DRM_DP_MST)  in intel_dp_detect_dpcd()
5456 	if (drm_probe_ddc(&intel_dp->aux.ddc))  in intel_dp_detect_dpcd()
5460 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {  in intel_dp_detect_dpcd()
5461 		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;  in intel_dp_detect_dpcd()
5466 		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in intel_dp_detect_dpcd()
5474 	drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");  in intel_dp_detect_dpcd()
5488 	if (dig_port->lock)  in intel_digital_port_lock()
5489 		dig_port->lock(dig_port);  in intel_digital_port_lock()
5496 	if (dig_port->unlock)  in intel_digital_port_unlock()
5497 		dig_port->unlock(dig_port);  in intel_digital_port_unlock()
5501  * intel_digital_port_connected_locked - is the specified port connected?
5504  * In cases where there's a connector physically connected but it can't be used
5506  * pretty much treat the port as disconnected. This is relevant for type-C
5516 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_digital_port_connected_locked()
5526 			is_connected = dig_port->connected(encoder);  in intel_digital_port_connected_locked()
5550 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_get_edid()  local
5551 	const struct drm_edid *fixed_edid = connector->panel.fixed_edid;  in intel_dp_get_edid()
5562 	return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);  in intel_dp_get_edid()
5570 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_update_dfp()  local
5572 	intel_dp->dfp.max_bpc =  in intel_dp_update_dfp()
5573 		drm_dp_downstream_max_bpc(intel_dp->dpcd,  in intel_dp_update_dfp()
5574 					  intel_dp->downstream_ports, drm_edid);  in intel_dp_update_dfp()
5576 	intel_dp->dfp.max_dotclock =  in intel_dp_update_dfp()
5577 		drm_dp_downstream_max_dotclock(intel_dp->dpcd,  in intel_dp_update_dfp()
5578 					       intel_dp->downstream_ports);  in intel_dp_update_dfp()
5580 	intel_dp->dfp.min_tmds_clock =  in intel_dp_update_dfp()
5581 		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,  in intel_dp_update_dfp()
5582 						 intel_dp->downstream_ports,  in intel_dp_update_dfp()
5584 	intel_dp->dfp.max_tmds_clock =  in intel_dp_update_dfp()
5585 		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,  in intel_dp_update_dfp()
5586 						 intel_dp->downstream_ports,  in intel_dp_update_dfp()
5589 	intel_dp->dfp.pcon_max_frl_bw =  in intel_dp_update_dfp()
5590 		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,  in intel_dp_update_dfp()
5591 					   intel_dp->downstream_ports);  in intel_dp_update_dfp()
5593 	drm_dbg_kms(display->drm,  in intel_dp_update_dfp()
5594 …   "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",  in intel_dp_update_dfp()
5595 		    connector->base.base.id, connector->base.name,  in intel_dp_update_dfp()
5596 		    intel_dp->dfp.max_bpc,  in intel_dp_update_dfp()
5597 		    intel_dp->dfp.max_dotclock,  in intel_dp_update_dfp()
5598 		    intel_dp->dfp.min_tmds_clock,  in intel_dp_update_dfp()
5599 		    intel_dp->dfp.max_tmds_clock,  in intel_dp_update_dfp()
5600 		    intel_dp->dfp.pcon_max_frl_bw);  in intel_dp_update_dfp()
5609 	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))  in intel_dp_can_ycbcr420()
5627 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_update_420()  local
5629 	intel_dp->dfp.ycbcr420_passthrough =  in intel_dp_update_420()
5630 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,  in intel_dp_update_420()
5631 						  intel_dp->downstream_ports);  in intel_dp_update_420()
5632 	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */  in intel_dp_update_420()
5633 	intel_dp->dfp.ycbcr_444_to_420 =  in intel_dp_update_420()
5634 		dp_to_dig_port(intel_dp)->lspcon.active ||  in intel_dp_update_420()
5635 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,  in intel_dp_update_420()
5636 							intel_dp->downstream_ports);  in intel_dp_update_420()
5637 	intel_dp->dfp.rgb_to_ycbcr =  in intel_dp_update_420()
5638 		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,  in intel_dp_update_420()
5639 							  intel_dp->downstream_ports,  in intel_dp_update_420()
5642 	connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);  in intel_dp_update_420()
5644 	drm_dbg_kms(display->drm,  in intel_dp_update_420()
5645 …"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversi…  in intel_dp_update_420()
5646 		    connector->base.base.id, connector->base.name,  in intel_dp_update_420()
5647 		    str_yes_no(intel_dp->dfp.rgb_to_ycbcr),  in intel_dp_update_420()
5648 		    str_yes_no(connector->base.ycbcr_420_allowed),  in intel_dp_update_420()
5649 		    str_yes_no(intel_dp->dfp.ycbcr_444_to_420));  in intel_dp_update_420()
5656 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_edid()  local
5662 	connector->detect_edid = drm_edid;  in intel_dp_set_edid()
5665 	drm_edid_connector_update(&connector->base, drm_edid);  in intel_dp_set_edid()
5667 	vrr_capable = intel_vrr_is_capable(connector);  in intel_dp_set_edid()
5668 	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",  in intel_dp_set_edid()
5669 		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));  in intel_dp_set_edid()
5670 	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);  in intel_dp_set_edid()
5675 	drm_dp_cec_attach(&intel_dp->aux,  in intel_dp_set_edid()
5676 			  connector->base.display_info.source_physical_address);  in intel_dp_set_edid()
5682 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_unset_edid()  local
5684 	drm_dp_cec_unset_edid(&intel_dp->aux);  in intel_dp_unset_edid()
5685 	drm_edid_free(connector->detect_edid);  in intel_dp_unset_edid()
5686 	connector->detect_edid = NULL;  in intel_dp_unset_edid()
5688 	intel_dp->dfp.max_bpc = 0;  in intel_dp_unset_edid()
5689 	intel_dp->dfp.max_dotclock = 0;  in intel_dp_unset_edid()
5690 	intel_dp->dfp.min_tmds_clock = 0;  in intel_dp_unset_edid()
5691 	intel_dp->dfp.max_tmds_clock = 0;  in intel_dp_unset_edid()
5693 	intel_dp->dfp.pcon_max_frl_bw = 0;  in intel_dp_unset_edid()
5695 	intel_dp->dfp.ycbcr_444_to_420 = false;  in intel_dp_unset_edid()
5696 	connector->base.ycbcr_420_allowed = false;  in intel_dp_unset_edid()
5698 	drm_connector_set_vrr_capable_property(&connector->base,  in intel_dp_unset_edid()
5707 	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&  in intel_dp_detect_sdp_caps()
5708 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);  in intel_dp_detect_sdp_caps()
5716 	struct intel_display *display = to_intel_display(_connector->dev);  in intel_dp_detect()
5717 	struct intel_connector *connector = to_intel_connector(_connector);  in intel_dp_detect()  local
5718 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_detect()
5720 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_detect()
5724 	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",  in intel_dp_detect()
5725 		    connector->base.base.id, connector->base.name);  in intel_dp_detect()
5726 	drm_WARN_ON(display->drm,  in intel_dp_detect()
5727 		    !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));  in intel_dp_detect()
5733 		return connector->base.status;  in intel_dp_detect()
5735 	intel_dp_flush_connector_commits(connector);  in intel_dp_detect()
5750 		 * This requires retrying detection for instance to re-enable  in intel_dp_detect()
5753 		 * ensured by setting the connector here to SST/disconnected,  in intel_dp_detect()
5754 		 * or via a userspace connector probing in response to the  in intel_dp_detect()
5761 		memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));  in intel_dp_detect()
5762 		intel_dp->psr.sink_panel_replay_support = false;  in intel_dp_detect()
5763 		intel_dp->psr.sink_panel_replay_su_support = false;  in intel_dp_detect()
5775 	if (ret == -EDEADLK) {  in intel_dp_detect()
5782 		connector->base.epoch_counter++;  in intel_dp_detect()
5787 	intel_dp_detect_dsc_caps(intel_dp, connector);  in intel_dp_detect()
5791 	if (intel_dp->reset_link_params) {  in intel_dp_detect()
5793 		intel_dp->reset_link_params = false;  in intel_dp_detect()
5800 	if (intel_dp->is_mst) {  in intel_dp_detect()
5802 		 * If we are in MST mode then this connector  in intel_dp_detect()
5826 	intel_dp->aux.i2c_nack_count = 0;  in intel_dp_detect()
5827 	intel_dp->aux.i2c_defer_count = 0;  in intel_dp_detect()
5830 	if (intel_dp_is_edp(intel_dp) || connector->detect_edid)  in intel_dp_detect()
5836 	if (status != connector_status_connected && !intel_dp->is_mst)  in intel_dp_detect()
5840 		drm_dp_set_subconnector_property(&connector->base,  in intel_dp_detect()
5842 						 intel_dp->dpcd,  in intel_dp_detect()
5843 						 intel_dp->downstream_ports);  in intel_dp_detect()
5851 intel_dp_force(struct drm_connector *connector)  in intel_dp_force()  argument
5853 	struct intel_display *display = to_intel_display(connector->dev);  in intel_dp_force()
5854 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));  in intel_dp_force()
5856 	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",  in intel_dp_force()
5857 		    connector->base.id, connector->name);  in intel_dp_force()
5864 	if (connector->status != connector_status_connected)  in intel_dp_force()
5872 	struct intel_display *display = to_intel_display(_connector->dev);  in intel_dp_get_modes()
5873 	struct intel_connector *connector = to_intel_connector(_connector);  in intel_dp_get_modes()  local
5874 	struct intel_dp *intel_dp = intel_attached_dp(connector);  in intel_dp_get_modes()
5877 	/* drm_edid_connector_update() done in ->detect() or ->force() */  in intel_dp_get_modes()
5878 	num_modes = drm_edid_connector_add_modes(&connector->base);  in intel_dp_get_modes()
5882 		num_modes += intel_panel_get_modes(connector);  in intel_dp_get_modes()
5887 	if (!connector->detect_edid) {  in intel_dp_get_modes()
5890 		mode = drm_dp_downstream_mode(display->drm,  in intel_dp_get_modes()
5891 					      intel_dp->dpcd,  in intel_dp_get_modes()
5892 					      intel_dp->downstream_ports);  in intel_dp_get_modes()
5894 			drm_mode_probed_add(&connector->base, mode);  in intel_dp_get_modes()
5903 intel_dp_connector_register(struct drm_connector *connector)  in intel_dp_connector_register()  argument
5905 	struct intel_display *display = to_intel_display(connector->dev);  in intel_dp_connector_register()
5906 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));  in intel_dp_connector_register()
5908 	struct intel_lspcon *lspcon = &dig_port->lspcon;  in intel_dp_connector_register()
5911 	ret = intel_connector_register(connector);  in intel_dp_connector_register()
5915 	drm_dbg_kms(display->drm, "registering %s bus for %s\n",  in intel_dp_connector_register()
5916 		    intel_dp->aux.name, connector->kdev->kobj.name);  in intel_dp_connector_register()
5918 	intel_dp->aux.dev = connector->kdev;  in intel_dp_connector_register()
5919 	ret = drm_dp_aux_register(&intel_dp->aux);  in intel_dp_connector_register()
5921 		drm_dp_cec_register_connector(&intel_dp->aux, connector);  in intel_dp_connector_register()
5923 	if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))  in intel_dp_connector_register()
5932 		if (lspcon->hdr_supported)  in intel_dp_connector_register()
5933 			drm_connector_attach_hdr_output_metadata_property(connector);  in intel_dp_connector_register()
5940 intel_dp_connector_unregister(struct drm_connector *connector)  in intel_dp_connector_unregister()  argument
5942 	struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));  in intel_dp_connector_unregister()
5944 	drm_dp_cec_unregister_connector(&intel_dp->aux);  in intel_dp_connector_unregister()
5945 	drm_dp_aux_unregister(&intel_dp->aux);  in intel_dp_connector_unregister()
5946 	intel_connector_unregister(connector);  in intel_dp_connector_unregister()
5949 void intel_dp_connector_sync_state(struct intel_connector *connector,  in intel_dp_connector_sync_state()  argument
5952 	struct intel_display *display = to_intel_display(connector);  in intel_dp_connector_sync_state()
5954 	if (crtc_state && crtc_state->dsc.compression_enable) {  in intel_dp_connector_sync_state()
5955 		drm_WARN_ON(display->drm,  in intel_dp_connector_sync_state()
5956 			    !connector->dp.dsc_decompression_aux);  in intel_dp_connector_sync_state()
5957 		connector->dp.dsc_decompression_enabled = true;  in intel_dp_connector_sync_state()
5959 		connector->dp.dsc_decompression_enabled = false;  in intel_dp_connector_sync_state()
5967 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_encoder_flush_work()
6007 	struct drm_connector *connector;  in intel_modeset_tile_group()  local
6010 	drm_connector_list_iter_begin(display->drm, &conn_iter);  in intel_modeset_tile_group()
6011 	drm_for_each_connector_iter(connector, &conn_iter) {  in intel_modeset_tile_group()
6016 		if (!connector->has_tile ||  in intel_modeset_tile_group()
6017 		    connector->tile_group->id != tile_group_id)  in intel_modeset_tile_group()
6020 		conn_state = drm_atomic_get_connector_state(&state->base,  in intel_modeset_tile_group()
6021 							    connector);  in intel_modeset_tile_group()
6027 		crtc = to_intel_crtc(conn_state->crtc);  in intel_modeset_tile_group()
6033 		crtc_state->uapi.mode_changed = true;  in intel_modeset_tile_group()
6035 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);  in intel_modeset_tile_group()
6052 	for_each_intel_crtc(display->drm, crtc) {  in intel_modeset_affected_transcoders()
6056 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_affected_transcoders()
6060 		if (!crtc_state->hw.enable)  in intel_modeset_affected_transcoders()
6063 		if (!(transcoders & BIT(crtc_state->cpu_transcoder)))  in intel_modeset_affected_transcoders()
6066 		crtc_state->uapi.mode_changed = true;  in intel_modeset_affected_transcoders()
6068 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);  in intel_modeset_affected_transcoders()
6072 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);  in intel_modeset_affected_transcoders()
6076 		transcoders &= ~BIT(crtc_state->cpu_transcoder);  in intel_modeset_affected_transcoders()
6079 	drm_WARN_ON(display->drm, transcoders != 0);  in intel_modeset_affected_transcoders()
6085 				      struct drm_connector *connector)  in intel_modeset_synced_crtcs()  argument
6088 		drm_atomic_get_old_connector_state(&state->base, connector);  in intel_modeset_synced_crtcs()
6093 	crtc = to_intel_crtc(old_conn_state->crtc);  in intel_modeset_synced_crtcs()
6099 	if (!old_crtc_state->hw.active)  in intel_modeset_synced_crtcs()
6102 	transcoders = old_crtc_state->sync_mode_slaves_mask;  in intel_modeset_synced_crtcs()
6103 	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_modeset_synced_crtcs()
6104 		transcoders |= BIT(old_crtc_state->master_transcoder);  in intel_modeset_synced_crtcs()
6113 	struct intel_display *display = to_intel_display(conn->dev);  in intel_dp_connector_atomic_check()
6117 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);  in intel_dp_connector_atomic_check()
6120 	ret = intel_digital_connector_atomic_check(conn, &state->base);  in intel_dp_connector_atomic_check()
6125 		ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);  in intel_dp_connector_atomic_check()
6146 	if (conn->has_tile) {  in intel_dp_connector_atomic_check()
6147 		ret = intel_modeset_tile_group(state, conn->tile_group->id);  in intel_dp_connector_atomic_check()
6155 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,  in intel_dp_oob_hotplug_event()  argument
6158 	struct intel_display *display = to_intel_display(connector->dev);  in intel_dp_oob_hotplug_event()
6159 	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));  in intel_dp_oob_hotplug_event()
6160 	struct drm_i915_private *i915 = to_i915(connector->dev);  in intel_dp_oob_hotplug_event()
6162 	unsigned int hpd_pin = encoder->hpd_pin;  in intel_dp_oob_hotplug_event()
6165 	spin_lock_irq(&i915->irq_lock);  in intel_dp_oob_hotplug_event()
6166 	if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {  in intel_dp_oob_hotplug_event()
6167 		display->hotplug.event_bits |= BIT(hpd_pin);  in intel_dp_oob_hotplug_event()
6170 			     &display->hotplug.oob_hotplug_last_state,  in intel_dp_oob_hotplug_event()
6174 	spin_unlock_irq(&i915->irq_lock);  in intel_dp_oob_hotplug_event()
6204 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);  in intel_dp_hpd_pulse()
6205 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_hpd_pulse()
6208 	if (dig_port->base.type == INTEL_OUTPUT_EDP &&  in intel_dp_hpd_pulse()
6210 	     intel_runtime_pm_suspended(&i915->runtime_pm) ||  in intel_dp_hpd_pulse()
6216 		 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."  in intel_dp_hpd_pulse()
6218 		drm_dbg_kms(display->drm,  in intel_dp_hpd_pulse()
6221 			    dig_port->base.base.base.id,  in intel_dp_hpd_pulse()
6222 			    dig_port->base.base.name);  in intel_dp_hpd_pulse()
6226 	drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",  in intel_dp_hpd_pulse()
6227 		    dig_port->base.base.base.id,  in intel_dp_hpd_pulse()
6228 		    dig_port->base.base.name,  in intel_dp_hpd_pulse()
6232 	 * TBT DP tunnels require the GFX driver to read out the DPRX caps in  in intel_dp_hpd_pulse()
6233 	 * response to long HPD pulses. The DP hotplug handler does that,  in intel_dp_hpd_pulse()
6235 	 * connector's/encoder's hotplug handler. Since the TBT CM may not  in intel_dp_hpd_pulse()
6236 	 * complete the DP tunnel BW request for the latter connector/encoder  in intel_dp_hpd_pulse()
6243 		intel_dp->reset_link_params = true;  in intel_dp_hpd_pulse()
6249 	if (intel_dp->is_mst) {  in intel_dp_hpd_pulse()
6288 	enum port port = encoder->port;  in intel_dp_has_gamut_metadata_dip()
6290 	if (intel_bios_encoder_is_lspcon(encoder->devdata))  in intel_dp_has_gamut_metadata_dip()
6299 	if (display->platform.haswell || display->platform.broadwell ||  in intel_dp_has_gamut_metadata_dip()
6307 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)  in intel_dp_add_properties()  argument
6310 	enum port port = dp_to_dig_port(intel_dp)->base.port;  in intel_dp_add_properties()
6313 		drm_connector_attach_dp_subconnector_property(connector);  in intel_dp_add_properties()
6315 	if (!display->platform.g4x && port != PORT_A)  in intel_dp_add_properties()
6316 		intel_attach_force_audio_property(connector);  in intel_dp_add_properties()
6318 	intel_attach_broadcast_rgb_property(connector);  in intel_dp_add_properties()
6320 		drm_connector_attach_max_bpc_property(connector, 6, 10);  in intel_dp_add_properties()
6322 		drm_connector_attach_max_bpc_property(connector, 6, 12);  in intel_dp_add_properties()
6325 	if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {  in intel_dp_add_properties()
6326 		drm_connector_attach_content_type_property(connector);  in intel_dp_add_properties()
6327 		intel_attach_hdmi_colorspace_property(connector);  in intel_dp_add_properties()
6329 		intel_attach_dp_colorspace_property(connector);  in intel_dp_add_properties()
6332 	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))  in intel_dp_add_properties()
6333 		drm_connector_attach_hdr_output_metadata_property(connector);  in intel_dp_add_properties()
6336 		drm_connector_attach_vrr_capable_property(connector);  in intel_dp_add_properties()
6343 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_add_properties()  local
6345 		intel_panel_preferred_fixed_mode(connector);  in intel_edp_add_properties()
6347 	intel_attach_scaling_mode_property(&connector->base);  in intel_edp_add_properties()
6349 	drm_connector_set_panel_orientation_with_quirk(&connector->base,  in intel_edp_add_properties()
6350 						       display->vbt.orientation,  in intel_edp_add_properties()
6351 						       fixed_mode->hdisplay,  in intel_edp_add_properties()
6352 						       fixed_mode->vdisplay);  in intel_edp_add_properties()
6356 				      struct intel_connector *connector)  in intel_edp_backlight_setup()  argument
6361 	if (display->platform.valleyview || display->platform.cherryview)  in intel_edp_backlight_setup()
6364 	intel_backlight_setup(connector, pipe);  in intel_edp_backlight_setup()
6368 				     struct intel_connector *connector)  in intel_edp_init_connector()  argument
6371 	struct drm_i915_private *dev_priv = to_i915(display->drm);  in intel_edp_init_connector()
6373 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_edp_init_connector()
6384 	 * with an already powered-on LVDS power sequencer.  in intel_edp_init_connector()
6387 		drm_WARN_ON(display->drm,  in intel_edp_init_connector()
6389 		drm_info(display->drm,  in intel_edp_init_connector()
6395 	intel_bios_init_panel_early(display, &connector->panel,  in intel_edp_init_connector()
6396 				    encoder->devdata);  in intel_edp_init_connector()
6399 		drm_info(display->drm,  in intel_edp_init_connector()
6401 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6422 	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);  in intel_edp_init_connector()
6426 		drm_info(display->drm,  in intel_edp_init_connector()
6428 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6440 	if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {  in intel_edp_init_connector()
6449 			drm_info(display->drm,  in intel_edp_init_connector()
6451 				 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6457 		 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall  in intel_edp_init_connector()
6461 		if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&  in intel_edp_init_connector()
6462 		    (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==  in intel_edp_init_connector()
6464 			drm_info(display->drm,  in intel_edp_init_connector()
6466 				 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6471 	mutex_lock(&display->drm->mode_config.mutex);  in intel_edp_init_connector()
6472 	drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);  in intel_edp_init_connector()
6475 		drm_edid = intel_opregion_get_edid(connector);  in intel_edp_init_connector()
6477 			drm_dbg_kms(display->drm,  in intel_edp_init_connector()
6478 				    "[CONNECTOR:%d:%s] Using OpRegion EDID\n",  in intel_edp_init_connector()
6479 				    connector->base.base.id, connector->base.name);  in intel_edp_init_connector()
6482 		if (drm_edid_connector_update(&connector->base, drm_edid) ||  in intel_edp_init_connector()
6483 		    !drm_edid_connector_add_modes(&connector->base)) {  in intel_edp_init_connector()
6484 			drm_edid_connector_update(&connector->base, NULL);  in intel_edp_init_connector()
6486 			drm_edid = ERR_PTR(-EINVAL);  in intel_edp_init_connector()
6489 		drm_edid = ERR_PTR(-ENOENT);  in intel_edp_init_connector()
6492 	intel_bios_init_panel_late(display, &connector->panel, encoder->devdata,  in intel_edp_init_connector()
6495 	intel_panel_add_edid_fixed_modes(connector, true);  in intel_edp_init_connector()
6501 	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head)  in intel_edp_init_connector()
6502 		intel_edp_mso_mode_fixup(connector, fixed_mode);  in intel_edp_init_connector()
6505 	if (!intel_panel_preferred_fixed_mode(connector))  in intel_edp_init_connector()
6506 		intel_panel_add_vbt_lfp_fixed_mode(connector);  in intel_edp_init_connector()
6508 	mutex_unlock(&display->drm->mode_config.mutex);  in intel_edp_init_connector()
6510 	if (!intel_panel_preferred_fixed_mode(connector)) {  in intel_edp_init_connector()
6511 		drm_info(display->drm,  in intel_edp_init_connector()
6513 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6517 	intel_panel_init(connector, drm_edid);  in intel_edp_init_connector()
6519 	intel_edp_backlight_setup(intel_dp, connector);  in intel_edp_init_connector()
6529 	intel_bios_fini_panel(&connector->panel);  in intel_edp_init_connector()
6536 	struct intel_connector *connector = container_of(work, typeof(*connector),  in intel_dp_modeset_retry_work_fn()  local
6538 	struct intel_display *display = to_intel_display(connector);  in intel_dp_modeset_retry_work_fn()
6540 	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id,  in intel_dp_modeset_retry_work_fn()
6541 		    connector->base.name);  in intel_dp_modeset_retry_work_fn()
6543 	/* Grab the locks before changing connector property*/  in intel_dp_modeset_retry_work_fn()
6544 	mutex_lock(&display->drm->mode_config.mutex);  in intel_dp_modeset_retry_work_fn()
6545 	/* Set connector link status to BAD and send a Uevent to notify  in intel_dp_modeset_retry_work_fn()
6548 	drm_connector_set_link_status_property(&connector->base,  in intel_dp_modeset_retry_work_fn()
6550 	mutex_unlock(&display->drm->mode_config.mutex);  in intel_dp_modeset_retry_work_fn()
6552 	drm_kms_helper_connector_hotplug_event(&connector->base);  in intel_dp_modeset_retry_work_fn()
6554 	drm_connector_put(&connector->base);  in intel_dp_modeset_retry_work_fn()
6557 void intel_dp_init_modeset_retry_work(struct intel_connector *connector)  in intel_dp_init_modeset_retry_work()  argument
6559 	INIT_WORK(&connector->modeset_retry_work,  in intel_dp_init_modeset_retry_work()
6565 			struct intel_connector *connector)  in intel_dp_init_connector()  argument
6568 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_init_connector()
6569 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_init_connector()
6570 	struct drm_device *dev = encoder->base.dev;  in intel_dp_init_connector()
6572 	enum port port = encoder->port;  in intel_dp_init_connector()
6576 	intel_dp_init_modeset_retry_work(connector);  in intel_dp_init_connector()
6578 	if (drm_WARN(dev, dig_port->max_lanes < 1,  in intel_dp_init_connector()
6579 		     "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",  in intel_dp_init_connector()
6580 		     dig_port->max_lanes, encoder->base.base.id,  in intel_dp_init_connector()
6581 		     encoder->base.name))  in intel_dp_init_connector()
6584 	intel_dp->reset_link_params = true;  in intel_dp_init_connector()
6587 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg);  in intel_dp_init_connector()
6588 	intel_dp->attached_connector = connector;  in intel_dp_init_connector()
6590 	if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {  in intel_dp_init_connector()
6598 		encoder->type = INTEL_OUTPUT_EDP;  in intel_dp_init_connector()
6601 		if (drm_WARN_ON(dev, (display->platform.valleyview ||  in intel_dp_init_connector()
6602 				      display->platform.cherryview) &&  in intel_dp_init_connector()
6612 	if (display->platform.valleyview || display->platform.cherryview)  in intel_dp_init_connector()
6616 	connector->dp.dsc_decompression_aux = &intel_dp->aux;  in intel_dp_init_connector()
6618 	drm_dbg_kms(display->drm,  in intel_dp_init_connector()
6619 		    "Adding %s connector on [ENCODER:%d:%s]\n",  in intel_dp_init_connector()
6620 		    type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",  in intel_dp_init_connector()
6621 		    encoder->base.base.id, encoder->base.name);  in intel_dp_init_connector()
6623 	drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs,  in intel_dp_init_connector()
6624 				    type, &intel_dp->aux.ddc);  in intel_dp_init_connector()
6625 	drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs);  in intel_dp_init_connector()
6628 		connector->base.interlace_allowed = true;  in intel_dp_init_connector()
6631 		connector->polled = DRM_CONNECTOR_POLL_HPD;  in intel_dp_init_connector()
6632 	connector->base.polled = connector->polled;  in intel_dp_init_connector()
6634 	intel_connector_attach_encoder(connector, encoder);  in intel_dp_init_connector()
6637 		connector->get_hw_state = intel_ddi_connector_get_hw_state;  in intel_dp_init_connector()
6639 		connector->get_hw_state = intel_connector_get_hw_state;  in intel_dp_init_connector()
6640 	connector->sync_state = intel_dp_connector_sync_state;  in intel_dp_init_connector()
6642 	if (!intel_edp_init_connector(intel_dp, connector)) {  in intel_dp_init_connector()
6652 	intel_dp_mst_encoder_init(dig_port, connector->base.base.id);  in intel_dp_init_connector()
6654 	intel_dp_add_properties(intel_dp, &connector->base);  in intel_dp_init_connector()
6657 		int ret = intel_dp_hdcp_init(dig_port, connector);  in intel_dp_init_connector()
6659 			drm_dbg_kms(display->drm,  in intel_dp_init_connector()
6663 	intel_dp->frl.is_trained = false;  in intel_dp_init_connector()
6664 	intel_dp->frl.trained_rate_gbps = 0;  in intel_dp_init_connector()
6672 	drm_connector_cleanup(&connector->base);  in intel_dp_init_connector()
6684 	for_each_intel_encoder(display->drm, encoder) {  in intel_dp_mst_suspend()
6687 		if (encoder->type != INTEL_OUTPUT_DDI)  in intel_dp_mst_suspend()
6695 		if (intel_dp->is_mst)  in intel_dp_mst_suspend()
6696 			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);  in intel_dp_mst_suspend()
6707 	for_each_intel_encoder(display->drm, encoder) {  in intel_dp_mst_resume()
6711 		if (encoder->type != INTEL_OUTPUT_DDI)  in intel_dp_mst_resume()
6719 		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,  in intel_dp_mst_resume()
6722 			intel_dp->is_mst = false;  in intel_dp_mst_resume()
6723 			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,  in intel_dp_mst_resume()