Lines Matching full:pipe
30 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank() argument
33 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in intel_handle_vblank()
106 * bdw_update_pipe_irq - update DE pipe interrupt
108 * @pipe: pipe whose interrupt to update
113 enum pipe pipe, u32 interrupt_mask, in bdw_update_pipe_irq() argument
125 new_val = dev_priv->display.irq.de_irq_mask[pipe]; in bdw_update_pipe_irq()
129 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) { in bdw_update_pipe_irq()
130 dev_priv->display.irq.de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
131 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), in bdw_update_pipe_irq()
132 dev_priv->display.irq.de_irq_mask[pipe]); in bdw_update_pipe_irq()
133 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
138 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq() argument
140 bdw_update_pipe_irq(i915, pipe, bits, bits); in bdw_enable_pipe_irq()
144 enum pipe pipe, u32 bits) in bdw_disable_pipe_irq() argument
146 bdw_update_pipe_irq(i915, pipe, bits, 0); in bdw_disable_pipe_irq()
186 enum pipe pipe) in i915_pipestat_enable_mask() argument
188 u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
197 * On pipe A we don't support the PSR interrupt yet, in i915_pipestat_enable_mask()
198 * on pipe B and C the same bit MBZ. in i915_pipestat_enable_mask()
204 * On pipe B and C we don't support the PSR interrupt yet, on pipe in i915_pipestat_enable_mask()
223 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", in i915_pipestat_enable_mask()
224 pipe_name(pipe), enable_mask, status_mask); in i915_pipestat_enable_mask()
230 enum pipe pipe, u32 status_mask) in i915_enable_pipestat() argument
232 i915_reg_t reg = PIPESTAT(dev_priv, pipe); in i915_enable_pipestat()
236 "pipe %c: status_mask=0x%x\n", in i915_enable_pipestat()
237 pipe_name(pipe), status_mask); in i915_enable_pipestat()
242 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
245 dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
246 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_enable_pipestat()
253 enum pipe pipe, u32 status_mask) in i915_disable_pipestat() argument
255 i915_reg_t reg = PIPESTAT(dev_priv, pipe); in i915_disable_pipestat()
259 "pipe %c: status_mask=0x%x\n", in i915_disable_pipestat()
260 pipe_name(pipe), status_mask); in i915_disable_pipestat()
265 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
268 dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
269 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_disable_pipestat()
314 enum pipe pipe, in display_pipe_crc_irq_handler() argument
320 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in display_pipe_crc_irq_handler()
350 enum pipe pipe, in display_pipe_crc_irq_handler() argument
357 enum pipe pipe) in flip_done_handler() argument
360 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); in flip_done_handler()
374 enum pipe pipe) in hsw_pipe_crc_irq_handler() argument
376 display_pipe_crc_irq_handler(dev_priv, pipe, in hsw_pipe_crc_irq_handler()
377 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)), in hsw_pipe_crc_irq_handler()
382 enum pipe pipe) in ivb_pipe_crc_irq_handler() argument
384 display_pipe_crc_irq_handler(dev_priv, pipe, in ivb_pipe_crc_irq_handler()
385 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
386 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
387 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
388 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
389 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
393 enum pipe pipe) in i9xx_pipe_crc_irq_handler() argument
399 PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); in i9xx_pipe_crc_irq_handler()
405 PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); in i9xx_pipe_crc_irq_handler()
409 display_pipe_crc_irq_handler(dev_priv, pipe, in i9xx_pipe_crc_irq_handler()
410 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
411 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
412 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
418 enum pipe pipe; in i9xx_pipestat_irq_reset() local
420 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_reset()
422 PIPESTAT(dev_priv, pipe), in i9xx_pipestat_irq_reset()
426 dev_priv->display.irq.pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
433 enum pipe pipe; in i9xx_pipestat_irq_ack() local
443 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_ack()
458 switch (pipe) { in i9xx_pipestat_irq_ack()
471 status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
476 reg = PIPESTAT(dev_priv, pipe); in i9xx_pipestat_irq_ack()
477 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; in i9xx_pipestat_irq_ack()
478 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i9xx_pipestat_irq_ack()
481 * Clear the PIPE*STAT regs before the IIR in i9xx_pipestat_irq_ack()
484 * edge in the ISR pipe event bit if we don't clear in i9xx_pipestat_irq_ack()
489 if (pipe_stats[pipe]) { in i9xx_pipestat_irq_ack()
490 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); in i9xx_pipestat_irq_ack()
502 enum pipe pipe; in i915_pipestat_irq_handler() local
504 for_each_pipe(dev_priv, pipe) { in i915_pipestat_irq_handler()
505 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) in i915_pipestat_irq_handler()
506 intel_handle_vblank(dev_priv, pipe); in i915_pipestat_irq_handler()
508 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i915_pipestat_irq_handler()
511 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i915_pipestat_irq_handler()
512 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
514 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i915_pipestat_irq_handler()
515 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
527 enum pipe pipe; in i965_pipestat_irq_handler() local
529 for_each_pipe(dev_priv, pipe) { in i965_pipestat_irq_handler()
530 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) in i965_pipestat_irq_handler()
531 intel_handle_vblank(dev_priv, pipe); in i965_pipestat_irq_handler()
533 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i965_pipestat_irq_handler()
536 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i965_pipestat_irq_handler()
537 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
539 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i965_pipestat_irq_handler()
540 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
554 enum pipe pipe; in valleyview_pipestat_irq_handler() local
556 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
557 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
558 intel_handle_vblank(dev_priv, pipe); in valleyview_pipestat_irq_handler()
560 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) in valleyview_pipestat_irq_handler()
561 flip_done_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
563 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
564 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
566 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in valleyview_pipestat_irq_handler()
567 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
577 enum pipe pipe; in ibx_irq_handler() local
605 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
606 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in ibx_irq_handler()
607 pipe_name(pipe), in ibx_irq_handler()
608 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in ibx_irq_handler()
628 enum pipe pipe; in ivb_err_int_handler() local
633 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
634 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) in ivb_err_int_handler()
635 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
637 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { in ivb_err_int_handler()
639 ivb_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
641 hsw_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
651 enum pipe pipe; in cpt_serr_int_handler() local
656 for_each_pipe(dev_priv, pipe) in cpt_serr_int_handler()
657 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) in cpt_serr_int_handler()
658 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); in cpt_serr_int_handler()
666 enum pipe pipe; in cpt_irq_handler() local
691 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
692 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in cpt_irq_handler()
693 pipe_name(pipe), in cpt_irq_handler()
694 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in cpt_irq_handler()
704 enum pipe pipe; in ilk_display_irq_handler() local
719 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
720 if (de_iir & DE_PIPE_VBLANK(pipe)) in ilk_display_irq_handler()
721 intel_handle_vblank(dev_priv, pipe); in ilk_display_irq_handler()
723 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) in ilk_display_irq_handler()
724 flip_done_handler(dev_priv, pipe); in ilk_display_irq_handler()
726 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) in ilk_display_irq_handler()
727 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
729 if (de_iir & DE_PIPE_CRC_DONE(pipe)) in ilk_display_irq_handler()
730 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
753 enum pipe pipe; in ivb_display_irq_handler() local
782 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
783 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) in ivb_display_irq_handler()
784 intel_handle_vblank(dev_priv, pipe); in ivb_display_irq_handler()
786 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) in ivb_display_irq_handler()
787 flip_done_handler(dev_priv, pipe); in ivb_display_irq_handler()
972 enum pipe pipe = INVALID_PIPE; in gen11_dsi_te_interrupt_handler() local
1002 /* Get PIPE for handling VBLANK event */ in gen11_dsi_te_interrupt_handler()
1007 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
1010 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
1013 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
1016 drm_err(&dev_priv->drm, "Invalid PIPE\n"); in gen11_dsi_te_interrupt_handler()
1020 intel_handle_vblank(dev_priv, pipe); in gen11_dsi_te_interrupt_handler()
1067 enum pipe pipe; in gen8_de_irq_handler() local
1145 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_handler()
1148 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) in gen8_de_irq_handler()
1151 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
1154 "The master control interrupt lied (DE PIPE)!\n"); in gen8_de_irq_handler()
1158 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
1161 intel_handle_vblank(dev_priv, pipe); in gen8_de_irq_handler()
1164 flip_done_handler(dev_priv, pipe); in gen8_de_irq_handler()
1168 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0); in gen8_de_irq_handler()
1171 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1); in gen8_de_irq_handler()
1174 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2); in gen8_de_irq_handler()
1178 hsw_pipe_crc_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
1181 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
1186 "Fault errors on pipe %c: 0x%08x\n", in gen8_de_irq_handler()
1187 pipe_name(pipe), in gen8_de_irq_handler()
1299 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_enable_vblank() local
1303 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_enable_vblank()
1312 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_disable_vblank() local
1316 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_disable_vblank()
1341 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_enable_vblank() local
1345 i915_enable_pipestat(dev_priv, pipe, in i965_enable_vblank()
1355 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_disable_vblank() local
1359 i915_disable_pipestat(dev_priv, pipe, in i965_disable_vblank()
1367 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_enable_vblank() local
1370 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); in ilk_enable_vblank()
1388 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_disable_vblank() local
1391 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); in ilk_disable_vblank()
1443 enum pipe pipe = crtc->pipe; in bdw_enable_vblank() local
1453 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_enable_vblank()
1470 enum pipe pipe = crtc->pipe; in bdw_disable_vblank() local
1477 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_disable_vblank()
1525 enum pipe pipe; in vlv_display_irq_postinstall() local
1533 for_each_pipe(dev_priv, pipe) in vlv_display_irq_postinstall()
1534 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in vlv_display_irq_postinstall()
1556 enum pipe pipe; in gen8_display_irq_reset() local
1564 for_each_pipe(dev_priv, pipe) in gen8_display_irq_reset()
1566 POWER_DOMAIN_PIPE(pipe))) in gen8_display_irq_reset()
1567 gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen8_display_irq_reset()
1576 enum pipe pipe; in gen11_display_irq_reset() local
1607 for_each_pipe(dev_priv, pipe) in gen11_display_irq_reset()
1609 POWER_DOMAIN_PIPE(pipe))) in gen11_display_irq_reset()
1610 gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen11_display_irq_reset()
1630 enum pipe pipe; in gen8_irq_power_well_post_enable() local
1639 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
1640 gen2_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe), in gen8_irq_power_well_post_enable()
1641 dev_priv->display.irq.de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
1642 ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
1651 enum pipe pipe; in gen8_irq_power_well_pre_disable() local
1660 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
1661 gen2_irq_reset(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe)); in gen8_irq_power_well_pre_disable()
1783 enum pipe pipe; in gen8_de_irq_postinstall() local
1846 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_postinstall()
1847 dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
1850 POWER_DOMAIN_PIPE(pipe))) in gen8_de_irq_postinstall()
1851 gen2_irq_init(uncore, GEN8_DE_PIPE_IRQ_REGS(pipe), in gen8_de_irq_postinstall()
1852 dev_priv->display.irq.de_irq_mask[pipe], in gen8_de_irq_postinstall()