Lines Matching +full:0 +full:x62000
76 #define PIPE_A_OFFSET 0x70000
77 #define PIPE_B_OFFSET 0x71000
78 #define PIPE_C_OFFSET 0x72000
79 #define PIPE_D_OFFSET 0x73000
80 #define CHV_PIPE_C_OFFSET 0x74000
87 #define PIPE_EDP_OFFSET 0x7f000
89 /* ICL DSI 0 and 1 */
90 #define PIPE_DSI0_OFFSET 0x7b000
91 #define PIPE_DSI1_OFFSET 0x7b800
93 #define TRANSCODER_A_OFFSET 0x60000
94 #define TRANSCODER_B_OFFSET 0x61000
95 #define TRANSCODER_C_OFFSET 0x62000
96 #define CHV_TRANSCODER_C_OFFSET 0x63000
97 #define TRANSCODER_D_OFFSET 0x63000
98 #define TRANSCODER_EDP_OFFSET 0x6f000
99 #define TRANSCODER_DSI0_OFFSET 0x6b000
100 #define TRANSCODER_DSI1_OFFSET 0x6b800
102 #define CURSOR_A_OFFSET 0x70080
103 #define CURSOR_B_OFFSET 0x700c0
104 #define CHV_CURSOR_C_OFFSET 0x700e0
105 #define IVB_CURSOR_B_OFFSET 0x71080
106 #define IVB_CURSOR_C_OFFSET 0x72080
107 #define TGL_CURSOR_D_OFFSET 0x73080
541 0
547 0
592 0
600 0
687 0
693 0
697 [0x6] = STEP_G0,
698 [0x7] = STEP_H0,
699 [0x9] = STEP_J0,
700 [0xA] = STEP_I1,
724 0
731 0
767 0
772 0
794 0
833 [0xA] = STEP_C0,
834 [0xB] = STEP_C0,
835 [0xC] = STEP_D0,
836 [0xD] = STEP_E0,
867 .abox_mask = BIT(0), \
909 0
940 [0] = STEP_A0,
1001 0
1005 [0] = STEP_B0,
1010 [0] = STEP_A0,
1040 [0] = STEP_A0,
1057 [0] = STEP_A0,
1066 .abox_mask = BIT(0),
1068 .has_psr_hw_tracking = 0,
1081 0
1085 [0x0] = STEP_A0,
1086 [0x1] = STEP_A2,
1087 [0x4] = STEP_B0,
1088 [0x8] = STEP_B0,
1089 [0xC] = STEP_C0,
1093 [0x4] = STEP_D0,
1094 [0xC] = STEP_C0,
1110 .has_psr_hw_tracking = 0,
1119 .abox_mask = GENMASK(1, 0), \
1164 .has_psr_hw_tracking = 0,
1176 0
1181 0
1186 0
1190 [0x0] = STEP_A0,
1191 [0x4] = STEP_B0,
1192 [0x8] = STEP_C0,
1193 [0xC] = STEP_D0,
1197 [0x0] = STEP_D0,
1201 [0x4] = STEP_E0,
1241 0
1246 0
1251 0
1255 [0x0] = STEP_A0,
1256 [0x1] = STEP_A0,
1257 [0x4] = STEP_B0,
1258 [0x8] = STEP_C0,
1262 [0x0] = STEP_B0,
1263 [0x4] = STEP_C0,
1264 [0x5] = STEP_C0,
1268 [0x0] = STEP_C0,
1269 [0x1] = STEP_C0,
1297 .abox_mask = GENMASK(1, 0), \
1393 INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0), in has_no_display()
1463 { 14, 0, &xe_lpdp_display },
1465 { 20, 0, &xe2_lpd_display },
1466 { 30, 0, &xe2_lpd_display },
1478 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); in probe_gmdid_display()
1488 if (val == 0) { in probe_gmdid_display()
1497 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) { in probe_gmdid_display()
1515 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { in find_platform_desc()
1560 drm_warn(display->drm, "Unknown revision 0x%02x\n", revision); in get_pre_gmdid_step()
1568 * it's better than defaulting to 0. in get_pre_gmdid_step()
1574 drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n", in get_pre_gmdid_step()
1591 return sizeof(((struct intel_display_platforms *)0)->bitmap) * BITS_PER_BYTE; in display_platforms_num_bits()
1719 display_runtime->num_scalers[pipe] = 0; in __intel_display_device_info_runtime_init()
1773 * reads don't land anywhere. In that case, we read 0s. in __intel_display_device_info_runtime_init()
1820 display_runtime->has_hdcp = 0; in __intel_display_device_info_runtime_init()
1824 display_runtime->fbc_mask = 0; in __intel_display_device_info_runtime_init()
1828 display_runtime->has_dmc = 0; in __intel_display_device_info_runtime_init()
1832 display_runtime->has_dsc = 0; in __intel_display_device_info_runtime_init()
1844 display_runtime->has_dsc = 0; in __intel_display_device_info_runtime_init()
1865 memset(display_runtime, 0, sizeof(*display_runtime)); in __intel_display_device_info_runtime_init()