Lines Matching +full:hdmi +full:- +full:dp2
101 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
103 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
129 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
132 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
133 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
138 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
143 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
145 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
152 * HDMI/DVI use cases.
157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_hdmi_ddi_buffers()
161 enum port port = encoder->port; in hsw_prepare_hdmi_ddi_buffers()
164 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_hdmi_ddi_buffers()
165 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_hdmi_ddi_buffers()
170 intel_bios_hdmi_boost_level(encoder->devdata)) in hsw_prepare_hdmi_ddi_buffers()
173 /* Entry 9 is for HDMI: */ in hsw_prepare_hdmi_ddi_buffers()
175 trans->entries[level].hsw.trans1 | iboost_bit); in hsw_prepare_hdmi_ddi_buffers()
177 trans->entries[level].hsw.trans2); in hsw_prepare_hdmi_ddi_buffers()
188 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", in mtl_wait_ddi_buf_idle()
202 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", in intel_wait_ddi_buf_idle()
208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_wait_ddi_buf_active()
209 enum port port = encoder->port; in intel_wait_ddi_buf_active()
242 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", in intel_wait_ddi_buf_active()
248 switch (pll->info->id) { in hsw_pll_to_ddi_pll_sel()
262 MISSING_CASE(pll->info->id); in hsw_pll_to_ddi_pll_sel()
270 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
271 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
272 const enum intel_dpll_id id = pll->info->id; in icl_pll_to_ddi_clk_sel()
334 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_init_dp_buf_reg()
339 intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | in intel_ddi_init_dp_buf_reg()
342 if (dig_port->lane_reversal) in intel_ddi_init_dp_buf_reg()
343 intel_dp->DP |= DDI_BUF_PORT_REVERSAL; in intel_ddi_init_dp_buf_reg()
344 if (dig_port->ddi_a_4_lanes) in intel_ddi_init_dp_buf_reg()
345 intel_dp->DP |= DDI_A_4_LANES; in intel_ddi_init_dp_buf_reg()
349 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; in intel_ddi_init_dp_buf_reg()
351 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; in intel_ddi_init_dp_buf_reg()
355 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
357 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; in intel_ddi_init_dp_buf_reg()
386 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
389 pipe_config->hw.adjusted_mode.crtc_clock = in ddi_dotclock_get()
396 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_set_dp_msa()
397 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_set_dp_msa()
398 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_set_dp_msa()
404 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); in intel_ddi_set_dp_msa()
408 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
422 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
427 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && in intel_ddi_set_dp_msa()
428 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_ddi_set_dp_msa()
430 if (crtc_state->limited_color_range) in intel_ddi_set_dp_msa()
438 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_ddi_set_dp_msa()
467 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_dp2()
489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_transcoder_func_reg_val_get()
490 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_transcoder_func_reg_val_get()
491 enum pipe pipe = crtc->pipe; in intel_ddi_transcoder_func_reg_val_get()
492 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_transcoder_func_reg_val_get()
493 enum port port = encoder->port; in intel_ddi_transcoder_func_reg_val_get()
496 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ in intel_ddi_transcoder_func_reg_val_get()
503 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
505 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
521 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) in intel_ddi_transcoder_func_reg_val_get()
523 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) in intel_ddi_transcoder_func_reg_val_get()
532 /* On Haswell, can only use the always-on power well for in intel_ddi_transcoder_func_reg_val_get()
536 if (crtc_state->pch_pfit.force_thru) in intel_ddi_transcoder_func_reg_val_get()
551 if (crtc_state->has_hdmi_sink) in intel_ddi_transcoder_func_reg_val_get()
556 if (crtc_state->hdmi_scrambling) in intel_ddi_transcoder_func_reg_val_get()
558 if (crtc_state->hdmi_high_tmds_clock_ratio) in intel_ddi_transcoder_func_reg_val_get()
561 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
564 temp |= (crtc_state->fdi_lanes - 1) << 1; in intel_ddi_transcoder_func_reg_val_get()
571 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
576 master = crtc_state->mst_master_transcoder; in intel_ddi_transcoder_func_reg_val_get()
577 drm_WARN_ON(&dev_priv->drm, in intel_ddi_transcoder_func_reg_val_get()
583 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
587 crtc_state->master_transcoder != INVALID_TRANSCODER) { in intel_ddi_transcoder_func_reg_val_get()
589 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); in intel_ddi_transcoder_func_reg_val_get()
601 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_enable_transcoder_func()
602 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_enable_transcoder_func()
603 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_func()
606 enum transcoder master_transcoder = crtc_state->master_transcoder; in intel_ddi_enable_transcoder_func()
629 * bit for the DDI function and enables the DP2 configuration. Called for all
636 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_config_transcoder_func()
637 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_config_transcoder_func()
638 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_func()
651 * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port,
652 * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master
658 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_disable_transcoder_func()
659 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_disable_transcoder_func()
660 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_func()
671 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); in intel_ddi_disable_transcoder_func()
696 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); in intel_ddi_disable_transcoder_func()
706 struct drm_device *dev = intel_encoder->base.dev; in intel_ddi_toggle_hdcp_bits()
712 intel_encoder->power_domain); in intel_ddi_toggle_hdcp_bits()
714 return -ENXIO; in intel_ddi_toggle_hdcp_bits()
718 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); in intel_ddi_toggle_hdcp_bits()
725 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_ddi_connector_get_hw_state()
727 int type = intel_connector->base.connector_type; in intel_ddi_connector_get_hw_state()
728 enum port port = encoder->port; in intel_ddi_connector_get_hw_state()
736 encoder->power_domain); in intel_ddi_connector_get_hw_state()
741 if (!encoder->get_hw_state(encoder, &pipe)) { in intel_ddi_connector_get_hw_state()
764 * encoder->get_hw_state() should have bailed out on MST. This in intel_ddi_connector_get_hw_state()
765 * must be SST and non-eDP. in intel_ddi_connector_get_hw_state()
768 } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { in intel_ddi_connector_get_hw_state()
769 /* encoder->get_hw_state() should have bailed out on MST. */ in intel_ddi_connector_get_hw_state()
776 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_ddi_connector_get_hw_state()
785 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_ddi_get_encoder_pipes()
786 enum port port = encoder->port; in intel_ddi_get_encoder_pipes()
796 encoder->power_domain); in intel_ddi_get_encoder_pipes()
864 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
866 encoder->base.base.id, encoder->base.name); in intel_ddi_get_encoder_pipes()
887 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
889 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
891 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
895 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
896 …"Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b … in intel_ddi_get_encoder_pipes()
897 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
908 drm_err(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
910 encoder->base.base.id, encoder->base.name, tmp); in intel_ddi_get_encoder_pipes()
913 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_ddi_get_encoder_pipes()
927 *pipe = ffs(pipe_mask) - 1; in intel_ddi_get_hw_state()
936 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_ddi_main_link_aux_domain()
945 * Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require in intel_ddi_main_link_aux_domain()
951 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) in intel_ddi_main_link_aux_domain()
952 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); in intel_ddi_main_link_aux_domain()
955 intel_encoder_is_tc(&dig_port->base))) in intel_ddi_main_link_aux_domain()
965 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in main_link_aux_power_domain_get()
969 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); in main_link_aux_power_domain_get()
974 dig_port->aux_wakeref = intel_display_power_get(i915, domain); in main_link_aux_power_domain_get()
981 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in main_link_aux_power_domain_put()
986 wf = fetch_and_zero(&dig_port->aux_wakeref); in main_link_aux_power_domain_put()
996 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_power_domains()
1001 * happen since fake-MST encoders don't set their get_power_domains() in intel_ddi_get_power_domains()
1004 if (drm_WARN_ON(&dev_priv->drm, in intel_ddi_get_power_domains()
1011 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in intel_ddi_get_power_domains()
1012 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in intel_ddi_get_power_domains()
1013 dig_port->ddi_io_power_domain); in intel_ddi_get_power_domains()
1022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_enable_transcoder_clock()
1023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_enable_transcoder_clock()
1024 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_clock()
1034 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); in intel_ddi_enable_transcoder_clock()
1036 val = TRANS_CLK_SEL_PORT(encoder->port); in intel_ddi_enable_transcoder_clock()
1043 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_disable_transcoder_clock()
1044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_clock()
1077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in skl_ddi_set_iboost()
1081 iboost = intel_bios_hdmi_boost_level(encoder->devdata); in skl_ddi_set_iboost()
1083 iboost = intel_bios_dp_boost_level(encoder->devdata); in skl_ddi_set_iboost()
1089 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in skl_ddi_set_iboost()
1090 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in skl_ddi_set_iboost()
1093 iboost = trans->entries[level].hsw.i_boost; in skl_ddi_set_iboost()
1098 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); in skl_ddi_set_iboost()
1102 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); in skl_ddi_set_iboost()
1104 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
1111 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_dp_voltage_max()
1112 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_dp_voltage_max()
1115 encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_ddi_dp_voltage_max()
1117 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) in intel_ddi_dp_voltage_max()
1119 if (drm_WARN_ON(&dev_priv->drm, in intel_ddi_dp_voltage_max()
1123 return index_to_dp_signal_levels[n_entries - 1] & in intel_ddi_dp_voltage_max()
1128 * We assume that the full set of pre-emphasis values can be
1140 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1143 if (crtc_state->lane_count == 4) in icl_combo_phy_loadgen_select()
1152 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_ddi_combo_vswing_program()
1158 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in icl_ddi_combo_vswing_program()
1159 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in icl_ddi_combo_vswing_program()
1166 intel_dp->hobl_active = is_hobl_buf_trans(trans); in icl_ddi_combo_vswing_program()
1168 intel_dp->hobl_active ? val : 0); in icl_ddi_combo_vswing_program()
1186 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | in icl_ddi_combo_vswing_program()
1187 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | in icl_ddi_combo_vswing_program()
1198 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | in icl_ddi_combo_vswing_program()
1199 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | in icl_ddi_combo_vswing_program()
1200 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); in icl_ddi_combo_vswing_program()
1209 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); in icl_ddi_combo_vswing_program()
1216 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_combo_phy_set_signal_levels()
1255 /* 5. Program swing and de-emphasis */ in icl_combo_phy_set_signal_levels()
1267 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_mg_phy_set_signal_levels()
1275 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in icl_mg_phy_set_signal_levels()
1276 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in icl_mg_phy_set_signal_levels()
1294 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1300 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1312 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1313 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1321 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1322 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1336 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()
1344 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1351 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_dkl_phy_set_signal_levels()
1376 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in tgl_dkl_phy_set_signal_levels()
1377 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in tgl_dkl_phy_set_signal_levels()
1391 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | in tgl_dkl_phy_set_signal_levels()
1392 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | in tgl_dkl_phy_set_signal_levels()
1393 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); in tgl_dkl_phy_set_signal_levels()
1401 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | in tgl_dkl_phy_set_signal_levels()
1402 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | in tgl_dkl_phy_set_signal_levels()
1403 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); in tgl_dkl_phy_set_signal_levels()
1443 drm_WARN(display->drm, 1, in translate_signal_level()
1444 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", in translate_signal_level()
1454 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level()
1470 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_level()
1474 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_ddi_level()
1475 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) in intel_ddi_level()
1484 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) in intel_ddi_level()
1485 level = n_entries - 1; in intel_ddi_level()
1494 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_set_signal_levels()
1497 enum port port = encoder->port; in hsw_set_signal_levels()
1503 /* HDMI ignores the rest */ in hsw_set_signal_levels()
1509 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", in hsw_set_signal_levels()
1512 intel_dp->DP &= ~DDI_BUF_EMP_MASK; in hsw_set_signal_levels()
1513 intel_dp->DP |= signal_levels; in hsw_set_signal_levels()
1515 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in hsw_set_signal_levels()
1522 mutex_lock(&i915->display.dpll.lock); in _icl_ddi_enable_clock()
1532 mutex_unlock(&i915->display.dpll.lock); in _icl_ddi_enable_clock()
1538 mutex_lock(&i915->display.dpll.lock); in _icl_ddi_disable_clock()
1542 mutex_unlock(&i915->display.dpll.lock); in _icl_ddi_disable_clock()
1565 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_enable_clock()
1566 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in adls_ddi_enable_clock()
1569 if (drm_WARN_ON(&i915->drm, !pll)) in adls_ddi_enable_clock()
1574 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), in adls_ddi_enable_clock()
1580 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_disable_clock()
1589 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_is_clock_enabled()
1598 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_get_pll()
1609 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_enable_clock()
1610 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in rkl_ddi_enable_clock()
1613 if (drm_WARN_ON(&i915->drm, !pll)) in rkl_ddi_enable_clock()
1618 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in rkl_ddi_enable_clock()
1624 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_disable_clock()
1633 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_is_clock_enabled()
1642 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_get_pll()
1653 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_enable_clock()
1654 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in dg1_ddi_enable_clock()
1657 if (drm_WARN_ON(&i915->drm, !pll)) in dg1_ddi_enable_clock()
1664 if (drm_WARN_ON(&i915->drm, in dg1_ddi_enable_clock()
1665 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || in dg1_ddi_enable_clock()
1666 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) in dg1_ddi_enable_clock()
1671 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in dg1_ddi_enable_clock()
1677 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_disable_clock()
1686 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_is_clock_enabled()
1695 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_get_pll()
1719 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_enable_clock()
1720 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_combo_enable_clock()
1723 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_combo_enable_clock()
1728 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in icl_ddi_combo_enable_clock()
1734 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_disable_clock()
1743 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_is_clock_enabled()
1752 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_get_pll()
1763 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_enable_clock()
1764 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in jsl_ddi_tc_enable_clock()
1765 enum port port = encoder->port; in jsl_ddi_tc_enable_clock()
1767 if (drm_WARN_ON(&i915->drm, !pll)) in jsl_ddi_tc_enable_clock()
1781 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_disable_clock()
1782 enum port port = encoder->port; in jsl_ddi_tc_disable_clock()
1791 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_is_clock_enabled()
1792 enum port port = encoder->port; in jsl_ddi_tc_is_clock_enabled()
1806 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_enable_clock()
1807 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_enable_clock()
1809 enum port port = encoder->port; in icl_ddi_tc_enable_clock()
1811 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_enable_clock()
1817 mutex_lock(&i915->display.dpll.lock); in icl_ddi_tc_enable_clock()
1822 mutex_unlock(&i915->display.dpll.lock); in icl_ddi_tc_enable_clock()
1827 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_disable_clock()
1829 enum port port = encoder->port; in icl_ddi_tc_disable_clock()
1831 mutex_lock(&i915->display.dpll.lock); in icl_ddi_tc_disable_clock()
1836 mutex_unlock(&i915->display.dpll.lock); in icl_ddi_tc_disable_clock()
1843 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_is_clock_enabled()
1845 enum port port = encoder->port; in icl_ddi_tc_is_clock_enabled()
1860 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_get_pll()
1862 enum port port = encoder->port; in icl_ddi_tc_get_pll()
1890 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in bxt_ddi_get_pll()
1893 switch (encoder->port) { in bxt_ddi_get_pll()
1904 MISSING_CASE(encoder->port); in bxt_ddi_get_pll()
1914 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_enable_clock()
1915 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in skl_ddi_enable_clock()
1916 enum port port = encoder->port; in skl_ddi_enable_clock()
1918 if (drm_WARN_ON(&i915->drm, !pll)) in skl_ddi_enable_clock()
1921 mutex_lock(&i915->display.dpll.lock); in skl_ddi_enable_clock()
1926 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | in skl_ddi_enable_clock()
1929 mutex_unlock(&i915->display.dpll.lock); in skl_ddi_enable_clock()
1934 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_disable_clock()
1935 enum port port = encoder->port; in skl_ddi_disable_clock()
1937 mutex_lock(&i915->display.dpll.lock); in skl_ddi_disable_clock()
1942 mutex_unlock(&i915->display.dpll.lock); in skl_ddi_disable_clock()
1947 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_is_clock_enabled()
1948 enum port port = encoder->port; in skl_ddi_is_clock_enabled()
1959 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_get_pll()
1960 enum port port = encoder->port; in skl_ddi_get_pll()
1982 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_enable_clock()
1983 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in hsw_ddi_enable_clock()
1984 enum port port = encoder->port; in hsw_ddi_enable_clock()
1986 if (drm_WARN_ON(&i915->drm, !pll)) in hsw_ddi_enable_clock()
1994 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_disable_clock()
1995 enum port port = encoder->port; in hsw_ddi_disable_clock()
2002 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_is_clock_enabled()
2003 enum port port = encoder->port; in hsw_ddi_is_clock_enabled()
2010 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_get_pll()
2011 enum port port = encoder->port; in hsw_ddi_get_pll()
2049 if (encoder->enable_clock) in intel_ddi_enable_clock()
2050 encoder->enable_clock(encoder, crtc_state); in intel_ddi_enable_clock()
2055 if (encoder->disable_clock) in intel_ddi_disable_clock()
2056 encoder->disable_clock(encoder); in intel_ddi_disable_clock()
2061 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_sanitize_encoder_pll_mapping()
2069 if (encoder->type == INTEL_OUTPUT_DP_MST) in intel_ddi_sanitize_encoder_pll_mapping()
2072 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { in intel_ddi_sanitize_encoder_pll_mapping()
2081 if (drm_WARN_ON(&i915->drm, is_mst)) in intel_ddi_sanitize_encoder_pll_mapping()
2085 port_mask = BIT(encoder->port); in intel_ddi_sanitize_encoder_pll_mapping()
2086 ddi_clk_needed = encoder->base.crtc; in intel_ddi_sanitize_encoder_pll_mapping()
2088 if (encoder->type == INTEL_OUTPUT_DSI) { in intel_ddi_sanitize_encoder_pll_mapping()
2096 for_each_intel_encoder(&i915->drm, other_encoder) { in intel_ddi_sanitize_encoder_pll_mapping()
2100 if (drm_WARN_ON(&i915->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2101 port_mask & BIT(other_encoder->port))) in intel_ddi_sanitize_encoder_pll_mapping()
2111 if (ddi_clk_needed || !encoder->is_clock_enabled || in intel_ddi_sanitize_encoder_pll_mapping()
2112 !encoder->is_clock_enabled(encoder)) in intel_ddi_sanitize_encoder_pll_mapping()
2115 drm_dbg_kms(&i915->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2117 encoder->base.base.id, encoder->base.name); in intel_ddi_sanitize_encoder_pll_mapping()
2119 encoder->disable_clock(encoder); in intel_ddi_sanitize_encoder_pll_mapping()
2126 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in icl_program_mg_dp_mode()
2127 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in icl_program_mg_dp_mode()
2134 if (!intel_encoder_is_tc(&dig_port->base) || in icl_program_mg_dp_mode()
2151 width = crtc_state->lane_count; in icl_program_mg_dp_mode()
2155 drm_WARN_ON(&dev_priv->drm, in icl_program_mg_dp_mode()
2213 return crtc_state->mst_master_transcoder; in tgl_dp_tp_transcoder()
2215 return crtc_state->cpu_transcoder; in tgl_dp_tp_transcoder()
2221 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dp_tp_ctl_reg()
2227 return DP_TP_CTL(encoder->port); in dp_tp_ctl_reg()
2233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dp_tp_status_reg()
2239 return DP_TP_STATUS(encoder->port); in dp_tp_status_reg()
2258 drm_err(display->drm, "Timed out waiting for ACT sent\n"); in intel_ddi_wait_for_act_sent()
2267 if (!crtc_state->vrr.enable) in intel_dp_sink_set_msa_timing_par_ignore_state()
2270 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, in intel_dp_sink_set_msa_timing_par_ignore_state()
2272 drm_dbg_kms(display->drm, in intel_dp_sink_set_msa_timing_par_ignore_state()
2283 if (!crtc_state->fec_enable) in intel_dp_sink_set_fec_ready()
2286 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, in intel_dp_sink_set_fec_ready()
2288 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", in intel_dp_sink_set_fec_ready()
2292 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, in intel_dp_sink_set_fec_ready()
2294 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); in intel_dp_sink_set_fec_ready()
2311 struct intel_display *display = to_intel_display(aux->drm_dev); in wait_for_fec_detected()
2321 drm_dbg_kms(display->drm, in wait_for_fec_detected()
2338 if (!crtc_state->fec_enable) in intel_ddi_wait_for_fec_status()
2349 drm_err(display->drm, in intel_ddi_wait_for_fec_status()
2359 ret = wait_for_fec_detected(&intel_dp->aux, enabled); in intel_ddi_wait_for_fec_status()
2374 if (!crtc_state->fec_enable) in intel_ddi_enable_fec()
2388 drm_dbg_kms(display->drm, "Retry FEC enabling\n"); in intel_ddi_enable_fec()
2405 drm_err(display->drm, "Failed to enable FEC after retries\n"); in intel_ddi_enable_fec()
2411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_disable_fec()
2413 if (!crtc_state->fec_enable) in intel_ddi_disable_fec()
2424 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_power_up_lanes()
2431 crtc_state->lane_count, in intel_ddi_power_up_lanes()
2432 dig_port->lane_reversal); in intel_ddi_power_up_lanes()
2453 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_mso_get_config()
2454 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_ddi_mso_get_config()
2455 enum pipe pipe = crtc->pipe; in intel_ddi_mso_get_config()
2463 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; in intel_ddi_mso_get_config()
2464 if (!pipe_config->splitter.enable) in intel_ddi_mso_get_config()
2467 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { in intel_ddi_mso_get_config()
2468 pipe_config->splitter.enable = false; in intel_ddi_mso_get_config()
2474 drm_WARN(&i915->drm, true, in intel_ddi_mso_get_config()
2478 pipe_config->splitter.link_count = 2; in intel_ddi_mso_get_config()
2481 pipe_config->splitter.link_count = 4; in intel_ddi_mso_get_config()
2485 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); in intel_ddi_mso_get_config()
2490 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_mso_configure()
2491 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_ddi_mso_configure()
2492 enum pipe pipe = crtc->pipe; in intel_ddi_mso_configure()
2498 if (crtc_state->splitter.enable) { in intel_ddi_mso_configure()
2500 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); in intel_ddi_mso_configure()
2501 if (crtc_state->splitter.link_count == 2) in intel_ddi_mso_configure()
2532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_ddi_enable_d2d()
2533 enum port port = encoder->port; in mtl_ddi_enable_d2d()
2549 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_enable_d2d()
2559 enum port port = encoder->port; in mtl_port_buf_ctl_program()
2562 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); in mtl_port_buf_ctl_program()
2569 if (dig_port->lane_reversal) in mtl_port_buf_ctl_program()
2579 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in mtl_port_buf_ctl_io_selection()
2585 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), in mtl_port_buf_ctl_io_selection()
2599 crtc_state->port_clock, in mtl_ddi_pre_enable_dp()
2600 crtc_state->lane_count); in mtl_ddi_pre_enable_dp()
2633 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. in mtl_ddi_pre_enable_dp()
2650 to_intel_connector(conn_state->connector), in mtl_ddi_pre_enable_dp()
2669 * stream or multi-stream master transcoder" can just be performed in mtl_ddi_pre_enable_dp()
2678 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in mtl_ddi_pre_enable_dp()
2694 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); in mtl_ddi_pre_enable_dp()
2709 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_ddi_pre_enable_dp()
2715 crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
2716 crtc_state->lane_count); in tgl_ddi_pre_enable_dp()
2735 * 3. For non-TBT Type-C ports, set FIA lane count in tgl_ddi_pre_enable_dp()
2739 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). in tgl_ddi_pre_enable_dp()
2746 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only in tgl_ddi_pre_enable_dp()
2753 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in tgl_ddi_pre_enable_dp()
2754 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in tgl_ddi_pre_enable_dp()
2755 dig_port->ddi_io_power_domain); in tgl_ddi_pre_enable_dp()
2767 * stream or multi-stream master transcoder" can just be performed in tgl_ddi_pre_enable_dp()
2792 encoder->set_signal_levels(encoder, crtc_state); in tgl_ddi_pre_enable_dp()
2811 to_intel_connector(conn_state->connector), in tgl_ddi_pre_enable_dp()
2826 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in tgl_ddi_pre_enable_dp()
2841 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); in tgl_ddi_pre_enable_dp()
2856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_ddi_pre_enable_dp()
2857 enum port port = encoder->port; in hsw_ddi_pre_enable_dp()
2862 drm_WARN_ON(&dev_priv->drm, in hsw_ddi_pre_enable_dp()
2865 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); in hsw_ddi_pre_enable_dp()
2868 crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
2869 crtc_state->lane_count); in hsw_ddi_pre_enable_dp()
2882 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in hsw_ddi_pre_enable_dp()
2883 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in hsw_ddi_pre_enable_dp()
2884 dig_port->ddi_io_power_domain); in hsw_ddi_pre_enable_dp()
2892 encoder->set_signal_levels(encoder, crtc_state); in hsw_ddi_pre_enable_dp()
2901 to_intel_connector(conn_state->connector), in hsw_ddi_pre_enable_dp()
2929 if (crtc_state->has_panel_replay) in intel_ddi_pre_enable_dp()
2952 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_pre_enable_hdmi()
2953 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_enable_hdmi()
2958 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in intel_ddi_pre_enable_hdmi()
2959 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in intel_ddi_pre_enable_hdmi()
2960 dig_port->ddi_io_power_domain); in intel_ddi_pre_enable_hdmi()
2966 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable_hdmi()
2967 crtc_state->has_infoframe, in intel_ddi_pre_enable_hdmi()
2972 * Note: Also called from the ->pre_enable of the first active MST stream
2977 * - conn_state will be NULL
2979 * - encoder will be the primary encoder (i.e. mst->primary)
2981 * - the main connector associated with this port won't be active or linked to a
2984 * - crtc_state will be the state of the first stream to be activated on this
2994 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_enable()
2995 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_pre_enable()
2996 enum pipe pipe = crtc->pipe; in intel_ddi_pre_enable()
2998 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); in intel_ddi_pre_enable()
3013 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_pre_enable()
3014 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable()
3015 crtc_state->has_infoframe, in intel_ddi_pre_enable()
3023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_ddi_disable_d2d_link()
3024 enum port port = encoder->port; in mtl_ddi_disable_d2d_link()
3040 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_disable_d2d_link()
3047 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_disable_ddi_buf()
3048 enum port port = encoder->port; in mtl_disable_ddi_buf()
3074 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in disable_ddi_buf()
3075 enum port port = encoder->port; in disable_ddi_buf()
3099 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_disable_ddi_buf()
3118 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_dp()
3120 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_post_disable_dp()
3137 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_ddi_post_disable_dp()
3156 * From TGL spec: "If single stream or multi-stream master transcoder: in intel_ddi_post_disable_dp()
3166 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); in intel_ddi_post_disable_dp()
3170 dig_port->ddi_io_power_domain, in intel_ddi_post_disable_dp()
3175 /* De-select Thunderbolt */ in intel_ddi_post_disable_dp()
3177 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), in intel_ddi_post_disable_dp()
3186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_hdmi()
3188 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_post_disable_hdmi()
3191 dig_port->set_infoframes(encoder, false, in intel_ddi_post_disable_hdmi()
3202 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); in intel_ddi_post_disable_hdmi()
3205 dig_port->ddi_io_power_domain, in intel_ddi_post_disable_hdmi()
3219 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_hdmi_or_sst()
3237 drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, 0); in intel_ddi_post_disable_hdmi_or_sst()
3241 intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), in intel_ddi_post_disable_hdmi_or_sst()
3245 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); in intel_ddi_post_disable_hdmi_or_sst()
3264 * Note: Also called from the ->post_disable of the last active MST stream
3279 * - old_conn_state will be NULL in intel_ddi_post_disable()
3280 * - encoder will be the main encoder (ie. mst->primary) in intel_ddi_post_disable()
3281 * - the main connector associated with this port in intel_ddi_post_disable()
3283 * - old_crtc_state will be the state of the last stream to in intel_ddi_post_disable()
3299 * Note: Also called from the ->post_pll_disable of the last active MST stream
3324 if (!crtc_state->sync_mode_slaves_mask) in trans_port_sync_stop_link_train()
3327 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in trans_port_sync_stop_link_train()
3329 to_intel_encoder(conn_state->best_encoder); in trans_port_sync_stop_link_train()
3330 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); in trans_port_sync_stop_link_train()
3339 if (slave_crtc_state->master_transcoder != in trans_port_sync_stop_link_train()
3340 crtc_state->cpu_transcoder) in trans_port_sync_stop_link_train()
3358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_enable_dp()
3361 enum port port = encoder->port; in intel_ddi_enable_dp()
3369 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_enable_dp()
3386 drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); in gen9_chicken_trans_reg_by_port()
3388 if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) in gen9_chicken_trans_reg_by_port()
3400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_enable_hdmi()
3402 struct drm_connector *connector = conn_state->connector; in intel_ddi_enable_hdmi()
3403 enum port port = encoder->port; in intel_ddi_enable_hdmi()
3407 crtc_state->hdmi_high_tmds_clock_ratio, in intel_ddi_enable_hdmi()
3408 crtc_state->hdmi_scrambling)) in intel_ddi_enable_hdmi()
3409 drm_dbg_kms(&dev_priv->drm, in intel_ddi_enable_hdmi()
3411 connector->base.id, connector->name); in intel_ddi_enable_hdmi()
3420 encoder->set_signal_levels(encoder, crtc_state); in intel_ddi_enable_hdmi()
3459 /* In HDMI/DVI mode, the port width, and swing/emphasis values in intel_ddi_enable_hdmi()
3464 * these are both 0 for HDMI. in intel_ddi_enable_hdmi()
3472 if (dig_port->lane_reversal) in intel_ddi_enable_hdmi()
3474 if (dig_port->ddi_a_4_lanes) in intel_ddi_enable_hdmi()
3478 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); in intel_ddi_enable_hdmi()
3483 if (dig_port->lane_reversal) in intel_ddi_enable_hdmi()
3489 buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_enable_hdmi()
3494 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); in intel_ddi_enable_hdmi()
3510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable()
3516 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_ddi_enable()
3517 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); in intel_ddi_enable()
3527 /* Enable/Disable DP2.0 SDP split config before transcoder */ in intel_ddi_enable()
3540 drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0); in intel_ddi_enable()
3570 to_intel_connector(old_conn_state->connector); in intel_ddi_disable_dp()
3572 intel_dp->link_trained = false; in intel_ddi_disable_dp()
3589 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_disable_hdmi()
3590 struct drm_connector *connector = old_conn_state->connector; in intel_ddi_disable_hdmi()
3594 drm_dbg_kms(&i915->drm, in intel_ddi_disable_hdmi()
3596 connector->base.id, connector->name); in intel_ddi_disable_hdmi()
3606 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); in intel_ddi_disable()
3658 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_update_active_dpll()
3667 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, in intel_ddi_update_active_dpll()
3673 * Note: Also called from the ->pre_pll_enable of the first active MST stream
3683 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_pll_enable()
3688 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_pll_enable()
3690 intel_tc_port_get_link(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3699 * Type-C ports. Skip this step for TBT. in intel_ddi_pre_pll_enable()
3701 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3704 crtc_state->lane_lat_optim_mask); in intel_ddi_pre_pll_enable()
3709 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adlp_tbt_to_dp_alt_switch_wa()
3722 struct intel_encoder *encoder = &dig_port->base; in mtl_ddi_prepare_link_retrain()
3723 enum port port = encoder->port; in mtl_ddi_prepare_link_retrain()
3741 if (crtc_state->enhanced_framing) in mtl_ddi_prepare_link_retrain()
3751 encoder->set_signal_levels(encoder, crtc_state); in mtl_ddi_prepare_link_retrain()
3757 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in mtl_ddi_prepare_link_retrain()
3759 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; in mtl_ddi_prepare_link_retrain()
3761 intel_de_write(display, DDI_BUF_CTL(port), intel_dp->DP); in mtl_ddi_prepare_link_retrain()
3772 struct intel_encoder *encoder = &dig_port->base; in intel_ddi_prepare_link_retrain()
3773 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_prepare_link_retrain()
3774 enum port port = encoder->port; in intel_ddi_prepare_link_retrain()
3802 if (crtc_state->enhanced_framing) in intel_ddi_prepare_link_retrain()
3812 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in intel_ddi_prepare_link_retrain()
3813 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in intel_ddi_prepare_link_retrain()
3823 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_link_train()
3824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_set_link_train()
3854 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_idle_link_train()
3855 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_set_idle_link_train()
3856 enum port port = encoder->port; in intel_ddi_set_idle_link_train()
3864 * issue where we enable the pipe while not in idle link-training mode. in intel_ddi_set_idle_link_train()
3874 drm_err(&dev_priv->drm, in intel_ddi_set_idle_link_train()
3893 if (crtc_state->port_clock > 594000) in tgl_ddi_min_voltage_level()
3901 if (crtc_state->port_clock > 594000) in jsl_ddi_min_voltage_level()
3909 if (crtc_state->port_clock > 594000) in icl_ddi_min_voltage_level()
3917 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_compute_min_voltage_level()
3920 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3922 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3924 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3926 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3955 return master_select - 1; in bdw_transcoder_master_readout()
3960 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in bdw_get_trans_port_sync_config()
3965 crtc_state->master_transcoder = in bdw_get_trans_port_sync_config()
3966 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); in bdw_get_trans_port_sync_config()
3980 crtc_state->cpu_transcoder) in bdw_get_trans_port_sync_config()
3981 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); in bdw_get_trans_port_sync_config()
3986 drm_WARN_ON(&dev_priv->drm, in bdw_get_trans_port_sync_config()
3987 crtc_state->master_transcoder != INVALID_TRANSCODER && in bdw_get_trans_port_sync_config()
3988 crtc_state->sync_mode_slaves_mask); in bdw_get_trans_port_sync_config()
3997 crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); in intel_ddi_read_func_ctl_dvi()
3999 crtc_state->lane_count = in intel_ddi_read_func_ctl_dvi()
4002 crtc_state->lane_count = 4; in intel_ddi_read_func_ctl_dvi()
4009 crtc_state->has_hdmi_sink = true; in intel_ddi_read_func_ctl_hdmi()
4011 crtc_state->infoframes.enable |= in intel_ddi_read_func_ctl_hdmi()
4014 if (crtc_state->infoframes.enable) in intel_ddi_read_func_ctl_hdmi()
4015 crtc_state->has_infoframe = true; in intel_ddi_read_func_ctl_hdmi()
4018 crtc_state->hdmi_scrambling = true; in intel_ddi_read_func_ctl_hdmi()
4020 crtc_state->hdmi_high_tmds_clock_ratio = true; in intel_ddi_read_func_ctl_hdmi()
4031 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_ddi_read_func_ctl_fdi()
4032 crtc_state->enhanced_framing = in intel_ddi_read_func_ctl_fdi()
4042 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_read_func_ctl_dp_sst()
4044 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_read_func_ctl_dp_sst()
4046 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_read_func_ctl_dp_sst()
4047 crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); in intel_ddi_read_func_ctl_dp_sst()
4049 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); in intel_ddi_read_func_ctl_dp_sst()
4050 crtc_state->lane_count = in intel_ddi_read_func_ctl_dp_sst()
4055 crtc_state->mst_master_transcoder = in intel_ddi_read_func_ctl_dp_sst()
4058 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); in intel_ddi_read_func_ctl_dp_sst()
4059 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); in intel_ddi_read_func_ctl_dp_sst()
4061 crtc_state->enhanced_framing = in intel_ddi_read_func_ctl_dp_sst()
4066 crtc_state->fec_enable = in intel_ddi_read_func_ctl_dp_sst()
4070 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_read_func_ctl_dp_sst()
4071 crtc_state->infoframes.enable |= in intel_ddi_read_func_ctl_dp_sst()
4074 crtc_state->infoframes.enable |= in intel_ddi_read_func_ctl_dp_sst()
4083 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_read_func_ctl_dp_mst()
4084 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_read_func_ctl_dp_mst()
4086 crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); in intel_ddi_read_func_ctl_dp_mst()
4087 crtc_state->lane_count = in intel_ddi_read_func_ctl_dp_mst()
4091 crtc_state->mst_master_transcoder = in intel_ddi_read_func_ctl_dp_mst()
4094 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); in intel_ddi_read_func_ctl_dp_mst()
4097 crtc_state->fec_enable = in intel_ddi_read_func_ctl_dp_mst()
4101 crtc_state->infoframes.enable |= in intel_ddi_read_func_ctl_dp_mst()
4109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_read_func_ctl()
4110 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_read_func_ctl()
4123 pipe_config->hw.adjusted_mode.flags |= flags; in intel_ddi_read_func_ctl()
4127 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
4130 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
4133 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
4136 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
4159 * encoder's ->get_config(). in intel_ddi_read_func_ctl()
4169 * Note: Also called from the ->get_config of the MST stream encoders on their
4176 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_config()
4177 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_get_config()
4180 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) in intel_ddi_get_config()
4187 pipe_config->has_audio = in intel_ddi_get_config()
4190 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_get_config()
4191 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
4196 pipe_config->lane_lat_optim_mask = in intel_ddi_get_config()
4205 &pipe_config->infoframes.avi); in intel_ddi_get_config()
4208 &pipe_config->infoframes.spd); in intel_ddi_get_config()
4211 &pipe_config->infoframes.hdmi); in intel_ddi_get_config()
4214 &pipe_config->infoframes.drm); in intel_ddi_get_config()
4232 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_get_clock()
4234 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in intel_ddi_get_clock()
4237 if (drm_WARN_ON(&i915->drm, !pll)) in intel_ddi_get_clock()
4240 port_dpll->pll = pll; in intel_ddi_get_clock()
4241 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); in intel_ddi_get_clock()
4242 drm_WARN_ON(&i915->drm, !pll_active); in intel_ddi_get_clock()
4246 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
4247 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
4253 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4255 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) in mtl_ddi_get_config()
4256 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); in mtl_ddi_get_config()
4258 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4266 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4267 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4302 return pll->info->id == DPLL_ID_ICL_TBTPLL; in icl_ddi_tc_pll_is_tbt()
4309 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_port_pll_type()
4310 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_port_pll_type()
4312 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_port_pll_type()
4325 if (!encoder->port_pll_type) in intel_ddi_port_pll_type()
4328 return encoder->port_pll_type(encoder, crtc_state); in intel_ddi_port_pll_type()
4335 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_get_clock()
4340 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_get_clock()
4348 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in icl_ddi_tc_get_clock()
4350 port_dpll->pll = pll; in icl_ddi_tc_get_clock()
4351 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); in icl_ddi_tc_get_clock()
4352 drm_WARN_ON(&i915->drm, !pll_active); in icl_ddi_tc_get_clock()
4356 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) in icl_ddi_tc_get_clock()
4357 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); in icl_ddi_tc_get_clock()
4359 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
4360 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()
4406 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_initial_fastset_check()
4410 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", in intel_ddi_initial_fastset_check()
4411 encoder->base.base.id, encoder->base.name); in intel_ddi_initial_fastset_check()
4412 crtc_state->uapi.mode_changed = true; in intel_ddi_initial_fastset_check()
4428 switch (conn_state->connector->connector_type) { in intel_ddi_compute_output_type()
4436 MISSING_CASE(conn_state->connector->connector_type); in intel_ddi_compute_output_type()
4445 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_compute_config()
4446 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_compute_config()
4447 enum port port = encoder->port; in intel_ddi_compute_config()
4451 pipe_config->cpu_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config()
4454 pipe_config->has_hdmi_sink = in intel_ddi_compute_config()
4465 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && in intel_ddi_compute_config()
4466 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_ddi_compute_config()
4467 pipe_config->pch_pfit.force_thru = in intel_ddi_compute_config()
4468 pipe_config->pch_pfit.enabled || in intel_ddi_compute_config()
4469 pipe_config->crc_enabled; in intel_ddi_compute_config()
4472 pipe_config->lane_lat_optim_mask = in intel_ddi_compute_config()
4473 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_ddi_compute_config()
4487 mode1->clock == mode2->clock; /* we want an exact match */ in mode_equal()
4493 return m_n_1->tu == m_n_2->tu && in m_n_equal()
4494 m_n_1->data_m == m_n_2->data_m && in m_n_equal()
4495 m_n_1->data_n == m_n_2->data_n && in m_n_equal()
4496 m_n_1->link_m == m_n_2->link_m && in m_n_equal()
4497 m_n_1->link_n == m_n_2->link_n; in m_n_equal()
4507 return crtc_state1->hw.active && crtc_state2->hw.active && in crtcs_port_sync_compatible()
4508 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && in crtcs_port_sync_compatible()
4509 crtc_state1->output_types == crtc_state2->output_types && in crtcs_port_sync_compatible()
4510 crtc_state1->output_format == crtc_state2->output_format && in crtcs_port_sync_compatible()
4511 crtc_state1->lane_count == crtc_state2->lane_count && in crtcs_port_sync_compatible()
4512 crtc_state1->port_clock == crtc_state2->port_clock && in crtcs_port_sync_compatible()
4513 mode_equal(&crtc_state1->hw.adjusted_mode, in crtcs_port_sync_compatible()
4514 &crtc_state2->hw.adjusted_mode) && in crtcs_port_sync_compatible()
4515 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); in crtcs_port_sync_compatible()
4524 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); in intel_ddi_port_sync_transcoders()
4526 to_intel_atomic_state(ref_crtc_state->uapi.state); in intel_ddi_port_sync_transcoders()
4540 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { in intel_ddi_port_sync_transcoders()
4541 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); in intel_ddi_port_sync_transcoders()
4547 if (!connector->has_tile || in intel_ddi_port_sync_transcoders()
4548 connector->tile_group->id != in intel_ddi_port_sync_transcoders()
4556 transcoders |= BIT(crtc_state->cpu_transcoder); in intel_ddi_port_sync_transcoders()
4566 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_compute_config_late()
4567 struct drm_connector *connector = conn_state->connector; in intel_ddi_compute_config_late()
4570 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", in intel_ddi_compute_config_late()
4571 encoder->base.base.id, encoder->base.name, in intel_ddi_compute_config_late()
4572 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
4574 if (connector->has_tile) in intel_ddi_compute_config_late()
4576 connector->tile_group->id); in intel_ddi_compute_config_late()
4583 crtc_state->master_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config_late()
4585 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; in intel_ddi_compute_config_late()
4587 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { in intel_ddi_compute_config_late()
4588 crtc_state->master_transcoder = INVALID_TRANSCODER; in intel_ddi_compute_config_late()
4589 crtc_state->sync_mode_slaves_mask = in intel_ddi_compute_config_late()
4590 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); in intel_ddi_compute_config_late()
4598 struct drm_i915_private *i915 = to_i915(encoder->dev); in intel_ddi_encoder_destroy()
4602 if (intel_encoder_is_tc(&dig_port->base)) in intel_ddi_encoder_destroy()
4607 kfree(dig_port->hdcp_port_data.streams); in intel_ddi_encoder_destroy()
4616 intel_dp->reset_link_params = true; in intel_ddi_encoder_reset()
4621 if (intel_encoder_is_tc(&dig_port->base)) in intel_ddi_encoder_reset()
4642 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_ddi_init_dp_connector()
4644 enum port port = dig_port->base.port; in intel_ddi_init_dp_connector()
4648 return -ENOMEM; in intel_ddi_init_dp_connector()
4650 dig_port->dp.output_reg = DDI_BUF_CTL(port); in intel_ddi_init_dp_connector()
4652 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4654 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4655 dig_port->dp.set_link_train = intel_ddi_set_link_train; in intel_ddi_init_dp_connector()
4656 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; in intel_ddi_init_dp_connector()
4658 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; in intel_ddi_init_dp_connector()
4659 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; in intel_ddi_init_dp_connector()
4663 return -EINVAL; in intel_ddi_init_dp_connector()
4666 if (dig_port->base.type == INTEL_OUTPUT_EDP) { in intel_ddi_init_dp_connector()
4667 struct drm_device *dev = dig_port->base.base.dev; in intel_ddi_init_dp_connector()
4670 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); in intel_ddi_init_dp_connector()
4672 drm_connector_attach_privacy_screen_provider(&connector->base, in intel_ddi_init_dp_connector()
4674 } else if (PTR_ERR(privacy_screen) != -ENODEV) { in intel_ddi_init_dp_connector()
4675 drm_warn(dev, "Error getting privacy-screen\n"); in intel_ddi_init_dp_connector()
4685 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_reset_link()
4686 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); in intel_hdmi_reset_link() local
4687 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_reset_link()
4688 struct i2c_adapter *ddc = connector->base.ddc; in intel_hdmi_reset_link()
4695 if (connector->base.status != connector_status_connected) in intel_hdmi_reset_link()
4698 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, in intel_hdmi_reset_link()
4703 conn_state = connector->base.state; in intel_hdmi_reset_link()
4705 crtc = to_intel_crtc(conn_state->crtc); in intel_hdmi_reset_link()
4709 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_hdmi_reset_link()
4713 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_hdmi_reset_link()
4715 drm_WARN_ON(&dev_priv->drm, in intel_hdmi_reset_link()
4718 if (!crtc_state->hw.active) in intel_hdmi_reset_link()
4721 if (!crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4722 !crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4725 if (conn_state->commit && in intel_hdmi_reset_link()
4726 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_hdmi_reset_link()
4731 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", in intel_hdmi_reset_link()
4732 connector->base.base.id, connector->base.name, ret); in intel_hdmi_reset_link()
4737 crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4739 crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4743 * HDMI 2.0 says that one should not send scrambled data in intel_hdmi_reset_link()
4751 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); in intel_hdmi_reset_link()
4756 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_link_check()
4759 /* TODO: Move checking the HDMI link state here as well. */ in intel_ddi_link_check()
4760 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); in intel_ddi_link_check()
4770 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_hotplug()
4782 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { in intel_ddi_hotplug()
4785 drm_WARN_ON(encoder->base.dev, ret); in intel_ddi_hotplug()
4792 * Unpowered type-c dongles can take some time to boot and be in intel_ddi_hotplug()
4796 * On many platforms the HDMI live state signal is known to be in intel_ddi_hotplug()
4807 * Type-c connectors which get their HPD signal deasserted then in intel_ddi_hotplug()
4810 * becomes functional. Retry the detection for 5 seconds on type-c in intel_ddi_hotplug()
4814 connector->hotplug_retries < (is_tc ? 5 : 1) && in intel_ddi_hotplug()
4815 !dig_port->dp.is_mst) in intel_ddi_hotplug()
4823 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in lpt_digital_port_connected()
4824 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; in lpt_digital_port_connected()
4831 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_digital_port_connected()
4832 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; in hsw_digital_port_connected()
4839 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bdw_digital_port_connected()
4840 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; in bdw_digital_port_connected()
4848 enum port port = dig_port->base.port; in intel_ddi_init_hdmi_connector()
4852 return -ENOMEM; in intel_ddi_init_hdmi_connector()
4854 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); in intel_ddi_init_hdmi_connector()
4858 * HDMI connector init failures may just mean conflicting DDC in intel_ddi_init_hdmi_connector()
4862 dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG; in intel_ddi_init_hdmi_connector()
4871 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_a_force_4_lanes()
4873 if (dig_port->base.port != PORT_A) in intel_ddi_a_force_4_lanes()
4876 if (dig_port->ddi_a_4_lanes) in intel_ddi_a_force_4_lanes()
4891 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_max_lanes()
4892 enum port port = dig_port->base.port; in intel_ddi_max_lanes()
4912 drm_dbg_kms(&dev_priv->drm, in intel_ddi_max_lanes()
4914 dig_port->ddi_a_4_lanes = true; in intel_ddi_max_lanes()
4925 return HPD_PORT_D + port - PORT_D_XELPD; in xelpd_hpd_pin()
4927 return HPD_PORT_TC1 + port - PORT_TC1; in xelpd_hpd_pin()
4929 return HPD_PORT_A + port - PORT_A; in xelpd_hpd_pin()
4936 return HPD_PORT_C + port - PORT_TC1; in dg1_hpd_pin()
4938 return HPD_PORT_A + port - PORT_A; in dg1_hpd_pin()
4945 return HPD_PORT_TC1 + port - PORT_TC1; in tgl_hpd_pin()
4947 return HPD_PORT_A + port - PORT_A; in tgl_hpd_pin()
4957 return HPD_PORT_C + port - PORT_TC1; in rkl_hpd_pin()
4959 return HPD_PORT_A + port - PORT_A; in rkl_hpd_pin()
4966 return HPD_PORT_TC1 + port - PORT_C; in icl_hpd_pin()
4968 return HPD_PORT_A + port - PORT_A; in icl_hpd_pin()
4980 return HPD_PORT_A + port - PORT_A; in ehl_hpd_pin()
4988 return HPD_PORT_A + port - PORT_A; in skl_hpd_pin()
5035 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
5036 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
5054 return true; /* no strap for DDI-E */ in port_strap_detected()
5068 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && in assert_has_icl_dsi()
5077 for_each_intel_encoder(&i915->drm, encoder) { in port_in_use()
5079 if (encoder->port == port) in port_in_use()
5089 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_ddi_init()
5102 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5111 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5134 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", in intel_ddi_init()
5151 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", in intel_ddi_init()
5156 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5157 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", in intel_ddi_init()
5163 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { in intel_ddi_init()
5164 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5173 dig_port->aux_ch = AUX_CH_NONE; in intel_ddi_init()
5175 encoder = &dig_port->base; in intel_ddi_init()
5176 encoder->devdata = devdata; in intel_ddi_init()
5179 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5182 port_name(port - PORT_D_XELPD + PORT_D), in intel_ddi_init()
5187 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5197 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5205 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
5212 mutex_init(&dig_port->hdcp_mutex); in intel_ddi_init()
5213 dig_port->num_hdcp_streams = 0; in intel_ddi_init()
5215 encoder->hotplug = intel_ddi_hotplug; in intel_ddi_init()
5216 encoder->compute_output_type = intel_ddi_compute_output_type; in intel_ddi_init()
5217 encoder->compute_config = intel_ddi_compute_config; in intel_ddi_init()
5218 encoder->compute_config_late = intel_ddi_compute_config_late; in intel_ddi_init()
5219 encoder->enable = intel_ddi_enable; in intel_ddi_init()
5220 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; in intel_ddi_init()
5221 encoder->pre_enable = intel_ddi_pre_enable; in intel_ddi_init()
5222 encoder->disable = intel_ddi_disable; in intel_ddi_init()
5223 encoder->post_pll_disable = intel_ddi_post_pll_disable; in intel_ddi_init()
5224 encoder->post_disable = intel_ddi_post_disable; in intel_ddi_init()
5225 encoder->update_pipe = intel_ddi_update_pipe; in intel_ddi_init()
5226 encoder->audio_enable = intel_audio_codec_enable; in intel_ddi_init()
5227 encoder->audio_disable = intel_audio_codec_disable; in intel_ddi_init()
5228 encoder->get_hw_state = intel_ddi_get_hw_state; in intel_ddi_init()
5229 encoder->sync_state = intel_ddi_sync_state; in intel_ddi_init()
5230 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; in intel_ddi_init()
5231 encoder->suspend = intel_ddi_encoder_suspend; in intel_ddi_init()
5232 encoder->shutdown = intel_ddi_encoder_shutdown; in intel_ddi_init()
5233 encoder->get_power_domains = intel_ddi_get_power_domains; in intel_ddi_init()
5235 encoder->type = INTEL_OUTPUT_DDI; in intel_ddi_init()
5236 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); in intel_ddi_init()
5237 encoder->port = port; in intel_ddi_init()
5238 encoder->cloneable = 0; in intel_ddi_init()
5239 encoder->pipe_mask = ~0; in intel_ddi_init()
5242 encoder->enable_clock = intel_mtl_pll_enable; in intel_ddi_init()
5243 encoder->disable_clock = intel_mtl_pll_disable; in intel_ddi_init()
5244 encoder->port_pll_type = intel_mtl_port_pll_type; in intel_ddi_init()
5245 encoder->get_config = mtl_ddi_get_config; in intel_ddi_init()
5247 encoder->enable_clock = intel_mpllb_enable; in intel_ddi_init()
5248 encoder->disable_clock = intel_mpllb_disable; in intel_ddi_init()
5249 encoder->get_config = dg2_ddi_get_config; in intel_ddi_init()
5251 encoder->enable_clock = adls_ddi_enable_clock; in intel_ddi_init()
5252 encoder->disable_clock = adls_ddi_disable_clock; in intel_ddi_init()
5253 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; in intel_ddi_init()
5254 encoder->get_config = adls_ddi_get_config; in intel_ddi_init()
5256 encoder->enable_clock = rkl_ddi_enable_clock; in intel_ddi_init()
5257 encoder->disable_clock = rkl_ddi_disable_clock; in intel_ddi_init()
5258 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; in intel_ddi_init()
5259 encoder->get_config = rkl_ddi_get_config; in intel_ddi_init()
5261 encoder->enable_clock = dg1_ddi_enable_clock; in intel_ddi_init()
5262 encoder->disable_clock = dg1_ddi_disable_clock; in intel_ddi_init()
5263 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; in intel_ddi_init()
5264 encoder->get_config = dg1_ddi_get_config; in intel_ddi_init()
5267 encoder->enable_clock = jsl_ddi_tc_enable_clock; in intel_ddi_init()
5268 encoder->disable_clock = jsl_ddi_tc_disable_clock; in intel_ddi_init()
5269 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; in intel_ddi_init()
5270 encoder->port_pll_type = icl_ddi_tc_port_pll_type; in intel_ddi_init()
5271 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5273 encoder->enable_clock = icl_ddi_combo_enable_clock; in intel_ddi_init()
5274 encoder->disable_clock = icl_ddi_combo_disable_clock; in intel_ddi_init()
5275 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; in intel_ddi_init()
5276 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5280 encoder->enable_clock = icl_ddi_tc_enable_clock; in intel_ddi_init()
5281 encoder->disable_clock = icl_ddi_tc_disable_clock; in intel_ddi_init()
5282 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; in intel_ddi_init()
5283 encoder->port_pll_type = icl_ddi_tc_port_pll_type; in intel_ddi_init()
5284 encoder->get_config = icl_ddi_tc_get_config; in intel_ddi_init()
5286 encoder->enable_clock = icl_ddi_combo_enable_clock; in intel_ddi_init()
5287 encoder->disable_clock = icl_ddi_combo_disable_clock; in intel_ddi_init()
5288 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; in intel_ddi_init()
5289 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5292 /* BXT/GLK have fixed PLL->port mapping */ in intel_ddi_init()
5293 encoder->get_config = bxt_ddi_get_config; in intel_ddi_init()
5295 encoder->enable_clock = skl_ddi_enable_clock; in intel_ddi_init()
5296 encoder->disable_clock = skl_ddi_disable_clock; in intel_ddi_init()
5297 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; in intel_ddi_init()
5298 encoder->get_config = skl_ddi_get_config; in intel_ddi_init()
5300 encoder->enable_clock = hsw_ddi_enable_clock; in intel_ddi_init()
5301 encoder->disable_clock = hsw_ddi_disable_clock; in intel_ddi_init()
5302 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; in intel_ddi_init()
5303 encoder->get_config = hsw_ddi_get_config; in intel_ddi_init()
5307 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; in intel_ddi_init()
5309 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; in intel_ddi_init()
5312 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; in intel_ddi_init()
5314 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; in intel_ddi_init()
5317 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; in intel_ddi_init()
5319 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; in intel_ddi_init()
5321 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; in intel_ddi_init()
5323 encoder->set_signal_levels = hsw_set_signal_levels; in intel_ddi_init()
5329 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); in intel_ddi_init()
5331 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); in intel_ddi_init()
5333 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); in intel_ddi_init()
5335 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); in intel_ddi_init()
5337 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); in intel_ddi_init()
5339 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); in intel_ddi_init()
5341 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); in intel_ddi_init()
5343 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); in intel_ddi_init()
5347 dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || in intel_ddi_init()
5350 dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; in intel_ddi_init()
5352 dig_port->dp.output_reg = INVALID_MMIO_REG; in intel_ddi_init()
5353 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); in intel_ddi_init()
5356 dig_port->aux_ch = intel_dp_aux_ch(encoder); in intel_ddi_init()
5357 if (dig_port->aux_ch == AUX_CH_NONE) in intel_ddi_init()
5369 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5370 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", in intel_ddi_init()
5373 is_legacy ? "legacy" : "non-legacy"); in intel_ddi_init()
5376 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; in intel_ddi_init()
5377 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; in intel_ddi_init()
5379 dig_port->lock = intel_tc_port_lock; in intel_ddi_init()
5380 dig_port->unlock = intel_tc_port_unlock; in intel_ddi_init()
5386 drm_WARN_ON(&dev_priv->drm, port > PORT_I); in intel_ddi_init()
5387 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); in intel_ddi_init()
5391 dig_port->connected = intel_tc_port_connected; in intel_ddi_init()
5393 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5395 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5397 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5400 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5402 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5405 dig_port->connected = hsw_digital_port_connected; in intel_ddi_init()
5407 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5416 dig_port->hpd_pulse = intel_dp_hpd_pulse; in intel_ddi_init()
5418 if (dig_port->dp.mso_link_count) in intel_ddi_init()
5419 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); in intel_ddi_init()
5423 * In theory we don't need the encoder->type check, in intel_ddi_init()
5426 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { in intel_ddi_init()
5434 drm_encoder_cleanup(&encoder->base); in intel_ddi_init()