527 	.cmn = 0x21,
553 	.cmn = 0x21,
579 	.cmn = 0x21,
605 	.cmn = 0x21,
631 	.cmn = 0x21,
657 	.cmn = 0x21,
683 	.cmn = 0x21,
709 	.cmn = 0x21,
735 	.cmn = 0x21,
786 	.cmn = {0x0500, /* cmn cfg0*/
787 		0x0005, /* cmn cfg1 */
788 		0x0000, /* cmn cfg2 */
789 		0x0000, /* cmn cfg3 */
811 	.cmn = {0x0500, /* cmn cfg0*/
812 		0x0005, /* cmn cfg1 */
813 		0x0000, /* cmn cfg2 */
814 		0x0000, /* cmn cfg3 */
836 	.cmn = {0x0500, /* cmn cfg0*/
837 		0x0005, /* cmn cfg1 */
838 		0x0000, /* cmn cfg2 */
839 		0x0000, /* cmn cfg3 */
861 	.cmn = {0x0500, /* cmn cfg0*/
862 		0x0005, /* cmn cfg1 */
863 		0x0000, /* cmn cfg2 */
864 		0x0000, /* cmn cfg3 */
887 	.cmn = {0x0700, /* cmn cfg0*/
888 		0x0005, /* cmn cfg1 */
889 		0x0000, /* cmn cfg2 */
890 		0x0000, /* cmn cfg3 */
911 	.cmn = {0x0500, /* cmn cfg0*/
912 		0x0005, /* cmn cfg1 */
913 		0x0000, /* cmn cfg2 */
914 		0x0000, /* cmn cfg3 */
936 	.cmn = {0x0500, /* cmn cfg0*/
937 		0x0005, /* cmn cfg1 */
938 		0x0000, /* cmn cfg2 */
939 		0x0000, /* cmn cfg3 */
975 	.cmn = { 0x0500,
1000 	.cmn = { 0x0500,
1025 	.cmn = { 0x0500,
1050 	.cmn = { 0x0500,
1075 	.cmn = { 0x0500,
1113 	.cmn = {0x0500, /* cmn cfg0*/
1114 		0x0005, /* cmn cfg1 */
1115 		0x0000, /* cmn cfg2 */
1116 		0x0000, /* cmn cfg3 */
1165 	.cmn = 0x1,
1191 	.cmn = 0x1,
1217 	.cmn = 0x1,
1243 	.cmn = 0x1,
1269 	.cmn = 0x1,
1296 	.cmn = 0x1,
1306 	.cmn = 0x1,
1316 	.cmn = 0x1,
1326 	.cmn = 0x1,
1336 	.cmn = 0x1,
1346 	.cmn = 0x1,
1356 	.cmn = 0x1,
1366 	.cmn = 0x1,
1376 	.cmn = 0x1,
1386 	.cmn = 0x1,
1396 	.cmn = 0x1,
1406 	.cmn = 0x1,
1416 	.cmn = 0x1,
1426 	.cmn = 0x1,
1436 	.cmn = 0x1,
1446 	.cmn = 0x1,
1456 	.cmn = 0x1,
1466 	.cmn = 0x1,
1476 	.cmn = 0x1,
1486 	.cmn = 0x1,
1496 	.cmn = 0x1,
1506 	.cmn = 0x1,
1516 	.cmn = 0x1,
1526 	.cmn = 0x1,
1536 	.cmn = 0x1,
1546 	.cmn = 0x1,
1556 	.cmn = 0x1,
1566 	.cmn = 0x1,
1576 	.cmn = 0x1,
1586 	.cmn = 0x1,
1596 	.cmn = 0x1,
1606 	.cmn = 0x1,
1616 	.cmn = 0x1,
1626 	.cmn = 0x1,
1636 	.cmn = 0x1,
1646 	.cmn = 0x1,
1656 	.cmn = 0x1,
1666 	.cmn = 0x1,
1676 	.cmn = 0x1,
1686 	.cmn = 0x1,
1748 	.cmn = { 0x0500, /* cmn cfg0*/
1749 		  0x0005, /* cmn cfg1 */
1750 		  0x0000, /* cmn cfg2 */
1751 		  0x0000, /* cmn cfg3 */
1773 	.cmn = { 0x0500, /* cmn cfg0*/
1774 		  0x0005, /* cmn cfg1 */
1775 		  0x0000, /* cmn cfg2 */
1776 		  0x0000, /* cmn cfg3 */
1798 	.cmn = { 0x0500, /* cmn cfg0*/
1799 		  0x0005, /* cmn cfg1 */
1800 		  0x0000, /* cmn cfg2 */
1801 		  0x0000, /* cmn cfg3 */
1823 	.cmn = { 0x0500, /* cmn cfg0*/
1824 		  0x0005, /* cmn cfg1 */
1825 		  0x0000, /* cmn cfg2 */
1826 		  0x0000, /* cmn cfg3 */
1848 	.cmn = { 0x0500, /* cmn cfg0*/
1849 		  0x0005, /* cmn cfg1 */
1850 		  0x0000, /* cmn cfg2 */
1851 		  0x0000, /* cmn cfg3 */
1873 	.cmn = { 0x0500, /* cmn cfg0*/
1874 		  0x0005, /* cmn cfg1 */
1875 		  0x0000, /* cmn cfg2 */
1876 		  0x0000, /* cmn cfg3 */
1898 	.cmn = { 0x0500, /* cmn cfg0*/
1899 		  0x0005, /* cmn cfg1 */
1900 		  0x0000, /* cmn cfg2 */
1901 		  0x0000, /* cmn cfg3 */
1923 	.cmn = { 0x0500, /* cmn cfg0*/
1924 		  0x0005, /* cmn cfg1 */
1925 		  0x0000, /* cmn cfg2 */
1926 		  0x0000, /* cmn cfg3 */
1948 	.cmn = { 0x0500, /* cmn cfg0*/
1949 		  0x0005, /* cmn cfg1 */
1950 		  0x0000, /* cmn cfg2 */
1951 		  0x0000, /* cmn cfg3 */
1973 	.cmn = { 0x0500, /* cmn cfg0*/
1974 		  0x0005, /* cmn cfg1 */
1975 		  0x0000, /* cmn cfg2 */
1976 		  0x0000, /* cmn cfg3 */
2103 	pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0));  in intel_c10pll_readout_hw_state()
2126 	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);  in intel_c10_pll_program()
2165 	drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,  in intel_c10pll_dump_hw_state()
2166 		    hw_state->cmn);  in intel_c10pll_dump_hw_state()
2226 	pll_state->cmn[0]	= 0x0500;  in intel_c20_compute_hdmi_tmds_pll()
2227 	pll_state->cmn[1]	= 0x0005;  in intel_c20_compute_hdmi_tmds_pll()
2228 	pll_state->cmn[2]	= 0x0000;  in intel_c20_compute_hdmi_tmds_pll()
2229 	pll_state->cmn[3]	= 0x0000;  in intel_c20_compute_hdmi_tmds_pll()
2417 	for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {  in intel_c20pll_readout_hw_state()
2419 			pll_state->cmn[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2423 			pll_state->cmn[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2469 		    "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",  in intel_c20pll_dump_hw_state()
2470 		    hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);  in intel_c20pll_dump_hw_state()
2631 	for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {  in intel_c20_pll_program()
2635 					     pll_state->cmn[i]);  in intel_c20_pll_program()
2639 					     pll_state->cmn[i]);  in intel_c20_pll_program()
3362 	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn,  in intel_c10pll_state_verify()
3365 				 mpllb_sw_state->cmn, mpllb_hw_state->cmn);  in intel_c10pll_state_verify()
3391 	if (a->cmn != b->cmn)  in mtl_compare_hw_state_c10()
3406 	if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0)  in mtl_compare_hw_state_c20()
3491 	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) {  in intel_c20pll_state_verify()
3492 		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],  in intel_c20pll_state_verify()
3493 					 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)",  in intel_c20pll_state_verify()
3495 					 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]);  in intel_c20pll_state_verify()