Lines Matching +full:6 +full:gbps
97 * It is required that PSR and DC5/6 are disabled before any CX0 message
442 return 6; in intel_c10_get_tx_term_ctl()
534 .pll[6] = 0x98,
560 .pll[6] = 0x75,
586 .pll[6] = 0xE3,
612 .pll[6] = 0x29,
638 .pll[6] = 0x98,
664 .pll[6] = 0x75,
690 .pll[6] = 0x29,
716 .pll[6] = 0x33,
742 .pll[6] = 0x3D,
882 .clock = 1000000, /* 10 Gbps */
906 .clock = 1350000, /* 13.5 Gbps */
931 .clock = 2000000, /* 20 Gbps */
1108 .clock = 1350000, /* 13.5 Gbps */
1172 .pll[6] = 0,
1198 .pll[6] = 0,
1224 .pll[6] = 0,
1250 .pll[6] = 0,
1276 .pll[6] = 0,
1298 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1308 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1318 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1328 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1338 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1348 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1358 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1368 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1378 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1388 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1398 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1408 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1418 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1428 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1438 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1448 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1458 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1468 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1478 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1488 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1498 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1508 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1518 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1528 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1538 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1548 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1558 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1568 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1578 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1588 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1598 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1608 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1618 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1628 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1638 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1648 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1658 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1668 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1678 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1688 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
2243 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); in intel_c20_compute_hdmi_tmds_pll()
2360 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2366 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2370 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2376 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2495 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2497 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2499 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2501 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2503 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2505 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2507 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2508 return 6; in intel_c20_get_dp_rate()
2509 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2511 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2513 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2515 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2517 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2519 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2533 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2534 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2535 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2537 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2539 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2559 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2560 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2561 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2562 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2563 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2673 /* 5. For DP or 6. For HDMI */ in intel_c20_pll_program()
2676 BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, in intel_c20_pll_program()
2677 BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), in intel_c20_pll_program()
3022 * 6. Program the enabled and disabled owned PHY lane in intel_cx0pll_enable()
3180 * 6. Follow the Display Voltage Frequency Switching Sequence After in intel_mtl_tbt_pll_enable()
3256 * 6. Follow the Display Voltage Frequency Switching Sequence After in intel_cx0pll_disable()
3304 /* 6. Program DDI_CLK_VALFREQ to 0. */ in intel_mtl_tbt_pll_disable()