Lines Matching +full:3 +full:gbps
253 /* 3 tries is assumed to be enough to read successfully */ in __intel_cx0_read()
254 for (i = 0; i < 3; i++) { in __intel_cx0_read()
344 /* 3 tries is assumed to be enough to write successfully */ in __intel_cx0_write()
345 for (i = 0; i < 3; i++) { in __intel_cx0_write()
472 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), in intel_cx0_phy_set_signal_levels()
531 .pll[3] = 0x1,
557 .pll[3] = 0x1,
583 .pll[3] = 0x1,
609 .pll[3] = 0x0,
635 .pll[3] = 0x1,
661 .pll[3] = 0x1,
687 .pll[3] = 0,
713 .pll[3] = 0x1,
739 .pll[3] = 0x1,
882 .clock = 1000000, /* 10 Gbps */
906 .clock = 1350000, /* 13.5 Gbps */
931 .clock = 2000000, /* 20 Gbps */
1108 .clock = 1350000, /* 13.5 Gbps */
1169 .pll[3] = 0,
1195 .pll[3] = 0,
1221 .pll[3] = 0,
1247 .pll[3] = 0,
1273 .pll[3] = 0,
1297 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1307 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1317 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1327 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1337 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1347 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1357 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1367 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1377 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1387 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1397 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1407 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1417 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1427 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1437 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1447 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1457 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1467 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1477 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1487 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1497 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1507 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1517 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1527 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1537 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1547 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1557 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1567 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1577 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1587 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1597 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1607 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1617 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1627 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1637 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1647 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1657 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1667 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1677 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1687 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
2158 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | in intel_c10pll_dump_hw_state()
2173 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); in intel_c10pll_dump_hw_state()
2229 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2238 pll_state->mpllb[3] = (V2I(V2I_2) | in intel_c20_compute_hdmi_tmds_pll()
2469 "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2470 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2495 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2497 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2499 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2501 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2502 return 3; in intel_c20_get_dp_rate()
2503 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2505 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2507 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2509 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2511 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2513 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2515 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2517 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2519 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2533 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2534 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2535 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2537 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2539 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2540 return 3; in intel_c20_get_hdmi_rate()
2559 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2560 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2561 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2562 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2563 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2617 /* 3. Write SRAM configuration context. If A in use, write configuration to B context */ in intel_c20_pll_program()
2711 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | in intel_c10pll_calc_port_clock()
2931 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2933 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
3003 * 3. Change Phy power state to Ready. in intel_cx0pll_enable()
3160 * 3. Follow the Display Voltage Frequency Switching - Sequence in intel_mtl_tbt_pll_enable()
3234 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK> in intel_cx0pll_disable()
3285 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ in intel_mtl_tbt_pll_disable()