Lines Matching +full:0 +full:x23
27 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
30 #define INTEL_CX0_LANE0 BIT(0)
52 return 0; in lane_mask_to_lane()
65 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
132 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); in intel_clear_response_ready_flag()
170 "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
185 "PHY %c Error occurred during %s command. Status: 0x%x\n", in intel_cx0_wait_for_ack()
194 "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", in intel_cx0_wait_for_ack()
201 return 0; in intel_cx0_wait_for_ack()
228 if (ack < 0) in __intel_cx0_read_once()
254 for (i = 0; i < 3; i++) { in __intel_cx0_read()
257 if (status >= 0) in __intel_cx0_read()
265 return 0; in __intel_cx0_read()
312 if (ack < 0) in __intel_cx0_write_once()
332 return 0; in __intel_cx0_write_once()
345 for (i = 0; i < 3; i++) { in __intel_cx0_write()
348 if (status == 0) in __intel_cx0_write()
372 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_write()
373 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); in intel_c20_sram_write()
375 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_H, data >> 8, 0); in intel_c20_sram_write()
376 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write()
387 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_read()
388 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read()
471 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
482 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_cx0_phy_set_signal_levels()
486 u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_phy_set_signal_levels()
491 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0), in intel_cx0_phy_set_signal_levels()
505 /* Write Override enables in 0xD71 */ in intel_cx0_phy_set_signal_levels()
507 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, in intel_cx0_phy_set_signal_levels()
512 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
520 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
521 * programmed 0.
526 .tx = 0x10,
527 .cmn = 0x21,
528 .pll[0] = 0xB4,
529 .pll[1] = 0,
530 .pll[2] = 0x30,
531 .pll[3] = 0x1,
532 .pll[4] = 0x26,
533 .pll[5] = 0x0C,
534 .pll[6] = 0x98,
535 .pll[7] = 0x46,
536 .pll[8] = 0x1,
537 .pll[9] = 0x1,
538 .pll[10] = 0,
539 .pll[11] = 0,
540 .pll[12] = 0xC0,
541 .pll[13] = 0,
542 .pll[14] = 0,
543 .pll[15] = 0x2,
544 .pll[16] = 0x84,
545 .pll[17] = 0x4F,
546 .pll[18] = 0xE5,
547 .pll[19] = 0x23,
552 .tx = 0x10,
553 .cmn = 0x21,
554 .pll[0] = 0x4,
555 .pll[1] = 0,
556 .pll[2] = 0xA2,
557 .pll[3] = 0x1,
558 .pll[4] = 0x33,
559 .pll[5] = 0x10,
560 .pll[6] = 0x75,
561 .pll[7] = 0xB3,
562 .pll[8] = 0x1,
563 .pll[9] = 0x1,
564 .pll[10] = 0,
565 .pll[11] = 0,
566 .pll[12] = 0,
567 .pll[13] = 0,
568 .pll[14] = 0,
569 .pll[15] = 0x2,
570 .pll[16] = 0x85,
571 .pll[17] = 0x0F,
572 .pll[18] = 0xE6,
573 .pll[19] = 0x23,
578 .tx = 0x10,
579 .cmn = 0x21,
580 .pll[0] = 0x34,
581 .pll[1] = 0,
582 .pll[2] = 0xDA,
583 .pll[3] = 0x1,
584 .pll[4] = 0x39,
585 .pll[5] = 0x12,
586 .pll[6] = 0xE3,
587 .pll[7] = 0xE9,
588 .pll[8] = 0x1,
589 .pll[9] = 0x1,
590 .pll[10] = 0,
591 .pll[11] = 0,
592 .pll[12] = 0x20,
593 .pll[13] = 0,
594 .pll[14] = 0,
595 .pll[15] = 0x2,
596 .pll[16] = 0x85,
597 .pll[17] = 0x8F,
598 .pll[18] = 0xE6,
599 .pll[19] = 0x23,
604 .tx = 0x10,
605 .cmn = 0x21,
606 .pll[0] = 0xF4,
607 .pll[1] = 0,
608 .pll[2] = 0xF8,
609 .pll[3] = 0x0,
610 .pll[4] = 0x20,
611 .pll[5] = 0x0A,
612 .pll[6] = 0x29,
613 .pll[7] = 0x10,
614 .pll[8] = 0x1, /* Verify */
615 .pll[9] = 0x1,
616 .pll[10] = 0,
617 .pll[11] = 0,
618 .pll[12] = 0xA0,
619 .pll[13] = 0,
620 .pll[14] = 0,
621 .pll[15] = 0x1,
622 .pll[16] = 0x84,
623 .pll[17] = 0x4F,
624 .pll[18] = 0xE5,
625 .pll[19] = 0x23,
630 .tx = 0x10,
631 .cmn = 0x21,
632 .pll[0] = 0xB4,
633 .pll[1] = 0,
634 .pll[2] = 0x30,
635 .pll[3] = 0x1,
636 .pll[4] = 0x26,
637 .pll[5] = 0x0C,
638 .pll[6] = 0x98,
639 .pll[7] = 0x46,
640 .pll[8] = 0x1,
641 .pll[9] = 0x1,
642 .pll[10] = 0,
643 .pll[11] = 0,
644 .pll[12] = 0xC0,
645 .pll[13] = 0,
646 .pll[14] = 0,
647 .pll[15] = 0x1,
648 .pll[16] = 0x85,
649 .pll[17] = 0x4F,
650 .pll[18] = 0xE6,
651 .pll[19] = 0x23,
656 .tx = 0x10,
657 .cmn = 0x21,
658 .pll[0] = 0x4,
659 .pll[1] = 0,
660 .pll[2] = 0xA2,
661 .pll[3] = 0x1,
662 .pll[4] = 0x33,
663 .pll[5] = 0x10,
664 .pll[6] = 0x75,
665 .pll[7] = 0xB3,
666 .pll[8] = 0x1,
667 .pll[9] = 0x1,
668 .pll[10] = 0,
669 .pll[11] = 0,
670 .pll[12] = 0,
671 .pll[13] = 0,
672 .pll[14] = 0,
673 .pll[15] = 0x1,
674 .pll[16] = 0x85,
675 .pll[17] = 0x0F,
676 .pll[18] = 0xE6,
677 .pll[19] = 0x23,
682 .tx = 0x10,
683 .cmn = 0x21,
684 .pll[0] = 0xF4,
685 .pll[1] = 0,
686 .pll[2] = 0xF8,
687 .pll[3] = 0,
688 .pll[4] = 0x20,
689 .pll[5] = 0x0A,
690 .pll[6] = 0x29,
691 .pll[7] = 0x10,
692 .pll[8] = 0x1,
693 .pll[9] = 0x1,
694 .pll[10] = 0,
695 .pll[11] = 0,
696 .pll[12] = 0xA0,
697 .pll[13] = 0,
698 .pll[14] = 0,
699 .pll[15] = 0,
700 .pll[16] = 0x84,
701 .pll[17] = 0x4F,
702 .pll[18] = 0xE5,
703 .pll[19] = 0x23,
708 .tx = 0x10,
709 .cmn = 0x21,
710 .pll[0] = 0xB4,
711 .pll[1] = 0,
712 .pll[2] = 0x3E,
713 .pll[3] = 0x1,
714 .pll[4] = 0xA8,
715 .pll[5] = 0x0C,
716 .pll[6] = 0x33,
717 .pll[7] = 0x54,
718 .pll[8] = 0x1,
719 .pll[9] = 0x1,
720 .pll[10] = 0,
721 .pll[11] = 0,
722 .pll[12] = 0xC8,
723 .pll[13] = 0,
724 .pll[14] = 0,
725 .pll[15] = 0,
726 .pll[16] = 0x85,
727 .pll[17] = 0x8F,
728 .pll[18] = 0xE6,
729 .pll[19] = 0x23,
734 .tx = 0x10,
735 .cmn = 0x21,
736 .pll[0] = 0x34,
737 .pll[1] = 0,
738 .pll[2] = 0x84,
739 .pll[3] = 0x1,
740 .pll[4] = 0x30,
741 .pll[5] = 0x0F,
742 .pll[6] = 0x3D,
743 .pll[7] = 0x98,
744 .pll[8] = 0x1,
745 .pll[9] = 0x1,
746 .pll[10] = 0,
747 .pll[11] = 0,
748 .pll[12] = 0xF0,
749 .pll[13] = 0,
750 .pll[14] = 0,
751 .pll[15] = 0,
752 .pll[16] = 0x84,
753 .pll[17] = 0x0F,
754 .pll[18] = 0xE5,
755 .pll[19] = 0x23,
782 .tx = { 0xbe88, /* tx cfg0 */
783 0x5800, /* tx cfg1 */
784 0x0000, /* tx cfg2 */
786 .cmn = {0x0500, /* cmn cfg0*/
787 0x0005, /* cmn cfg1 */
788 0x0000, /* cmn cfg2 */
789 0x0000, /* cmn cfg3 */
791 .mpllb = { 0x50a8, /* mpllb cfg0 */
792 0x2120, /* mpllb cfg1 */
793 0xcd9a, /* mpllb cfg2 */
794 0xbfc1, /* mpllb cfg3 */
795 0x5ab8, /* mpllb cfg4 */
796 0x4c34, /* mpllb cfg5 */
797 0x2000, /* mpllb cfg6 */
798 0x0001, /* mpllb cfg7 */
799 0x6000, /* mpllb cfg8 */
800 0x0000, /* mpllb cfg9 */
801 0x0000, /* mpllb cfg10 */
807 .tx = { 0xbe88, /* tx cfg0 */
808 0x4800, /* tx cfg1 */
809 0x0000, /* tx cfg2 */
811 .cmn = {0x0500, /* cmn cfg0*/
812 0x0005, /* cmn cfg1 */
813 0x0000, /* cmn cfg2 */
814 0x0000, /* cmn cfg3 */
816 .mpllb = { 0x308c, /* mpllb cfg0 */
817 0x2110, /* mpllb cfg1 */
818 0xcc9c, /* mpllb cfg2 */
819 0xbfc1, /* mpllb cfg3 */
820 0x4b9a, /* mpllb cfg4 */
821 0x3f81, /* mpllb cfg5 */
822 0x2000, /* mpllb cfg6 */
823 0x0001, /* mpllb cfg7 */
824 0x5000, /* mpllb cfg8 */
825 0x0000, /* mpllb cfg9 */
826 0x0000, /* mpllb cfg10 */
832 .tx = { 0xbe88, /* tx cfg0 */
833 0x4800, /* tx cfg1 */
834 0x0000, /* tx cfg2 */
836 .cmn = {0x0500, /* cmn cfg0*/
837 0x0005, /* cmn cfg1 */
838 0x0000, /* cmn cfg2 */
839 0x0000, /* cmn cfg3 */
841 .mpllb = { 0x108c, /* mpllb cfg0 */
842 0x2108, /* mpllb cfg1 */
843 0xcc9c, /* mpllb cfg2 */
844 0xbfc1, /* mpllb cfg3 */
845 0x4b9a, /* mpllb cfg4 */
846 0x3f81, /* mpllb cfg5 */
847 0x2000, /* mpllb cfg6 */
848 0x0001, /* mpllb cfg7 */
849 0x5000, /* mpllb cfg8 */
850 0x0000, /* mpllb cfg9 */
851 0x0000, /* mpllb cfg10 */
857 .tx = { 0xbe88, /* tx cfg0 */
858 0x4800, /* tx cfg1 */
859 0x0000, /* tx cfg2 */
861 .cmn = {0x0500, /* cmn cfg0*/
862 0x0005, /* cmn cfg1 */
863 0x0000, /* cmn cfg2 */
864 0x0000, /* cmn cfg3 */
866 .mpllb = { 0x10d2, /* mpllb cfg0 */
867 0x2108, /* mpllb cfg1 */
868 0x8d98, /* mpllb cfg2 */
869 0xbfc1, /* mpllb cfg3 */
870 0x7166, /* mpllb cfg4 */
871 0x5f42, /* mpllb cfg5 */
872 0x2000, /* mpllb cfg6 */
873 0x0001, /* mpllb cfg7 */
874 0x7800, /* mpllb cfg8 */
875 0x0000, /* mpllb cfg9 */
876 0x0000, /* mpllb cfg10 */
883 .tx = { 0xbe21, /* tx cfg0 */
884 0xe800, /* tx cfg1 */
885 0x0000, /* tx cfg2 */
887 .cmn = {0x0700, /* cmn cfg0*/
888 0x0005, /* cmn cfg1 */
889 0x0000, /* cmn cfg2 */
890 0x0000, /* cmn cfg3 */
892 .mplla = { 0x3104, /* mplla cfg0 */
893 0xd105, /* mplla cfg1 */
894 0xc025, /* mplla cfg2 */
895 0xc025, /* mplla cfg3 */
896 0x8c00, /* mplla cfg4 */
897 0x759a, /* mplla cfg5 */
898 0x4000, /* mplla cfg6 */
899 0x0003, /* mplla cfg7 */
900 0x3555, /* mplla cfg8 */
901 0x0001, /* mplla cfg9 */
907 .tx = { 0xbea0, /* tx cfg0 */
908 0x4800, /* tx cfg1 */
909 0x0000, /* tx cfg2 */
911 .cmn = {0x0500, /* cmn cfg0*/
912 0x0005, /* cmn cfg1 */
913 0x0000, /* cmn cfg2 */
914 0x0000, /* cmn cfg3 */
916 .mpllb = { 0x015f, /* mpllb cfg0 */
917 0x2205, /* mpllb cfg1 */
918 0x1b17, /* mpllb cfg2 */
919 0xffc1, /* mpllb cfg3 */
920 0xe100, /* mpllb cfg4 */
921 0xbd00, /* mpllb cfg5 */
922 0x2000, /* mpllb cfg6 */
923 0x0001, /* mpllb cfg7 */
924 0x4800, /* mpllb cfg8 */
925 0x0000, /* mpllb cfg9 */
926 0x0000, /* mpllb cfg10 */
932 .tx = { 0xbe20, /* tx cfg0 */
933 0x4800, /* tx cfg1 */
934 0x0000, /* tx cfg2 */
936 .cmn = {0x0500, /* cmn cfg0*/
937 0x0005, /* cmn cfg1 */
938 0x0000, /* cmn cfg2 */
939 0x0000, /* cmn cfg3 */
941 .mplla = { 0x3104, /* mplla cfg0 */
942 0xd105, /* mplla cfg1 */
943 0x9217, /* mplla cfg2 */
944 0x9217, /* mplla cfg3 */
945 0x8c00, /* mplla cfg4 */
946 0x759a, /* mplla cfg5 */
947 0x4000, /* mplla cfg6 */
948 0x0003, /* mplla cfg7 */
949 0x3555, /* mplla cfg8 */
950 0x0001, /* mplla cfg9 */
971 .tx = { 0xbe88,
972 0x4800,
973 0x0000,
975 .cmn = { 0x0500,
976 0x0005,
977 0x0000,
978 0x0000,
980 .mpllb = { 0x50e1,
981 0x2120,
982 0x8e18,
983 0xbfc1,
984 0x9000,
985 0x78f6,
986 0x0000,
987 0x0000,
988 0x0000,
989 0x0000,
990 0x0000,
996 .tx = { 0xbe88,
997 0x4800,
998 0x0000,
1000 .cmn = { 0x0500,
1001 0x0005,
1002 0x0000,
1003 0x0000,
1005 .mpllb = { 0x50fd,
1006 0x2120,
1007 0x8f18,
1008 0xbfc1,
1009 0xa200,
1010 0x8814,
1011 0x2000,
1012 0x0001,
1013 0x1000,
1014 0x0000,
1015 0x0000,
1021 .tx = { 0xbe88,
1022 0x4800,
1023 0x0000,
1025 .cmn = { 0x0500,
1026 0x0005,
1027 0x0000,
1028 0x0000,
1030 .mpllb = { 0x30a8,
1031 0x2110,
1032 0xcd9a,
1033 0xbfc1,
1034 0x6c00,
1035 0x5ab8,
1036 0x2000,
1037 0x0001,
1038 0x6000,
1039 0x0000,
1040 0x0000,
1046 .tx = { 0xbe88,
1047 0x4800,
1048 0x0000,
1050 .cmn = { 0x0500,
1051 0x0005,
1052 0x0000,
1053 0x0000,
1055 .mpllb = { 0x30e1,
1056 0x2110,
1057 0x8e18,
1058 0xbfc1,
1059 0x9000,
1060 0x78f6,
1061 0x0000,
1062 0x0000,
1063 0x0000,
1064 0x0000,
1065 0x0000,
1071 .tx = { 0xbe88,
1072 0x4800,
1073 0x0000,
1075 .cmn = { 0x0500,
1076 0x0005,
1077 0x0000,
1078 0x0000,
1080 .mpllb = { 0x10af,
1081 0x2108,
1082 0xce1a,
1083 0xbfc1,
1084 0x7080,
1085 0x5e80,
1086 0x2000,
1087 0x0001,
1088 0x6400,
1089 0x0000,
1090 0x0000,
1109 .tx = { 0xbea0, /* tx cfg0 */
1110 0x4800, /* tx cfg1 */
1111 0x0000, /* tx cfg2 */
1113 .cmn = {0x0500, /* cmn cfg0*/
1114 0x0005, /* cmn cfg1 */
1115 0x0000, /* cmn cfg2 */
1116 0x0000, /* cmn cfg3 */
1118 .mpllb = { 0x015f, /* mpllb cfg0 */
1119 0x2205, /* mpllb cfg1 */
1120 0x1b17, /* mpllb cfg2 */
1121 0xffc1, /* mpllb cfg3 */
1122 0xbd00, /* mpllb cfg4 */
1123 0x9ec3, /* mpllb cfg5 */
1124 0x2000, /* mpllb cfg6 */
1125 0x0001, /* mpllb cfg7 */
1126 0x4800, /* mpllb cfg8 */
1127 0x0000, /* mpllb cfg9 */
1128 0x0000, /* mpllb cfg10 */
1164 .tx = 0x10,
1165 .cmn = 0x1,
1166 .pll[0] = 0x4,
1167 .pll[1] = 0,
1168 .pll[2] = 0xB2,
1169 .pll[3] = 0,
1170 .pll[4] = 0,
1171 .pll[5] = 0,
1172 .pll[6] = 0,
1173 .pll[7] = 0,
1174 .pll[8] = 0x20,
1175 .pll[9] = 0x1,
1176 .pll[10] = 0,
1177 .pll[11] = 0,
1178 .pll[12] = 0,
1179 .pll[13] = 0,
1180 .pll[14] = 0,
1181 .pll[15] = 0xD,
1182 .pll[16] = 0x6,
1183 .pll[17] = 0x8F,
1184 .pll[18] = 0x84,
1185 .pll[19] = 0x23,
1190 .tx = 0x10,
1191 .cmn = 0x1,
1192 .pll[0] = 0x34,
1193 .pll[1] = 0,
1194 .pll[2] = 0xC0,
1195 .pll[3] = 0,
1196 .pll[4] = 0,
1197 .pll[5] = 0,
1198 .pll[6] = 0,
1199 .pll[7] = 0,
1200 .pll[8] = 0x20,
1201 .pll[9] = 0x1,
1202 .pll[10] = 0,
1203 .pll[11] = 0,
1204 .pll[12] = 0x80,
1205 .pll[13] = 0,
1206 .pll[14] = 0,
1207 .pll[15] = 0xD,
1208 .pll[16] = 0x6,
1209 .pll[17] = 0xCF,
1210 .pll[18] = 0x84,
1211 .pll[19] = 0x23,
1216 .tx = 0x10,
1217 .cmn = 0x1,
1218 .pll[0] = 0xF4,
1219 .pll[1] = 0,
1220 .pll[2] = 0x7A,
1221 .pll[3] = 0,
1222 .pll[4] = 0,
1223 .pll[5] = 0,
1224 .pll[6] = 0,
1225 .pll[7] = 0,
1226 .pll[8] = 0x20,
1227 .pll[9] = 0x1,
1228 .pll[10] = 0,
1229 .pll[11] = 0,
1230 .pll[12] = 0x58,
1231 .pll[13] = 0,
1232 .pll[14] = 0,
1233 .pll[15] = 0xB,
1234 .pll[16] = 0x6,
1235 .pll[17] = 0xF,
1236 .pll[18] = 0x85,
1237 .pll[19] = 0x23,
1242 .tx = 0x10,
1243 .cmn = 0x1,
1244 .pll[0] = 0xF4,
1245 .pll[1] = 0,
1246 .pll[2] = 0x7A,
1247 .pll[3] = 0,
1248 .pll[4] = 0,
1249 .pll[5] = 0,
1250 .pll[6] = 0,
1251 .pll[7] = 0,
1252 .pll[8] = 0x20,
1253 .pll[9] = 0x1,
1254 .pll[10] = 0,
1255 .pll[11] = 0,
1256 .pll[12] = 0x58,
1257 .pll[13] = 0,
1258 .pll[14] = 0,
1259 .pll[15] = 0xA,
1260 .pll[16] = 0x6,
1261 .pll[17] = 0xF,
1262 .pll[18] = 0x85,
1263 .pll[19] = 0x23,
1268 .tx = 0x10,
1269 .cmn = 0x1,
1270 .pll[0] = 0xF4,
1271 .pll[1] = 0,
1272 .pll[2] = 0x7A,
1273 .pll[3] = 0,
1274 .pll[4] = 0,
1275 .pll[5] = 0,
1276 .pll[6] = 0,
1277 .pll[7] = 0,
1278 .pll[8] = 0x20,
1279 .pll[9] = 0x1,
1280 .pll[10] = 0,
1281 .pll[11] = 0,
1282 .pll[12] = 0x58,
1283 .pll[13] = 0,
1284 .pll[14] = 0,
1285 .pll[15] = 0x8,
1286 .pll[16] = 0x6,
1287 .pll[17] = 0xF,
1288 .pll[18] = 0x85,
1289 .pll[19] = 0x23,
1295 .tx = 0x10,
1296 .cmn = 0x1,
1297 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1298 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1299 .pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC,
1300 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1305 .tx = 0x10,
1306 .cmn = 0x1,
1307 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1308 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1309 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1310 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1315 .tx = 0x10,
1316 .cmn = 0x1,
1317 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1318 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1319 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1320 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1325 .tx = 0x10,
1326 .cmn = 0x1,
1327 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1328 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1329 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00,
1330 .pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1335 .tx = 0x10,
1336 .cmn = 0x1,
1337 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1338 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1339 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1340 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1345 .tx = 0x10,
1346 .cmn = 0x1,
1347 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1348 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1349 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55,
1350 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1355 .tx = 0x10,
1356 .cmn = 0x1,
1357 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1358 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1359 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1360 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1365 .tx = 0x10,
1366 .cmn = 0x1,
1367 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1368 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1369 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA,
1370 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1375 .tx = 0x10,
1376 .cmn = 0x1,
1377 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1378 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1379 .pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77,
1380 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1385 .tx = 0x10,
1386 .cmn = 0x1,
1387 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1388 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1389 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55,
1390 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1395 .tx = 0x10,
1396 .cmn = 0x1,
1397 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1398 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1399 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55,
1400 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1405 .tx = 0x10,
1406 .cmn = 0x1,
1407 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1408 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1409 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1410 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1415 .tx = 0x10,
1416 .cmn = 0x1,
1417 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1418 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1419 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1420 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1425 .tx = 0x10,
1426 .cmn = 0x1,
1427 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1428 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1429 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1430 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1435 .tx = 0x10,
1436 .cmn = 0x1,
1437 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1438 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1439 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00,
1440 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1445 .tx = 0x10,
1446 .cmn = 0x1,
1447 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1448 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1449 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00,
1450 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1455 .tx = 0x10,
1456 .cmn = 0x1,
1457 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1458 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1459 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA,
1460 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1465 .tx = 0x10,
1466 .cmn = 0x1,
1467 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1468 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1469 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00,
1470 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1475 .tx = 0x10,
1476 .cmn = 0x1,
1477 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1478 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1479 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00,
1480 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1485 .tx = 0x10,
1486 .cmn = 0x1,
1487 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1488 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1489 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1490 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1495 .tx = 0x10,
1496 .cmn = 0x1,
1497 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1498 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1499 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1500 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1505 .tx = 0x10,
1506 .cmn = 0x1,
1507 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1508 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1509 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1510 .pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1515 .tx = 0x10,
1516 .cmn = 0x1,
1517 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1518 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1519 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA,
1520 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1525 .tx = 0x10,
1526 .cmn = 0x1,
1527 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1528 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1529 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55,
1530 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1535 .tx = 0x10,
1536 .cmn = 0x1,
1537 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1538 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1539 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1540 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1545 .tx = 0x10,
1546 .cmn = 0x1,
1547 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1548 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1549 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55,
1550 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1555 .tx = 0x10,
1556 .cmn = 0x1,
1557 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1558 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1559 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00,
1560 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1565 .tx = 0x10,
1566 .cmn = 0x1,
1567 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1568 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1569 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA,
1570 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1575 .tx = 0x10,
1576 .cmn = 0x1,
1577 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1578 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1579 .pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99,
1580 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1585 .tx = 0x10,
1586 .cmn = 0x1,
1587 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1588 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1589 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1590 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1595 .tx = 0x10,
1596 .cmn = 0x1,
1597 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1598 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1599 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55,
1600 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1605 .tx = 0x10,
1606 .cmn = 0x1,
1607 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1608 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1609 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00,
1610 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1615 .tx = 0x10,
1616 .cmn = 0x1,
1617 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1618 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1619 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA,
1620 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1625 .tx = 0x10,
1626 .cmn = 0x1,
1627 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1628 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1629 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00,
1630 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1635 .tx = 0x10,
1636 .cmn = 0x1,
1637 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1638 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1639 .pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33,
1640 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1645 .tx = 0x10,
1646 .cmn = 0x1,
1647 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1648 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1649 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00,
1650 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1655 .tx = 0x10,
1656 .cmn = 0x1,
1657 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1658 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1659 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA,
1660 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1665 .tx = 0x10,
1666 .cmn = 0x1,
1667 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1668 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1669 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55,
1670 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1675 .tx = 0x10,
1676 .cmn = 0x1,
1677 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1678 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1679 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55,
1680 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1685 .tx = 0x10,
1686 .cmn = 0x1,
1687 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1688 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1689 .pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB,
1690 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1744 .tx = { 0xbe88, /* tx cfg0 */
1745 0x9800, /* tx cfg1 */
1746 0x0000, /* tx cfg2 */
1748 .cmn = { 0x0500, /* cmn cfg0*/
1749 0x0005, /* cmn cfg1 */
1750 0x0000, /* cmn cfg2 */
1751 0x0000, /* cmn cfg3 */
1753 .mpllb = { 0xa0d2, /* mpllb cfg0 */
1754 0x7d80, /* mpllb cfg1 */
1755 0x0906, /* mpllb cfg2 */
1756 0xbe40, /* mpllb cfg3 */
1757 0x0000, /* mpllb cfg4 */
1758 0x0000, /* mpllb cfg5 */
1759 0x0200, /* mpllb cfg6 */
1760 0x0001, /* mpllb cfg7 */
1761 0x0000, /* mpllb cfg8 */
1762 0x0000, /* mpllb cfg9 */
1763 0x0001, /* mpllb cfg10 */
1769 .tx = { 0xbe88, /* tx cfg0 */
1770 0x9800, /* tx cfg1 */
1771 0x0000, /* tx cfg2 */
1773 .cmn = { 0x0500, /* cmn cfg0*/
1774 0x0005, /* cmn cfg1 */
1775 0x0000, /* cmn cfg2 */
1776 0x0000, /* cmn cfg3 */
1778 .mpllb = { 0xa0e0, /* mpllb cfg0 */
1779 0x7d80, /* mpllb cfg1 */
1780 0x0906, /* mpllb cfg2 */
1781 0xbe40, /* mpllb cfg3 */
1782 0x0000, /* mpllb cfg4 */
1783 0x0000, /* mpllb cfg5 */
1784 0x2200, /* mpllb cfg6 */
1785 0x0001, /* mpllb cfg7 */
1786 0x8000, /* mpllb cfg8 */
1787 0x0000, /* mpllb cfg9 */
1788 0x0001, /* mpllb cfg10 */
1794 .tx = { 0xbe88, /* tx cfg0 */
1795 0x9800, /* tx cfg1 */
1796 0x0000, /* tx cfg2 */
1798 .cmn = { 0x0500, /* cmn cfg0*/
1799 0x0005, /* cmn cfg1 */
1800 0x0000, /* cmn cfg2 */
1801 0x0000, /* cmn cfg3 */
1803 .mpllb = { 0x609a, /* mpllb cfg0 */
1804 0x7d40, /* mpllb cfg1 */
1805 0xca06, /* mpllb cfg2 */
1806 0xbe40, /* mpllb cfg3 */
1807 0x0000, /* mpllb cfg4 */
1808 0x0000, /* mpllb cfg5 */
1809 0x2200, /* mpllb cfg6 */
1810 0x0001, /* mpllb cfg7 */
1811 0x5800, /* mpllb cfg8 */
1812 0x0000, /* mpllb cfg9 */
1813 0x0001, /* mpllb cfg10 */
1819 .tx = { 0xbe88, /* tx cfg0 */
1820 0x9800, /* tx cfg1 */
1821 0x0000, /* tx cfg2 */
1823 .cmn = { 0x0500, /* cmn cfg0*/
1824 0x0005, /* cmn cfg1 */
1825 0x0000, /* cmn cfg2 */
1826 0x0000, /* cmn cfg3 */
1828 .mpllb = { 0x409a, /* mpllb cfg0 */
1829 0x7d20, /* mpllb cfg1 */
1830 0xca06, /* mpllb cfg2 */
1831 0xbe40, /* mpllb cfg3 */
1832 0x0000, /* mpllb cfg4 */
1833 0x0000, /* mpllb cfg5 */
1834 0x2200, /* mpllb cfg6 */
1835 0x0001, /* mpllb cfg7 */
1836 0x5800, /* mpllb cfg8 */
1837 0x0000, /* mpllb cfg9 */
1838 0x0001, /* mpllb cfg10 */
1844 .tx = { 0xbe88, /* tx cfg0 */
1845 0x9800, /* tx cfg1 */
1846 0x0000, /* tx cfg2 */
1848 .cmn = { 0x0500, /* cmn cfg0*/
1849 0x0005, /* cmn cfg1 */
1850 0x0000, /* cmn cfg2 */
1851 0x0000, /* cmn cfg3 */
1853 .mpllb = { 0x009a, /* mpllb cfg0 */
1854 0x7d08, /* mpllb cfg1 */
1855 0xca06, /* mpllb cfg2 */
1856 0xbe40, /* mpllb cfg3 */
1857 0x0000, /* mpllb cfg4 */
1858 0x0000, /* mpllb cfg5 */
1859 0x2200, /* mpllb cfg6 */
1860 0x0001, /* mpllb cfg7 */
1861 0x5800, /* mpllb cfg8 */
1862 0x0000, /* mpllb cfg9 */
1863 0x0001, /* mpllb cfg10 */
1869 .tx = { 0xbe98, /* tx cfg0 */
1870 0x8800, /* tx cfg1 */
1871 0x0000, /* tx cfg2 */
1873 .cmn = { 0x0500, /* cmn cfg0*/
1874 0x0005, /* cmn cfg1 */
1875 0x0000, /* cmn cfg2 */
1876 0x0000, /* cmn cfg3 */
1878 .mpllb = { 0x309c, /* mpllb cfg0 */
1879 0x2110, /* mpllb cfg1 */
1880 0xca06, /* mpllb cfg2 */
1881 0xbe40, /* mpllb cfg3 */
1882 0x0000, /* mpllb cfg4 */
1883 0x0000, /* mpllb cfg5 */
1884 0x2200, /* mpllb cfg6 */
1885 0x0001, /* mpllb cfg7 */
1886 0x2000, /* mpllb cfg8 */
1887 0x0000, /* mpllb cfg9 */
1888 0x0004, /* mpllb cfg10 */
1894 .tx = { 0xbe98, /* tx cfg0 */
1895 0x8800, /* tx cfg1 */
1896 0x0000, /* tx cfg2 */
1898 .cmn = { 0x0500, /* cmn cfg0*/
1899 0x0005, /* cmn cfg1 */
1900 0x0000, /* cmn cfg2 */
1901 0x0000, /* cmn cfg3 */
1903 .mpllb = { 0x109c, /* mpllb cfg0 */
1904 0x2108, /* mpllb cfg1 */
1905 0xca06, /* mpllb cfg2 */
1906 0xbe40, /* mpllb cfg3 */
1907 0x0000, /* mpllb cfg4 */
1908 0x0000, /* mpllb cfg5 */
1909 0x2200, /* mpllb cfg6 */
1910 0x0001, /* mpllb cfg7 */
1911 0x2000, /* mpllb cfg8 */
1912 0x0000, /* mpllb cfg9 */
1913 0x0004, /* mpllb cfg10 */
1919 .tx = { 0xbe98, /* tx cfg0 */
1920 0x8800, /* tx cfg1 */
1921 0x0000, /* tx cfg2 */
1923 .cmn = { 0x0500, /* cmn cfg0*/
1924 0x0005, /* cmn cfg1 */
1925 0x0000, /* cmn cfg2 */
1926 0x0000, /* cmn cfg3 */
1928 .mpllb = { 0x10d0, /* mpllb cfg0 */
1929 0x2108, /* mpllb cfg1 */
1930 0x4a06, /* mpllb cfg2 */
1931 0xbe40, /* mpllb cfg3 */
1932 0x0000, /* mpllb cfg4 */
1933 0x0000, /* mpllb cfg5 */
1934 0x2200, /* mpllb cfg6 */
1935 0x0003, /* mpllb cfg7 */
1936 0x2aaa, /* mpllb cfg8 */
1937 0x0002, /* mpllb cfg9 */
1938 0x0004, /* mpllb cfg10 */
1944 .tx = { 0xbe98, /* tx cfg0 */
1945 0x8800, /* tx cfg1 */
1946 0x0000, /* tx cfg2 */
1948 .cmn = { 0x0500, /* cmn cfg0*/
1949 0x0005, /* cmn cfg1 */
1950 0x0000, /* cmn cfg2 */
1951 0x0000, /* cmn cfg3 */
1953 .mpllb = { 0x1104, /* mpllb cfg0 */
1954 0x2108, /* mpllb cfg1 */
1955 0x0a06, /* mpllb cfg2 */
1956 0xbe40, /* mpllb cfg3 */
1957 0x0000, /* mpllb cfg4 */
1958 0x0000, /* mpllb cfg5 */
1959 0x2200, /* mpllb cfg6 */
1960 0x0003, /* mpllb cfg7 */
1961 0x3555, /* mpllb cfg8 */
1962 0x0001, /* mpllb cfg9 */
1963 0x0004, /* mpllb cfg10 */
1969 .tx = { 0xbe98, /* tx cfg0 */
1970 0x8800, /* tx cfg1 */
1971 0x0000, /* tx cfg2 */
1973 .cmn = { 0x0500, /* cmn cfg0*/
1974 0x0005, /* cmn cfg1 */
1975 0x0000, /* cmn cfg2 */
1976 0x0000, /* cmn cfg3 */
1978 .mpllb = { 0x1138, /* mpllb cfg0 */
1979 0x2108, /* mpllb cfg1 */
1980 0x5486, /* mpllb cfg2 */
1981 0xfe40, /* mpllb cfg3 */
1982 0x0000, /* mpllb cfg4 */
1983 0x0000, /* mpllb cfg5 */
1984 0x2200, /* mpllb cfg6 */
1985 0x0001, /* mpllb cfg7 */
1986 0x4000, /* mpllb cfg8 */
1987 0x0000, /* mpllb cfg9 */
1988 0x0004, /* mpllb cfg10 */
2011 for (i = 0; tables[i]; i++) { in intel_c10_phy_check_hdmi_link_rate()
2057 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
2070 for (i = 0; tables[i]; i++) { in intel_c10pll_calc_state()
2076 return 0; in intel_c10pll_calc_state()
2097 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10pll_readout_hw_state()
2100 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
2103 pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
2104 pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
2117 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10_pll_program()
2121 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10_pll_program()
2126 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2127 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2129 /* Custom width needs to be programmed to 0 for both the phy lanes */ in intel_c10_pll_program()
2134 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, in intel_c10_pll_program()
2143 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_dump_hw_state()
2146 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; in intel_c10pll_dump_hw_state()
2165 drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, in intel_c10pll_dump_hw_state()
2169 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) in intel_c10pll_dump_hw_state()
2171 "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", in intel_c10pll_dump_hw_state()
2202 mpll_fracn_quot = (multiplier >> 16) & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
2203 mpll_fracn_rem = multiplier & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
2209 tx_misc = 0x5; in intel_c20_compute_hdmi_tmds_pll()
2211 tx_misc = 0x0; in intel_c20_compute_hdmi_tmds_pll()
2223 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
2224 pll_state->tx[1] = 0x9800 | C20_PHY_TX_MISC(tx_misc); in intel_c20_compute_hdmi_tmds_pll()
2225 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2226 pll_state->cmn[0] = 0x0500; in intel_c20_compute_hdmi_tmds_pll()
2227 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
2228 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2229 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2230 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | in intel_c20_compute_hdmi_tmds_pll()
2241 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2242 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2249 return 0; in intel_c20_compute_hdmi_tmds_pll()
2257 for (i = 0; tables[i]; i++) { in intel_c20_phy_check_hdmi_link_rate()
2314 if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0) in intel_c20pll_calc_state()
2315 return 0; in intel_c20pll_calc_state()
2322 for (i = 0; tables[i]; i++) { in intel_c20pll_calc_state()
2326 return 0; in intel_c20pll_calc_state()
2343 return state->tx[0] & C20_PHY_USE_MPLLB; in intel_c20phy_use_mpllb()
2356 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2364 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2365 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2367 fb_clk_div4_en = 0; in intel_c20pll_calc_port_clock()
2374 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2377 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2383 frac = 0; in intel_c20pll_calc_port_clock()
2405 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20pll_readout_hw_state()
2417 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20pll_readout_hw_state()
2430 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20pll_readout_hw_state()
2442 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20pll_readout_hw_state()
2466 "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2467 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2469 "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2470 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2473 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) in intel_c20pll_dump_hw_state()
2474 drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, in intel_c20pll_dump_hw_state()
2477 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) in intel_c20pll_dump_hw_state()
2478 drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i, in intel_c20pll_dump_hw_state()
2496 return 0; in intel_c20_get_dp_rate()
2511 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2513 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2515 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2523 return 0; in intel_c20_get_dp_rate()
2530 return 0; in intel_c20_get_hdmi_rate()
2543 return 0; in intel_c20_get_hdmi_rate()
2549 /* DP2.0 clock rates */ in is_dp2()
2586 return 0; in intel_get_c20_custom_width()
2604 cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); in intel_c20_pll_program()
2608 * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. in intel_c20_pll_program()
2612 for (i = 0; i < 4; i++) in intel_c20_pll_program()
2613 intel_c20_sram_write(encoder, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); in intel_c20_pll_program()
2619 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20_pll_program()
2631 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20_pll_program()
2644 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20_pll_program()
2655 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20_pll_program()
2682 is_hdmi_frl(clock) ? BIT(7) : 0, in intel_c20_pll_program()
2695 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); in intel_c20_pll_program()
2701 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_calc_port_clock()
2703 int tmpclk = 0; in intel_c10pll_calc_port_clock()
2705 if (pll_state->pll[0] & C10_PLL0_FRACEN) { in intel_c10pll_calc_port_clock()
2730 u32 val = 0; in intel_program_port_clock_ctl()
2734 lane_reversal ? XELPDP_PORT_REVERSAL : 0); in intel_program_port_clock_ctl()
2748 /* DP2.0 10G and 20G rates enable MPLLA*/ in intel_program_port_clock_ctl()
2750 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()
2752 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()
2762 u32 val = 0; in intel_cx0_get_powerdown_update()
2763 int lane = 0; in intel_cx0_get_powerdown_update()
2773 u32 val = 0; in intel_cx0_get_powerdown_state()
2774 int lane = 0; in intel_cx0_get_powerdown_state()
2812 intel_cx0_get_powerdown_update(lane_mask), 0, in intel_cx0_powerdown_change_sequence()
2813 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) in intel_cx0_powerdown_change_sequence()
2831 XELPDP_PLL_LANE_STAGGERING_DELAY(0)); in intel_cx0_setup_powerdown()
2836 u32 val = 0; in intel_cx0_get_pclk_refclk_request()
2837 int lane = 0; in intel_cx0_get_pclk_refclk_request()
2847 u32 val = 0; in intel_cx0_get_pclk_refclk_ack()
2848 int lane = 0; in intel_cx0_get_pclk_refclk_ack()
2865 ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) in intel_cx0_phy_lane_reset()
2866 : XELPDP_LANE_PIPE_RESET(0); in intel_cx0_phy_lane_reset()
2868 ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) | in intel_cx0_phy_lane_reset()
2870 : XELPDP_LANE_PHY_CURRENT_STATUS(0); in intel_cx0_phy_lane_reset()
2875 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2885 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2897 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2906 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0); in intel_cx0_phy_lane_reset()
2926 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2931 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2933 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
2936 disables &= ~REG_GENMASK8(1, 0); in intel_cx0_program_phy_lane()
2937 disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1); in intel_cx0_program_phy_lane()
2940 for (i = 0; i < 4; i++) { in intel_cx0_program_phy_lane()
2949 disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, in intel_cx0_program_phy_lane()
2955 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2962 u32 val = 0; in intel_cx0_get_pclk_pll_request()
2963 int lane = 0; in intel_cx0_get_pclk_pll_request()
2973 u32 val = 0; in intel_cx0_get_pclk_pll_ack()
2974 int lane = 0; in intel_cx0_get_pclk_pll_ack()
3010 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000. in intel_cx0pll_enable()
3051 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_enable()
3134 u32 val = 0; in intel_mtl_tbt_pll_enable()
3174 100, 0, NULL)) in intel_mtl_tbt_pll_enable()
3235 * to "0" to disable PLL. in intel_cx0pll_disable()
3239 intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0); in intel_cx0pll_disable()
3241 /* 4. Program DDI_CLK_VALFREQ to 0. */ in intel_cx0pll_disable()
3242 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); in intel_cx0pll_disable()
3245 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". in intel_cx0pll_disable()
3249 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, in intel_cx0pll_disable()
3250 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_disable()
3262 XELPDP_DDI_CLOCK_SELECT_MASK, 0); in intel_cx0pll_disable()
3264 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_cx0pll_disable()
3280 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. in intel_mtl_tbt_pll_disable()
3283 XELPDP_TBT_CLOCK_REQUEST, 0); in intel_mtl_tbt_pll_disable()
3285 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ in intel_mtl_tbt_pll_disable()
3287 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) in intel_mtl_tbt_pll_disable()
3302 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_mtl_tbt_pll_disable()
3304 /* 6. Program DDI_CLK_VALFREQ to 0. */ in intel_mtl_tbt_pll_disable()
3305 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); in intel_mtl_tbt_pll_disable()
3348 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { in intel_c10pll_state_verify()
3352 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3358 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3363 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3394 if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0) in mtl_compare_hw_state_c10()
3403 if (memcmp(&a->tx, &b->tx, sizeof(a->tx)) != 0) in mtl_compare_hw_state_c20()
3406 if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0) in mtl_compare_hw_state_c20()
3409 if (a->tx[0] & C20_PHY_USE_MPLLB) { in mtl_compare_hw_state_c20()
3410 if (memcmp(&a->mpllb, &b->mpllb, sizeof(a->mpllb)) != 0) in mtl_compare_hw_state_c20()
3413 if (memcmp(&a->mplla, &b->mplla, sizeof(a->mplla)) != 0) in mtl_compare_hw_state_c20()
3469 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { in intel_c20pll_state_verify()
3471 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3476 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { in intel_c20pll_state_verify()
3478 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3484 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { in intel_c20pll_state_verify()
3486 "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()
3491 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { in intel_c20pll_state_verify()
3493 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", in intel_c20pll_state_verify()