Lines Matching full:display
55 * The display engine uses several different clocks to do its work. There
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
66 * to minimize power consumption for a given display configuration.
67 * Typically changes to the CDCLK frequency require all the display pipes
117 void (*get_cdclk)(struct intel_display *display,
119 void (*set_cdclk)(struct intel_display *display,
126 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
129 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
132 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
136 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
141 struct intel_display *display = to_intel_display(state); in intel_cdclk_modeset_calc_cdclk() local
143 return display->funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
146 static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, in intel_cdclk_calc_voltage_level() argument
149 return display->funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
152 static void fixed_133mhz_get_cdclk(struct intel_display *display, in fixed_133mhz_get_cdclk() argument
158 static void fixed_200mhz_get_cdclk(struct intel_display *display, in fixed_200mhz_get_cdclk() argument
164 static void fixed_266mhz_get_cdclk(struct intel_display *display, in fixed_266mhz_get_cdclk() argument
170 static void fixed_333mhz_get_cdclk(struct intel_display *display, in fixed_333mhz_get_cdclk() argument
176 static void fixed_400mhz_get_cdclk(struct intel_display *display, in fixed_400mhz_get_cdclk() argument
182 static void fixed_450mhz_get_cdclk(struct intel_display *display, in fixed_450mhz_get_cdclk() argument
188 static void i85x_get_cdclk(struct intel_display *display, in i85x_get_cdclk() argument
191 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i85x_get_cdclk()
230 static void i915gm_get_cdclk(struct intel_display *display, in i915gm_get_cdclk() argument
233 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i915gm_get_cdclk()
254 static void i945gm_get_cdclk(struct intel_display *display, in i945gm_get_cdclk() argument
257 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i945gm_get_cdclk()
278 static unsigned int intel_hpll_vco(struct intel_display *display) in intel_hpll_vco() argument
317 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_hpll_vco()
336 tmp = intel_de_read(display, in intel_hpll_vco()
341 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
344 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
349 static void g33_get_cdclk(struct intel_display *display, in g33_get_cdclk() argument
352 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in g33_get_cdclk()
361 cdclk_config->vco = intel_hpll_vco(display); in g33_get_cdclk()
392 drm_err(display->drm, in g33_get_cdclk()
398 static void pnv_get_cdclk(struct intel_display *display, in pnv_get_cdclk() argument
401 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in pnv_get_cdclk()
420 drm_err(display->drm, in pnv_get_cdclk()
421 "Unknown pnv display core clock 0x%04x\n", gcfgc); in pnv_get_cdclk()
432 static void i965gm_get_cdclk(struct intel_display *display, in i965gm_get_cdclk() argument
435 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i965gm_get_cdclk()
443 cdclk_config->vco = intel_hpll_vco(display); in i965gm_get_cdclk()
471 drm_err(display->drm, in i965gm_get_cdclk()
477 static void gm45_get_cdclk(struct intel_display *display, in gm45_get_cdclk() argument
480 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in gm45_get_cdclk()
484 cdclk_config->vco = intel_hpll_vco(display); in gm45_get_cdclk()
500 drm_err(display->drm, in gm45_get_cdclk()
508 static void hsw_get_cdclk(struct intel_display *display, in hsw_get_cdclk() argument
511 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_get_cdclk()
512 u32 lcpll = intel_de_read(display, LCPLL_CTL); in hsw_get_cdclk()
517 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
527 static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) in vlv_calc_cdclk() argument
529 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_calc_cdclk()
548 static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) in vlv_calc_voltage_level() argument
550 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_calc_voltage_level()
569 static void vlv_get_cdclk(struct intel_display *display, in vlv_get_cdclk() argument
572 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_get_cdclk()
596 static void vlv_program_pfi_credits(struct intel_display *display) in vlv_program_pfi_credits() argument
598 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_program_pfi_credits()
606 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
620 intel_de_write(display, GCI_CONTROL, in vlv_program_pfi_credits()
623 intel_de_write(display, GCI_CONTROL, in vlv_program_pfi_credits()
630 drm_WARN_ON(display->drm, in vlv_program_pfi_credits()
631 intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
634 static void vlv_set_cdclk(struct intel_display *display, in vlv_set_cdclk() argument
638 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_set_cdclk()
657 * issuing a modeset without actually changing any display after in vlv_set_cdclk()
658 * a system suspend. So grab the display core domain, which covers in vlv_set_cdclk()
675 drm_err(display->drm, in vlv_set_cdclk()
694 drm_err(display->drm, in vlv_set_cdclk()
704 * so that the core display fetch happens in time to avoid underruns. in vlv_set_cdclk()
717 intel_update_cdclk(display); in vlv_set_cdclk()
719 vlv_program_pfi_credits(display); in vlv_set_cdclk()
724 static void chv_set_cdclk(struct intel_display *display, in chv_set_cdclk() argument
728 struct drm_i915_private *dev_priv = to_i915(display->drm); in chv_set_cdclk()
746 * issuing a modeset without actually changing any display after in chv_set_cdclk()
747 * a system suspend. So grab the display core domain, which covers in chv_set_cdclk()
760 drm_err(display->drm, in chv_set_cdclk()
766 intel_update_cdclk(display); in chv_set_cdclk()
768 vlv_program_pfi_credits(display); in chv_set_cdclk()
800 static void bdw_get_cdclk(struct intel_display *display, in bdw_get_cdclk() argument
803 u32 lcpll = intel_de_read(display, LCPLL_CTL); in bdw_get_cdclk()
808 else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
844 static void bdw_set_cdclk(struct intel_display *display, in bdw_set_cdclk() argument
848 struct drm_i915_private *dev_priv = to_i915(display->drm); in bdw_set_cdclk()
852 if (drm_WARN(display->drm, in bdw_set_cdclk()
853 (intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
863 drm_err(display->drm, in bdw_set_cdclk()
868 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
875 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
877 drm_err(display->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
879 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
882 intel_de_rmw(display, LCPLL_CTL, in bdw_set_cdclk()
885 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & in bdw_set_cdclk()
887 drm_err(display->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
892 intel_de_write(display, CDCLK_FREQ, in bdw_set_cdclk()
895 intel_update_cdclk(display); in bdw_set_cdclk()
933 static void skl_dpll0_update(struct intel_display *display, in skl_dpll0_update() argument
941 val = intel_de_read(display, LCPLL1_CTL); in skl_dpll0_update()
945 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
948 val = intel_de_read(display, DPLL_CTRL1); in skl_dpll0_update()
950 if (drm_WARN_ON(display->drm, in skl_dpll0_update()
974 static void skl_get_cdclk(struct intel_display *display, in skl_get_cdclk() argument
979 skl_dpll0_update(display, cdclk_config); in skl_get_cdclk()
986 cdctl = intel_de_read(display, CDCLK_CTL); in skl_get_cdclk()
1041 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) in skl_set_preferred_cdclk_vco() argument
1043 bool changed = display->cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1045 display->cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1048 intel_update_max_cdclk(display); in skl_set_preferred_cdclk_vco()
1051 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) in skl_dpll0_link_rate() argument
1053 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1070 static void skl_dpll0_enable(struct intel_display *display, int vco) in skl_dpll0_enable() argument
1072 intel_de_rmw(display, DPLL_CTRL1, in skl_dpll0_enable()
1077 skl_dpll0_link_rate(display, vco)); in skl_dpll0_enable()
1078 intel_de_posting_read(display, DPLL_CTRL1); in skl_dpll0_enable()
1080 intel_de_rmw(display, LCPLL1_CTL, in skl_dpll0_enable()
1083 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
1084 drm_err(display->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1086 display->cdclk.hw.vco = vco; in skl_dpll0_enable()
1089 skl_set_preferred_cdclk_vco(display, vco); in skl_dpll0_enable()
1092 static void skl_dpll0_disable(struct intel_display *display) in skl_dpll0_disable() argument
1094 intel_de_rmw(display, LCPLL1_CTL, in skl_dpll0_disable()
1097 if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) in skl_dpll0_disable()
1098 drm_err(display->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1100 display->cdclk.hw.vco = 0; in skl_dpll0_disable()
1103 static u32 skl_cdclk_freq_sel(struct intel_display *display, in skl_cdclk_freq_sel() argument
1108 drm_WARN_ON(display->drm, in skl_cdclk_freq_sel()
1109 cdclk != display->cdclk.hw.bypass); in skl_cdclk_freq_sel()
1110 drm_WARN_ON(display->drm, vco != 0); in skl_cdclk_freq_sel()
1126 static void skl_set_cdclk(struct intel_display *display, in skl_set_cdclk() argument
1130 struct drm_i915_private *dev_priv = to_i915(display->drm); in skl_set_cdclk()
1144 drm_WARN_ON_ONCE(display->drm, in skl_set_cdclk()
1152 drm_err(display->drm, in skl_set_cdclk()
1157 freq_select = skl_cdclk_freq_sel(display, cdclk, vco); in skl_set_cdclk()
1159 if (display->cdclk.hw.vco != 0 && in skl_set_cdclk()
1160 display->cdclk.hw.vco != vco) in skl_set_cdclk()
1161 skl_dpll0_disable(display); in skl_set_cdclk()
1163 cdclk_ctl = intel_de_read(display, CDCLK_CTL); in skl_set_cdclk()
1165 if (display->cdclk.hw.vco != vco) { in skl_set_cdclk()
1166 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1169 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1172 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1174 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1175 intel_de_posting_read(display, CDCLK_CTL); in skl_set_cdclk()
1177 if (display->cdclk.hw.vco != vco) in skl_set_cdclk()
1178 skl_dpll0_enable(display, vco); in skl_set_cdclk()
1180 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1182 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1185 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1187 /* Wa Display #1183: skl,kbl,cfl */ in skl_set_cdclk()
1189 intel_de_write(display, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1190 intel_de_posting_read(display, CDCLK_CTL); in skl_set_cdclk()
1196 intel_update_cdclk(display); in skl_set_cdclk()
1199 static void skl_sanitize_cdclk(struct intel_display *display) in skl_sanitize_cdclk() argument
1204 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1208 if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) in skl_sanitize_cdclk()
1211 intel_update_cdclk(display); in skl_sanitize_cdclk()
1212 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1215 if (display->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1216 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
1223 * enable display. Verify the same as well. in skl_sanitize_cdclk()
1225 cdctl = intel_de_read(display, CDCLK_CTL); in skl_sanitize_cdclk()
1227 skl_cdclk_decimal(display->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1233 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1236 display->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1238 display->cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1241 static void skl_cdclk_init_hw(struct intel_display *display) in skl_cdclk_init_hw() argument
1245 skl_sanitize_cdclk(display); in skl_cdclk_init_hw()
1247 if (display->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1248 display->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1253 if (display->cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1254 skl_set_preferred_cdclk_vco(display, in skl_cdclk_init_hw()
1255 display->cdclk.hw.vco); in skl_cdclk_init_hw()
1259 cdclk_config = display->cdclk.hw; in skl_cdclk_init_hw()
1261 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1267 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1270 static void skl_cdclk_uninit_hw(struct intel_display *display) in skl_cdclk_uninit_hw() argument
1272 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in skl_cdclk_uninit_hw()
1278 skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1519 static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) in bxt_calc_cdclk() argument
1521 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk()
1525 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk()
1529 drm_WARN(display->drm, 1, in bxt_calc_cdclk()
1531 min_cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk()
1535 static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1537 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk_pll_vco()
1540 if (cdclk == display->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1544 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1546 return display->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1548 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1549 cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1641 static void icl_readout_refclk(struct intel_display *display, in icl_readout_refclk() argument
1644 u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; in icl_readout_refclk()
1662 static void bxt_de_pll_readout(struct intel_display *display, in bxt_de_pll_readout() argument
1665 struct drm_i915_private *dev_priv = to_i915(display->drm); in bxt_de_pll_readout()
1670 else if (DISPLAY_VER(display) >= 11) in bxt_de_pll_readout()
1671 icl_readout_refclk(display, cdclk_config); in bxt_de_pll_readout()
1675 val = intel_de_read(display, BXT_DE_PLL_ENABLE); in bxt_de_pll_readout()
1690 if (DISPLAY_VER(display) >= 11) in bxt_de_pll_readout()
1693 ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in bxt_de_pll_readout()
1698 static void bxt_get_cdclk(struct intel_display *display, in bxt_get_cdclk() argument
1705 bxt_de_pll_readout(display, cdclk_config); in bxt_get_cdclk()
1707 if (DISPLAY_VER(display) >= 12) in bxt_get_cdclk()
1709 else if (DISPLAY_VER(display) >= 11) in bxt_get_cdclk()
1719 divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1739 if (HAS_CDCLK_SQUASH(display)) in bxt_get_cdclk()
1740 squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); in bxt_get_cdclk()
1756 if (DISPLAY_VER(display) >= 20) in bxt_get_cdclk()
1757 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; in bxt_get_cdclk()
1763 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); in bxt_get_cdclk()
1766 static void bxt_de_pll_disable(struct intel_display *display) in bxt_de_pll_disable() argument
1768 intel_de_write(display, BXT_DE_PLL_ENABLE, 0); in bxt_de_pll_disable()
1771 if (intel_de_wait_for_clear(display, in bxt_de_pll_disable()
1773 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1775 display->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1778 static void bxt_de_pll_enable(struct intel_display *display, int vco) in bxt_de_pll_enable() argument
1780 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in bxt_de_pll_enable()
1782 intel_de_rmw(display, BXT_DE_PLL_CTL, in bxt_de_pll_enable()
1785 intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); in bxt_de_pll_enable()
1788 if (intel_de_wait_for_set(display, in bxt_de_pll_enable()
1790 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1792 display->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1795 static void icl_cdclk_pll_disable(struct intel_display *display) in icl_cdclk_pll_disable() argument
1797 intel_de_rmw(display, BXT_DE_PLL_ENABLE, in icl_cdclk_pll_disable()
1801 if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_disable()
1802 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1804 display->cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1807 static void icl_cdclk_pll_enable(struct intel_display *display, int vco) in icl_cdclk_pll_enable() argument
1809 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in icl_cdclk_pll_enable()
1813 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1816 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1819 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_enable()
1820 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1822 display->cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1825 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) in adlp_cdclk_pll_crawl() argument
1827 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1832 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1836 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1839 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, in adlp_cdclk_pll_crawl()
1841 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1844 intel_de_write(display, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1846 display->cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1849 static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) in bxt_cdclk_cd2x_pipe() argument
1851 if (DISPLAY_VER(display) >= 12) { in bxt_cdclk_cd2x_pipe()
1856 } else if (DISPLAY_VER(display) >= 11) { in bxt_cdclk_cd2x_pipe()
1869 static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, in bxt_cdclk_cd2x_div_sel() argument
1875 drm_WARN_ON(display->drm, in bxt_cdclk_cd2x_div_sel()
1876 cdclk != display->cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1877 drm_WARN_ON(display->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1890 static u16 cdclk_squash_waveform(struct intel_display *display, in cdclk_squash_waveform() argument
1893 const struct intel_cdclk_vals *table = display->cdclk.table; in cdclk_squash_waveform()
1896 if (cdclk == display->cdclk.hw.bypass) in cdclk_squash_waveform()
1900 if (table[i].refclk == display->cdclk.hw.ref && in cdclk_squash_waveform()
1904 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1905 cdclk, display->cdclk.hw.ref); in cdclk_squash_waveform()
1910 static void icl_cdclk_pll_update(struct intel_display *display, int vco) in icl_cdclk_pll_update() argument
1912 if (display->cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1913 display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1914 icl_cdclk_pll_disable(display); in icl_cdclk_pll_update()
1916 if (display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1917 icl_cdclk_pll_enable(display, vco); in icl_cdclk_pll_update()
1920 static void bxt_cdclk_pll_update(struct intel_display *display, int vco) in bxt_cdclk_pll_update() argument
1922 if (display->cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1923 display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1924 bxt_de_pll_disable(display); in bxt_cdclk_pll_update()
1926 if (display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1927 bxt_de_pll_enable(display, vco); in bxt_cdclk_pll_update()
1930 static void dg2_cdclk_squash_program(struct intel_display *display, in dg2_cdclk_squash_program() argument
1939 intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); in dg2_cdclk_squash_program()
1952 static bool mdclk_source_is_cdclk_pll(struct intel_display *display) in mdclk_source_is_cdclk_pll() argument
1954 return DISPLAY_VER(display) >= 20; in mdclk_source_is_cdclk_pll()
1957 static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) in xe2lpd_mdclk_source_sel() argument
1959 if (mdclk_source_is_cdclk_pll(display)) in xe2lpd_mdclk_source_sel()
1965 int intel_mdclk_cdclk_ratio(struct intel_display *display, in intel_mdclk_cdclk_ratio() argument
1968 if (mdclk_source_is_cdclk_pll(display)) in intel_mdclk_cdclk_ratio()
1975 static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, in xe2lpd_mdclk_cdclk_ratio_program() argument
1978 struct drm_i915_private *i915 = to_i915(display->drm); in xe2lpd_mdclk_cdclk_ratio_program()
1981 intel_mdclk_cdclk_ratio(display, cdclk_config), in xe2lpd_mdclk_cdclk_ratio_program()
1985 static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, in cdclk_compute_crawl_and_squash_midpoint() argument
1998 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) in cdclk_compute_crawl_and_squash_midpoint()
2001 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2002 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2019 if (drm_WARN_ON(display->drm, old_div != new_div)) in cdclk_compute_crawl_and_squash_midpoint()
2048 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
2050 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
2051 display->cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
2052 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
2058 static bool pll_enable_wa_needed(struct intel_display *display) in pll_enable_wa_needed() argument
2060 struct drm_i915_private *dev_priv = to_i915(display->drm); in pll_enable_wa_needed()
2062 return (DISPLAY_VERx100(display) == 2000 || in pll_enable_wa_needed()
2063 DISPLAY_VERx100(display) == 1400 || in pll_enable_wa_needed()
2065 display->cdclk.hw.vco > 0; in pll_enable_wa_needed()
2068 static u32 bxt_cdclk_ctl(struct intel_display *display, in bxt_cdclk_ctl() argument
2072 struct drm_i915_private *i915 = to_i915(display->drm); in bxt_cdclk_ctl()
2078 waveform = cdclk_squash_waveform(display, cdclk); in bxt_cdclk_ctl()
2080 val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | in bxt_cdclk_ctl()
2081 bxt_cdclk_cd2x_pipe(display, pipe); in bxt_cdclk_ctl()
2091 if (DISPLAY_VER(display) >= 20) in bxt_cdclk_ctl()
2092 val |= xe2lpd_mdclk_source_sel(display); in bxt_cdclk_ctl()
2099 static void _bxt_set_cdclk(struct intel_display *display, in _bxt_set_cdclk() argument
2106 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2107 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { in _bxt_set_cdclk()
2108 if (display->cdclk.hw.vco != vco) in _bxt_set_cdclk()
2109 adlp_cdclk_pll_crawl(display, vco); in _bxt_set_cdclk()
2110 } else if (DISPLAY_VER(display) >= 11) { in _bxt_set_cdclk()
2112 if (pll_enable_wa_needed(display)) in _bxt_set_cdclk()
2113 dg2_cdclk_squash_program(display, 0); in _bxt_set_cdclk()
2115 icl_cdclk_pll_update(display, vco); in _bxt_set_cdclk()
2117 bxt_cdclk_pll_update(display, vco); in _bxt_set_cdclk()
2120 if (HAS_CDCLK_SQUASH(display)) { in _bxt_set_cdclk()
2121 u16 waveform = cdclk_squash_waveform(display, cdclk); in _bxt_set_cdclk()
2123 dg2_cdclk_squash_program(display, waveform); in _bxt_set_cdclk()
2126 intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); in _bxt_set_cdclk()
2129 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); in _bxt_set_cdclk()
2132 static void bxt_set_cdclk(struct intel_display *display, in bxt_set_cdclk() argument
2136 struct drm_i915_private *dev_priv = to_i915(display->drm); in bxt_set_cdclk()
2143 * Display versions 14 and beyond do not follow the PUnit in bxt_set_cdclk()
2147 if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv)) in bxt_set_cdclk()
2149 else if (DISPLAY_VER(display) >= 11) in bxt_set_cdclk()
2164 drm_err(display->drm, in bxt_set_cdclk()
2170 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) in bxt_set_cdclk()
2171 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); in bxt_set_cdclk()
2173 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, in bxt_set_cdclk()
2175 _bxt_set_cdclk(display, &mid_cdclk_config, pipe); in bxt_set_cdclk()
2176 _bxt_set_cdclk(display, cdclk_config, pipe); in bxt_set_cdclk()
2178 _bxt_set_cdclk(display, cdclk_config, pipe); in bxt_set_cdclk()
2181 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) in bxt_set_cdclk()
2182 xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); in bxt_set_cdclk()
2184 if (DISPLAY_VER(display) >= 14) in bxt_set_cdclk()
2187 * Display versions 14 and beyond in bxt_set_cdclk()
2189 else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv)) in bxt_set_cdclk()
2192 if (DISPLAY_VER(display) < 11) { in bxt_set_cdclk()
2205 drm_err(display->drm, in bxt_set_cdclk()
2211 intel_update_cdclk(display); in bxt_set_cdclk()
2213 if (DISPLAY_VER(display) >= 11) in bxt_set_cdclk()
2218 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2221 static void bxt_sanitize_cdclk(struct intel_display *display) in bxt_sanitize_cdclk() argument
2226 intel_update_cdclk(display); in bxt_sanitize_cdclk()
2227 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2229 if (display->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2230 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2234 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2235 if (cdclk != display->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2239 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_sanitize_cdclk()
2240 if (vco != display->cdclk.hw.vco) in bxt_sanitize_cdclk()
2248 cdctl = intel_de_read(display, CDCLK_CTL); in bxt_sanitize_cdclk()
2249 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2256 cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); in bxt_sanitize_cdclk()
2257 expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); in bxt_sanitize_cdclk()
2264 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2267 display->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2270 display->cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2273 static void bxt_cdclk_init_hw(struct intel_display *display) in bxt_cdclk_init_hw() argument
2277 bxt_sanitize_cdclk(display); in bxt_cdclk_init_hw()
2279 if (display->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2280 display->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2283 cdclk_config = display->cdclk.hw; in bxt_cdclk_init_hw()
2290 cdclk_config.cdclk = bxt_calc_cdclk(display, 0); in bxt_cdclk_init_hw()
2291 cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2293 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2295 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2298 static void bxt_cdclk_uninit_hw(struct intel_display *display) in bxt_cdclk_uninit_hw() argument
2300 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in bxt_cdclk_uninit_hw()
2305 intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2307 bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2312 * @display: display instance
2314 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2316 * during the display core initialization sequence, after which the DMC will
2319 void intel_cdclk_init_hw(struct intel_display *display) in intel_cdclk_init_hw() argument
2321 struct drm_i915_private *i915 = to_i915(display->drm); in intel_cdclk_init_hw()
2323 if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) in intel_cdclk_init_hw()
2324 bxt_cdclk_init_hw(display); in intel_cdclk_init_hw()
2325 else if (DISPLAY_VER(display) == 9) in intel_cdclk_init_hw()
2326 skl_cdclk_init_hw(display); in intel_cdclk_init_hw()
2331 * @display: display instance
2333 * Uninitialize CDCLK. This is done only during the display core
2336 void intel_cdclk_uninit_hw(struct intel_display *display) in intel_cdclk_uninit_hw() argument
2338 struct drm_i915_private *i915 = to_i915(display->drm); in intel_cdclk_uninit_hw()
2340 if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) in intel_cdclk_uninit_hw()
2341 bxt_cdclk_uninit_hw(display); in intel_cdclk_uninit_hw()
2342 else if (DISPLAY_VER(display) == 9) in intel_cdclk_uninit_hw()
2343 skl_cdclk_uninit_hw(display); in intel_cdclk_uninit_hw()
2346 static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, in intel_cdclk_can_crawl_and_squash() argument
2353 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); in intel_cdclk_can_crawl_and_squash()
2358 if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_crawl_and_squash()
2361 old_waveform = cdclk_squash_waveform(display, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2362 new_waveform = cdclk_squash_waveform(display, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2368 static bool intel_cdclk_can_crawl(struct intel_display *display, in intel_cdclk_can_crawl() argument
2374 if (!HAS_CDCLK_CRAWL(display)) in intel_cdclk_can_crawl()
2390 static bool intel_cdclk_can_squash(struct intel_display *display, in intel_cdclk_can_squash() argument
2400 if (!HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_squash()
2429 * @display: display instance
2437 static bool intel_cdclk_can_cd2x_update(struct intel_display *display, in intel_cdclk_can_cd2x_update() argument
2441 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_cdclk_can_cd2x_update()
2444 if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv)) in intel_cdclk_can_cd2x_update()
2453 if (HAS_CDCLK_SQUASH(display)) in intel_cdclk_can_cd2x_update()
2477 void intel_cdclk_dump_config(struct intel_display *display, in intel_cdclk_dump_config() argument
2481 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2487 static void intel_pcode_notify(struct intel_display *display, in intel_pcode_notify() argument
2494 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pcode_notify()
2515 drm_err(display->drm, in intel_pcode_notify()
2516 "Failed to inform PCU about display config (err %d)\n", in intel_pcode_notify()
2520 static void intel_set_cdclk(struct intel_display *display, in intel_set_cdclk() argument
2524 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_set_cdclk()
2527 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) in intel_set_cdclk()
2530 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2533 intel_cdclk_dump_config(display, cdclk_config, context); in intel_set_cdclk()
2535 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_set_cdclk()
2548 mutex_lock(&display->gmbus.mutex); in intel_set_cdclk()
2549 for_each_intel_dp(display->drm, encoder) { in intel_set_cdclk()
2553 &display->gmbus.mutex); in intel_set_cdclk()
2556 intel_cdclk_set_cdclk(display, cdclk_config, pipe); in intel_set_cdclk()
2558 for_each_intel_dp(display->drm, encoder) { in intel_set_cdclk()
2563 mutex_unlock(&display->gmbus.mutex); in intel_set_cdclk()
2565 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_set_cdclk()
2573 if (drm_WARN(display->drm, in intel_set_cdclk()
2574 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), in intel_set_cdclk()
2576 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); in intel_set_cdclk()
2577 intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); in intel_set_cdclk()
2583 struct intel_display *display = to_intel_display(state); in intel_cdclk_pcode_pre_notify() local
2622 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_pre_notify()
2628 struct intel_display *display = to_intel_display(state); in intel_cdclk_pcode_post_notify() local
2659 intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, in intel_cdclk_pcode_post_notify()
2684 struct intel_display *display = to_intel_display(state); in intel_set_cdclk_pre_plane_update() local
2685 struct drm_i915_private *i915 = to_i915(display->drm); in intel_set_cdclk_pre_plane_update()
2722 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2724 intel_set_cdclk(display, &cdclk_config, pipe, in intel_set_cdclk_pre_plane_update()
2738 struct intel_display *display = to_intel_display(state); in intel_set_cdclk_post_plane_update() local
2739 struct drm_i915_private *i915 = to_i915(display->drm); in intel_set_cdclk_post_plane_update()
2759 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2761 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, in intel_set_cdclk_post_plane_update()
2766 static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) in intel_cdclk_ppc() argument
2768 return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; in intel_cdclk_ppc()
2772 static int intel_cdclk_guardband(struct intel_display *display) in intel_cdclk_guardband() argument
2774 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_cdclk_guardband()
2776 if (DISPLAY_VER(display) >= 9 || in intel_cdclk_guardband()
2787 struct intel_display *display = to_intel_display(crtc_state); in intel_pixel_rate_to_cdclk() local
2788 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); in intel_pixel_rate_to_cdclk()
2789 int guardband = intel_cdclk_guardband(display); in intel_pixel_rate_to_cdclk()
2798 struct intel_display *display = to_intel_display(crtc); in intel_planes_min_cdclk() local
2802 for_each_intel_plane_on_crtc(display->drm, crtc, plane) in intel_planes_min_cdclk()
2827 struct intel_display *display = to_intel_display(state); in intel_compute_min_cdclk() local
2828 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_compute_min_cdclk()
2871 for_each_pipe(display, pipe) in intel_compute_min_cdclk()
2886 if (min_cdclk > display->cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2887 drm_dbg_kms(display->drm, in intel_compute_min_cdclk()
2889 min_cdclk, display->cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2911 struct intel_display *display = to_intel_display(state); in bxt_compute_min_voltage_level() local
2939 for_each_pipe(display, pipe) in bxt_compute_min_voltage_level()
2948 struct intel_display *display = to_intel_display(state); in vlv_modeset_calc_cdclk() local
2957 cdclk = vlv_calc_cdclk(display, min_cdclk); in vlv_modeset_calc_cdclk()
2961 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
2964 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2968 vlv_calc_voltage_level(display, cdclk); in vlv_modeset_calc_cdclk()
3007 struct intel_display *display = to_intel_display(state); in skl_dpll0_vco() local
3016 vco = display->cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3078 struct intel_display *display = to_intel_display(state); in bxt_modeset_calc_cdclk() local
3091 cdclk = bxt_calc_cdclk(display, min_cdclk); in bxt_modeset_calc_cdclk()
3092 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3098 intel_cdclk_calc_voltage_level(display, cdclk)); in bxt_modeset_calc_cdclk()
3101 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3102 vco = bxt_calc_cdclk_pll_vco(display, cdclk); in bxt_modeset_calc_cdclk()
3107 intel_cdclk_calc_voltage_level(display, cdclk); in bxt_modeset_calc_cdclk()
3159 struct intel_display *display = to_intel_display(state); in intel_atomic_get_cdclk_state() local
3162 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); in intel_atomic_get_cdclk_state()
3218 int intel_cdclk_init(struct intel_display *display) in intel_cdclk_init() argument
3226 intel_atomic_global_obj_init(display, &display->cdclk.obj, in intel_cdclk_init()
3232 static bool intel_cdclk_need_serialize(struct intel_display *display, in intel_cdclk_need_serialize() argument
3236 struct drm_i915_private *i915 = to_i915(display->drm); in intel_cdclk_need_serialize()
3250 struct intel_display *display = to_intel_display(state); in intel_modeset_calc_cdclk() local
3269 if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { in intel_modeset_calc_cdclk()
3289 intel_cdclk_can_cd2x_update(display, in intel_modeset_calc_cdclk()
3296 crtc = intel_crtc_for_pipe(display, pipe); in intel_modeset_calc_cdclk()
3306 if (intel_cdclk_can_crawl_and_squash(display, in intel_modeset_calc_cdclk()
3309 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3311 } else if (intel_cdclk_can_squash(display, in intel_modeset_calc_cdclk()
3314 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3316 } else if (intel_cdclk_can_crawl(display, in intel_modeset_calc_cdclk()
3319 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3324 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3336 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3340 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != in intel_modeset_calc_cdclk()
3341 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3342 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); in intel_modeset_calc_cdclk()
3349 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3353 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3361 static int intel_compute_max_dotclk(struct intel_display *display) in intel_compute_max_dotclk() argument
3363 int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); in intel_compute_max_dotclk()
3364 int guardband = intel_cdclk_guardband(display); in intel_compute_max_dotclk()
3365 int max_cdclk_freq = display->cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3372 * @display: display instance
3378 void intel_update_max_cdclk(struct intel_display *display) in intel_update_max_cdclk() argument
3380 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_update_max_cdclk()
3382 if (DISPLAY_VER(display) >= 30) { in intel_update_max_cdclk()
3383 display->cdclk.max_cdclk_freq = 691200; in intel_update_max_cdclk()
3385 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3386 display->cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3388 display->cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3389 } else if (DISPLAY_VER(display) >= 11) { in intel_update_max_cdclk()
3390 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3391 display->cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3393 display->cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3395 display->cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3397 display->cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3398 } else if (DISPLAY_VER(display) == 9) { in intel_update_max_cdclk()
3399 u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; in intel_update_max_cdclk()
3402 vco = display->cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3403 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3419 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3427 if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) in intel_update_max_cdclk()
3428 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3430 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3432 display->cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3434 display->cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3436 display->cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3438 display->cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3441 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; in intel_update_max_cdclk()
3444 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); in intel_update_max_cdclk()
3446 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3447 display->cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3449 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3450 display->cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3455 * @display: display instance
3459 void intel_update_cdclk(struct intel_display *display) in intel_update_cdclk() argument
3461 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_update_cdclk()
3463 intel_cdclk_get_cdclk(display, &display->cdclk.hw); in intel_update_cdclk()
3472 intel_de_write(display, GMBUSFREQ_VLV, in intel_update_cdclk()
3473 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3476 static int dg1_rawclk(struct intel_display *display) in dg1_rawclk() argument
3482 intel_de_write(display, PCH_RAWCLK_FREQ, in dg1_rawclk()
3488 static int cnp_rawclk(struct intel_display *display) in cnp_rawclk() argument
3490 struct drm_i915_private *dev_priv = to_i915(display->drm); in cnp_rawclk()
3494 if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { in cnp_rawclk()
3514 intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); in cnp_rawclk()
3518 static int pch_rawclk(struct intel_display *display) in pch_rawclk() argument
3520 return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; in pch_rawclk()
3523 static int vlv_hrawclk(struct intel_display *display) in vlv_hrawclk() argument
3525 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_hrawclk()
3532 static int i9xx_hrawclk(struct intel_display *display) in i9xx_hrawclk() argument
3534 struct drm_i915_private *i915 = to_i915(display->drm); in i9xx_hrawclk()
3542 * @display: display instance
3547 u32 intel_read_rawclk(struct intel_display *display) in intel_read_rawclk() argument
3549 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_read_rawclk()
3560 freq = dg1_rawclk(display); in intel_read_rawclk()
3562 freq = cnp_rawclk(display); in intel_read_rawclk()
3564 freq = pch_rawclk(display); in intel_read_rawclk()
3566 freq = vlv_hrawclk(display); in intel_read_rawclk()
3567 else if (DISPLAY_VER(display) >= 3) in intel_read_rawclk()
3568 freq = i9xx_hrawclk(display); in intel_read_rawclk()
3578 struct intel_display *display = m->private; in i915_cdclk_info_show() local
3580 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); in i915_cdclk_info_show()
3581 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3582 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); in i915_cdclk_info_show()
3589 void intel_cdclk_debugfs_register(struct intel_display *display) in intel_cdclk_debugfs_register() argument
3591 struct drm_minor *minor = display->drm->primary; in intel_cdclk_debugfs_register()
3594 display, &i915_cdclk_info_fops); in intel_cdclk_debugfs_register()
3742 * @display: display instance
3744 void intel_init_cdclk_hooks(struct intel_display *display) in intel_init_cdclk_hooks() argument
3746 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_init_cdclk_hooks()
3748 if (DISPLAY_VER(display) >= 30) { in intel_init_cdclk_hooks()
3749 display->funcs.cdclk = &xe3lpd_cdclk_funcs; in intel_init_cdclk_hooks()
3750 display->cdclk.table = xe3lpd_cdclk_table; in intel_init_cdclk_hooks()
3751 } else if (DISPLAY_VER(display) >= 20) { in intel_init_cdclk_hooks()
3752 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3753 display->cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3754 } else if (DISPLAY_VERx100(display) >= 1401) { in intel_init_cdclk_hooks()
3755 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3756 display->cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3757 } else if (DISPLAY_VER(display) >= 14) { in intel_init_cdclk_hooks()
3758 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3759 display->cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3761 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3762 display->cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3766 display->cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3767 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3769 display->cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3770 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3772 display->cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3773 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3776 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3777 display->cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3778 } else if (DISPLAY_VER(display) >= 12) { in intel_init_cdclk_hooks()
3779 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3780 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3782 display->funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3783 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3784 } else if (DISPLAY_VER(display) >= 11) { in intel_init_cdclk_hooks()
3785 display->funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3786 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3788 display->funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3790 display->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3792 display->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3793 } else if (DISPLAY_VER(display) == 9) { in intel_init_cdclk_hooks()
3794 display->funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3796 display->funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3798 display->funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3800 display->funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3802 display->funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3804 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3806 display->funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3808 display->funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3810 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3812 display->funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3814 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3816 display->funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3818 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3820 display->funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3822 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3824 display->funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3826 display->funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3828 display->funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3830 display->funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3832 display->funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3834 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3837 if (drm_WARN(display->drm, !display->funcs.cdclk, in intel_init_cdclk_hooks()
3839 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()