89  *     cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
91  * , where vco is the frequency generated by the PLL; cd2x_div
103  * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
106  * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
319 	unsigned int vco;  in intel_hpll_vco()  local
339 	vco = vco_table[tmp & 0x7];  in intel_hpll_vco()
340 	if (vco == 0)  in intel_hpll_vco()
341 		drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",  in intel_hpll_vco()
344 		drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);  in intel_hpll_vco()
346 	return vco;  in intel_hpll_vco()
361 	cdclk_config->vco = intel_hpll_vco(display);  in g33_get_cdclk()
370 	switch (cdclk_config->vco) {  in g33_get_cdclk()
387 	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,  in g33_get_cdclk()
393 		"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",  in g33_get_cdclk()
394 		cdclk_config->vco, tmp);  in g33_get_cdclk()
443 	cdclk_config->vco = intel_hpll_vco(display);  in i965gm_get_cdclk()
452 	switch (cdclk_config->vco) {  in i965gm_get_cdclk()
466 	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,  in i965gm_get_cdclk()
472 		"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",  in i965gm_get_cdclk()
473 		cdclk_config->vco, tmp);  in i965gm_get_cdclk()
484 	cdclk_config->vco = intel_hpll_vco(display);  in gm45_get_cdclk()
490 	switch (cdclk_config->vco) {  in gm45_get_cdclk()
501 			"Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",  in gm45_get_cdclk()
502 			cdclk_config->vco, tmp);  in gm45_get_cdclk()
578 	cdclk_config->vco = vlv_get_hpll_vco(dev_priv);  in vlv_get_cdclk()
581 						cdclk_config->vco);  in vlv_get_cdclk()
898 static int skl_calc_cdclk(int min_cdclk, int vco)  in skl_calc_cdclk()  argument
900 	if (vco == 8640000) {  in skl_calc_cdclk()
939 	cdclk_config->vco = 0;  in skl_dpll0_update()
962 		cdclk_config->vco = 8100000;  in skl_dpll0_update()
966 		cdclk_config->vco = 8640000;  in skl_dpll0_update()
983 	if (cdclk_config->vco == 0)  in skl_get_cdclk()
988 	if (cdclk_config->vco == 8640000) {  in skl_get_cdclk()
1041 static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)  in skl_set_preferred_cdclk_vco()  argument
1043 	bool changed = display->cdclk.skl_preferred_vco_freq != vco;  in skl_set_preferred_cdclk_vco()
1045 	display->cdclk.skl_preferred_vco_freq = vco;  in skl_set_preferred_cdclk_vco()
1051 static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)  in skl_dpll0_link_rate()  argument
1053 	drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);  in skl_dpll0_link_rate()
1057 	 * taking into account the VCO required to operate the eDP panel at the  in skl_dpll0_link_rate()
1058 	 * desired frequency. The usual DP link rates operate with a VCO of  in skl_dpll0_link_rate()
1059 	 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.  in skl_dpll0_link_rate()
1062 	 * works with vco.  in skl_dpll0_link_rate()
1064 	if (vco == 8640000)  in skl_dpll0_link_rate()
1070 static void skl_dpll0_enable(struct intel_display *display, int vco)  in skl_dpll0_enable()  argument
1077 		     skl_dpll0_link_rate(display, vco));  in skl_dpll0_enable()
1086 	display->cdclk.hw.vco = vco;  in skl_dpll0_enable()
1088 	/* We'll want to keep using the current vco from now on. */  in skl_dpll0_enable()
1089 	skl_set_preferred_cdclk_vco(display, vco);  in skl_dpll0_enable()
1100 	display->cdclk.hw.vco = 0;  in skl_dpll0_disable()
1104 			      int cdclk, int vco)  in skl_cdclk_freq_sel()  argument
1110 		drm_WARN_ON(display->drm, vco != 0);  in skl_cdclk_freq_sel()
1132 	int vco = cdclk_config->vco;  in skl_set_cdclk()  local
1141 	 * use the corresponding VCO freq as that always leads to using the  in skl_set_cdclk()
1145 			 IS_SKYLAKE(dev_priv) && vco == 8640000);  in skl_set_cdclk()
1157 	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);  in skl_set_cdclk()
1159 	if (display->cdclk.hw.vco != 0 &&  in skl_set_cdclk()
1160 	    display->cdclk.hw.vco != vco)  in skl_set_cdclk()
1165 	if (display->cdclk.hw.vco != vco) {  in skl_set_cdclk()
1177 	if (display->cdclk.hw.vco != vco)  in skl_set_cdclk()
1178 		skl_dpll0_enable(display, vco);  in skl_set_cdclk()
1215 	if (display->cdclk.hw.vco == 0 ||  in skl_sanitize_cdclk()
1238 	display->cdclk.hw.vco = ~0;  in skl_sanitize_cdclk()
1248 	    display->cdclk.hw.vco != 0) {  in skl_cdclk_init_hw()
1250 		 * Use the current vco as our initial  in skl_cdclk_init_hw()
1251 		 * guess as to what the preferred vco is.  in skl_cdclk_init_hw()
1255 						    display->cdclk.hw.vco);  in skl_cdclk_init_hw()
1261 	cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;  in skl_cdclk_init_hw()
1262 	if (cdclk_config.vco == 0)  in skl_cdclk_init_hw()
1263 		cdclk_config.vco = 8100000;  in skl_cdclk_init_hw()
1264 	cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);  in skl_cdclk_init_hw()
1275 	cdclk_config.vco = 0;  in skl_cdclk_uninit_hw()
1512 static int cdclk_divider(int cdclk, int vco, u16 waveform)  in cdclk_divider()  argument
1515 	return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),  in cdclk_divider()
1679 		 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but  in bxt_de_pll_readout()
1682 		cdclk_config->vco = 0;  in bxt_de_pll_readout()
1695 	cdclk_config->vco = ratio * cdclk_config->ref;  in bxt_de_pll_readout()
1714 	if (cdclk_config->vco == 0) {  in bxt_get_cdclk()
1750 							cdclk_config->vco, size * div);  in bxt_get_cdclk()
1752 		cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);  in bxt_get_cdclk()
1775 	display->cdclk.hw.vco = 0;  in bxt_de_pll_disable()
1778 static void bxt_de_pll_enable(struct intel_display *display, int vco)  in bxt_de_pll_enable()  argument
1780 	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);  in bxt_de_pll_enable()
1792 	display->cdclk.hw.vco = vco;  in bxt_de_pll_enable()
1804 	display->cdclk.hw.vco = 0;  in icl_cdclk_pll_disable()
1807 static void icl_cdclk_pll_enable(struct intel_display *display, int vco)  in icl_cdclk_pll_enable()  argument
1809 	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);  in icl_cdclk_pll_enable()
1822 	display->cdclk.hw.vco = vco;  in icl_cdclk_pll_enable()
1825 static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)  in adlp_cdclk_pll_crawl()  argument
1827 	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);  in adlp_cdclk_pll_crawl()
1846 	display->cdclk.hw.vco = vco;  in adlp_cdclk_pll_crawl()
1870 				  int cdclk, int vco, u16 waveform)  in bxt_cdclk_cd2x_div_sel()  argument
1872 	/* cdclk = vco / 2 / div{1,1.5,2,4} */  in bxt_cdclk_cd2x_div_sel()
1873 	switch (cdclk_divider(cdclk, vco, waveform)) {  in bxt_cdclk_cd2x_div_sel()
1877 		drm_WARN_ON(display->drm, vco != 0);  in bxt_cdclk_cd2x_div_sel()
1910 static void icl_cdclk_pll_update(struct intel_display *display, int vco)  in icl_cdclk_pll_update()  argument
1912 	if (display->cdclk.hw.vco != 0 &&  in icl_cdclk_pll_update()
1913 	    display->cdclk.hw.vco != vco)  in icl_cdclk_pll_update()
1916 	if (display->cdclk.hw.vco != vco)  in icl_cdclk_pll_update()
1917 		icl_cdclk_pll_enable(display, vco);  in icl_cdclk_pll_update()
1920 static void bxt_cdclk_pll_update(struct intel_display *display, int vco)  in bxt_cdclk_pll_update()  argument
1922 	if (display->cdclk.hw.vco != 0 &&  in bxt_cdclk_pll_update()
1923 	    display->cdclk.hw.vco != vco)  in bxt_cdclk_pll_update()
1926 	if (display->cdclk.hw.vco != vco)  in bxt_cdclk_pll_update()
1927 		bxt_de_pll_enable(display, vco);  in bxt_cdclk_pll_update()
1942 static bool cdclk_pll_is_unknown(unsigned int vco)  in cdclk_pll_is_unknown()  argument
1946 	 * case when the vco is set to ~0 in the  in cdclk_pll_is_unknown()
1949 	return vco == ~0;  in cdclk_pll_is_unknown()
1969 		return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);  in intel_mdclk_cdclk_ratio()
1994 	if (cdclk_pll_is_unknown(old_cdclk_config->vco))  in cdclk_compute_crawl_and_squash_midpoint()
2005 	if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||  in cdclk_compute_crawl_and_squash_midpoint()
2006 	    old_cdclk_config->vco == new_cdclk_config->vco ||  in cdclk_compute_crawl_and_squash_midpoint()
2011 				old_cdclk_config->vco, old_waveform);  in cdclk_compute_crawl_and_squash_midpoint()
2013 				new_cdclk_config->vco, new_waveform);  in cdclk_compute_crawl_and_squash_midpoint()
2029 	 * The mid cdclk config should have the new vco.  in cdclk_compute_crawl_and_squash_midpoint()
2033 		mid_cdclk_config->vco = old_cdclk_config->vco;  in cdclk_compute_crawl_and_squash_midpoint()
2037 		mid_cdclk_config->vco = new_cdclk_config->vco;  in cdclk_compute_crawl_and_squash_midpoint()
2043 						    mid_cdclk_config->vco,  in cdclk_compute_crawl_and_squash_midpoint()
2065 		display->cdclk.hw.vco > 0;  in pll_enable_wa_needed()
2074 	int vco = cdclk_config->vco;  in bxt_cdclk_ctl()  local
2080 	val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |  in bxt_cdclk_ctl()
2104 	int vco = cdclk_config->vco;  in _bxt_set_cdclk()  local
2106 	if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&  in _bxt_set_cdclk()
2107 	    !cdclk_pll_is_unknown(display->cdclk.hw.vco)) {  in _bxt_set_cdclk()
2108 		if (display->cdclk.hw.vco != vco)  in _bxt_set_cdclk()
2109 			adlp_cdclk_pll_crawl(display, vco);  in _bxt_set_cdclk()
2115 		icl_cdclk_pll_update(display, vco);  in _bxt_set_cdclk()
2117 		bxt_cdclk_pll_update(display, vco);  in _bxt_set_cdclk()
2224 	int cdclk, vco;  in bxt_sanitize_cdclk()  local
2229 	if (display->cdclk.hw.vco == 0 ||  in bxt_sanitize_cdclk()
2238 	/* Make sure the VCO is correct for the cdclk */  in bxt_sanitize_cdclk()
2239 	vco = bxt_calc_cdclk_pll_vco(display, cdclk);  in bxt_sanitize_cdclk()
2240 	if (vco != display->cdclk.hw.vco)  in bxt_sanitize_cdclk()
2270 	display->cdclk.hw.vco = ~0;  in bxt_sanitize_cdclk()
2280 	    display->cdclk.hw.vco != 0)  in bxt_cdclk_init_hw()
2291 	cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk);  in bxt_cdclk_init_hw()
2303 	cdclk_config.vco = 0;  in bxt_cdclk_uninit_hw()
2353 	drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));  in intel_cdclk_can_crawl_and_squash()
2355 	if (a->vco == 0 || b->vco == 0)  in intel_cdclk_can_crawl_and_squash()
2364 	return a->vco != b->vco &&  in intel_cdclk_can_crawl_and_squash()
2378 	 * The vco and cd2x divider will change independently  in intel_cdclk_can_crawl()
2381 	a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);  in intel_cdclk_can_crawl()
2382 	b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);  in intel_cdclk_can_crawl()
2384 	return a->vco != 0 && b->vco != 0 &&  in intel_cdclk_can_crawl()
2385 		a->vco != b->vco &&  in intel_cdclk_can_crawl()
2404 		a->vco != 0 &&  in intel_cdclk_can_squash()
2405 		a->vco == b->vco &&  in intel_cdclk_can_squash()
2422 		a->vco != b->vco ||  in intel_cdclk_clock_changed()
2457 		a->vco != 0 &&  in intel_cdclk_can_cd2x_update()
2458 		a->vco == b->vco &&  in intel_cdclk_can_cd2x_update()
2481 	drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",  in intel_cdclk_dump_config()
2482 		    context, cdclk_config->cdclk, cdclk_config->vco,  in intel_cdclk_dump_config()
3012 	int vco, i;  in skl_dpll0_vco()  local
3014 	vco = cdclk_state->logical.vco;  in skl_dpll0_vco()
3015 	if (!vco)  in skl_dpll0_vco()
3016 		vco = display->cdclk.skl_preferred_vco_freq;  in skl_dpll0_vco()
3026 		 * DPLL0 VCO may need to be adjusted to get the correct  in skl_dpll0_vco()
3032 			vco = 8640000;  in skl_dpll0_vco()
3035 			vco = 8100000;  in skl_dpll0_vco()
3040 	return vco;  in skl_dpll0_vco()
3047 	int min_cdclk, cdclk, vco;  in skl_modeset_calc_cdclk()  local
3053 	vco = skl_dpll0_vco(state);  in skl_modeset_calc_cdclk()
3055 	cdclk = skl_calc_cdclk(min_cdclk, vco);  in skl_modeset_calc_cdclk()
3057 	cdclk_state->logical.vco = vco;  in skl_modeset_calc_cdclk()
3063 		cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);  in skl_modeset_calc_cdclk()
3065 		cdclk_state->actual.vco = vco;  in skl_modeset_calc_cdclk()
3081 	int min_cdclk, min_voltage_level, cdclk, vco;  in bxt_modeset_calc_cdclk()  local
3092 	vco = bxt_calc_cdclk_pll_vco(display, cdclk);  in bxt_modeset_calc_cdclk()
3094 	cdclk_state->logical.vco = vco;  in bxt_modeset_calc_cdclk()
3102 		vco = bxt_calc_cdclk_pll_vco(display, cdclk);  in bxt_modeset_calc_cdclk()
3104 		cdclk_state->actual.vco = vco;  in bxt_modeset_calc_cdclk()
3400 		int max_cdclk, vco;  in intel_update_max_cdclk()  local
3402 		vco = display->cdclk.skl_preferred_vco_freq;  in intel_update_max_cdclk()
3403 		drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);  in intel_update_max_cdclk()
3406 		 * Use the lower (vco 8640) cdclk values as a  in intel_update_max_cdclk()
3408 		 * if the preferred vco is 8100 instead.  in intel_update_max_cdclk()
3419 		display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);  in intel_update_max_cdclk()