Lines Matching +full:- +full:refclk
2 * Copyright © 2006-2017 Intel Corporation
77 * - We have the CDCLK PLL, which generates an output clock based on a
79 * - The CD2X Divider, which divides the output of the PLL based on a
80 * divisor selected from a set of pre-defined choices.
81 * - The CD2X Squasher, which further divides the output based on a
84 * - And, finally, a fixed divider that divides the output frequency by 2.
103 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
104 * - CD2X divider update. Single pipe can be active as the divider update
106 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
107 * - Squash waveform update. Pipes can be active.
108 * - Crawl and squash can also be done back to back. Pipes can be active.
129 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
136 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
143 return display->funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
149 return display->funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
155 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
161 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
167 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
173 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
179 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
185 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
191 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i85x_get_cdclk()
199 if (pdev->revision == 0x1) { in i85x_get_cdclk()
200 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
204 pci_bus_read_config_word(pdev->bus, in i85x_get_cdclk()
214 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
217 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
220 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
225 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
233 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i915gm_get_cdclk()
239 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
245 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
249 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
257 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i945gm_get_cdclk()
263 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
269 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
273 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
317 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_hpll_vco()
341 drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
344 drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
352 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in g33_get_cdclk()
361 cdclk_config->vco = intel_hpll_vco(display); in g33_get_cdclk()
370 switch (cdclk_config->vco) { in g33_get_cdclk()
387 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
392 drm_err(display->drm, in g33_get_cdclk()
394 cdclk_config->vco, tmp); in g33_get_cdclk()
395 cdclk_config->cdclk = 190476; in g33_get_cdclk()
401 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in pnv_get_cdclk()
408 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
411 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
414 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
417 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
420 drm_err(display->drm, in pnv_get_cdclk()
424 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
427 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
435 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in i965gm_get_cdclk()
443 cdclk_config->vco = intel_hpll_vco(display); in i965gm_get_cdclk()
447 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; in i965gm_get_cdclk()
452 switch (cdclk_config->vco) { in i965gm_get_cdclk()
466 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
471 drm_err(display->drm, in i965gm_get_cdclk()
473 cdclk_config->vco, tmp); in i965gm_get_cdclk()
474 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
480 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in gm45_get_cdclk()
484 cdclk_config->vco = intel_hpll_vco(display); in gm45_get_cdclk()
490 switch (cdclk_config->vco) { in gm45_get_cdclk()
494 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
497 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
500 drm_err(display->drm, in gm45_get_cdclk()
502 cdclk_config->vco, tmp); in gm45_get_cdclk()
503 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
511 struct drm_i915_private *dev_priv = to_i915(display->drm); in hsw_get_cdclk()
516 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
518 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
520 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
522 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
524 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
529 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_calc_cdclk()
530 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
550 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_calc_voltage_level()
565 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
572 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_get_cdclk()
578 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
579 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
581 cdclk_config->vco); in vlv_get_cdclk()
589 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
592 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
598 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_program_pfi_credits()
606 if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
617 * WA - write default credits before re-programming in vlv_program_pfi_credits()
630 drm_WARN_ON(display->drm, in vlv_program_pfi_credits()
638 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_set_cdclk()
639 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
640 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
675 drm_err(display->drm, in vlv_set_cdclk()
682 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
683 cdclk) - 1; in vlv_set_cdclk()
694 drm_err(display->drm, in vlv_set_cdclk()
698 /* adjust self-refresh exit latency value */ in vlv_set_cdclk()
728 struct drm_i915_private *dev_priv = to_i915(display->drm); in chv_set_cdclk()
729 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
730 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
760 drm_err(display->drm, in chv_set_cdclk()
807 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
809 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
811 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
813 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
815 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
817 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
823 cdclk_config->voltage_level = in bdw_get_cdclk()
824 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
848 struct drm_i915_private *dev_priv = to_i915(display->drm); in bdw_set_cdclk()
849 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
852 if (drm_WARN(display->drm, in bdw_set_cdclk()
861 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
863 drm_err(display->drm, in bdw_set_cdclk()
877 drm_err(display->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
887 drm_err(display->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
889 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
890 cdclk_config->voltage_level); in bdw_set_cdclk()
893 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
938 cdclk_config->ref = 24000; in skl_dpll0_update()
939 cdclk_config->vco = 0; in skl_dpll0_update()
945 if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
950 if (drm_WARN_ON(display->drm, in skl_dpll0_update()
962 cdclk_config->vco = 8100000; in skl_dpll0_update()
966 cdclk_config->vco = 8640000; in skl_dpll0_update()
981 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
983 if (cdclk_config->vco == 0) in skl_get_cdclk()
988 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
991 cdclk_config->cdclk = 432000; in skl_get_cdclk()
994 cdclk_config->cdclk = 308571; in skl_get_cdclk()
997 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1000 cdclk_config->cdclk = 617143; in skl_get_cdclk()
1009 cdclk_config->cdclk = 450000; in skl_get_cdclk()
1012 cdclk_config->cdclk = 337500; in skl_get_cdclk()
1015 cdclk_config->cdclk = 540000; in skl_get_cdclk()
1018 cdclk_config->cdclk = 675000; in skl_get_cdclk()
1031 cdclk_config->voltage_level = in skl_get_cdclk()
1032 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
1035 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
1038 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
1043 bool changed = display->cdclk.skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
1045 display->cdclk.skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
1053 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1084 drm_err(display->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1086 display->cdclk.hw.vco = vco; in skl_dpll0_enable()
1098 drm_err(display->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1100 display->cdclk.hw.vco = 0; in skl_dpll0_disable()
1108 drm_WARN_ON(display->drm, in skl_cdclk_freq_sel()
1109 cdclk != display->cdclk.hw.bypass); in skl_cdclk_freq_sel()
1110 drm_WARN_ON(display->drm, vco != 0); in skl_cdclk_freq_sel()
1130 struct drm_i915_private *dev_priv = to_i915(display->drm); in skl_set_cdclk()
1131 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1132 int vco = cdclk_config->vco; in skl_set_cdclk()
1144 drm_WARN_ON_ONCE(display->drm, in skl_set_cdclk()
1147 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1152 drm_err(display->drm, in skl_set_cdclk()
1159 if (display->cdclk.hw.vco != 0 && in skl_set_cdclk()
1160 display->cdclk.hw.vco != vco) in skl_set_cdclk()
1165 if (display->cdclk.hw.vco != vco) { in skl_set_cdclk()
1177 if (display->cdclk.hw.vco != vco) in skl_set_cdclk()
1193 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1194 cdclk_config->voltage_level); in skl_set_cdclk()
1204 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1206 * pre-os which can be used by the OS drivers to check the status in skl_sanitize_cdclk()
1212 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1215 if (display->cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1216 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
1222 * decimal part is programmed wrong from BIOS where pre-os does not in skl_sanitize_cdclk()
1227 skl_cdclk_decimal(display->cdclk.hw.cdclk); in skl_sanitize_cdclk()
1233 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1236 display->cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1238 display->cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1247 if (display->cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1248 display->cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1253 if (display->cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1255 display->cdclk.hw.vco); in skl_cdclk_init_hw()
1259 cdclk_config = display->cdclk.hw; in skl_cdclk_init_hw()
1261 cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1272 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in skl_cdclk_uninit_hw()
1283 u16 refclk; member
1289 { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1290 { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1291 { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1292 { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1293 { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1298 { .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1299 { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1300 { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1305 { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1306 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1307 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1308 { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1309 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1310 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1312 { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1313 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1314 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1315 { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1316 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1317 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1319 { .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1320 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1321 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1322 { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1323 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1324 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1329 { .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1330 { .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1331 { .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1332 { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1333 { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1334 { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1336 { .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1337 { .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1338 { .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1339 { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1340 { .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1341 { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1343 { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1344 { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1345 { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1346 { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1347 { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1348 { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1353 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1354 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1355 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1357 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1358 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1359 { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1361 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1362 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1363 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1368 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1369 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1370 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1371 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1372 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1374 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1375 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1376 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1377 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1378 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1380 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1381 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1382 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1383 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1384 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1389 { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1390 { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1391 { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1392 { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1393 { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1394 { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1396 { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1397 { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1398 { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1399 { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1400 { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1401 { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1403 { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1404 { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1405 { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1406 { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1407 { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1408 { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1413 { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1414 { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1415 { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1416 { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1417 { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1418 { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1419 { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1420 { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1421 { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1422 { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1423 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1424 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1425 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1430 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1431 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1432 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1433 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1434 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1435 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1440 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1441 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1442 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1443 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1444 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1445 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1446 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1447 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1448 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1449 { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1450 { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1451 { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1452 { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1453 { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1454 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1455 { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1456 { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1457 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1458 { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1459 { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1460 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1468 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1473 { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1474 { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1475 { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1476 { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1477 { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1478 { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1479 { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1480 { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1481 { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1482 { .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1483 { .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1484 { .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1485 { .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1486 { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1487 { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1488 { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1489 { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1490 { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1491 { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1492 { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1493 { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1494 { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1495 { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1496 { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1497 { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1498 { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1499 { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1500 { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1501 { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1521 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk()
1524 for (i = 0; table[i].refclk; i++) in bxt_calc_cdclk()
1525 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk()
1529 drm_WARN(display->drm, 1, in bxt_calc_cdclk()
1530 "Cannot satisfy minimum cdclk %d with refclk %u\n", in bxt_calc_cdclk()
1531 min_cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk()
1537 const struct intel_cdclk_vals *table = display->cdclk.table; in bxt_calc_cdclk_pll_vco()
1540 if (cdclk == display->cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1543 for (i = 0; table[i].refclk; i++) in bxt_calc_cdclk_pll_vco()
1544 if (table[i].refclk == display->cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1546 return display->cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1548 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1549 cdclk, display->cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1569 return num_voltage_levels - 1; in calc_voltage_level()
1651 cdclk_config->ref = 24000; in icl_readout_refclk()
1654 cdclk_config->ref = 19200; in icl_readout_refclk()
1657 cdclk_config->ref = 38400; in icl_readout_refclk()
1665 struct drm_i915_private *dev_priv = to_i915(display->drm); in bxt_de_pll_readout()
1669 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1673 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1682 cdclk_config->vco = 0; in bxt_de_pll_readout()
1695 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1708 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1710 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1712 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1714 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1715 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1747 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); in bxt_get_cdclk()
1749 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1750 cdclk_config->vco, size * div); in bxt_get_cdclk()
1752 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1757 cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; in bxt_get_cdclk()
1762 cdclk_config->voltage_level = in bxt_get_cdclk()
1763 intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); in bxt_get_cdclk()
1773 drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1775 display->cdclk.hw.vco = 0; in bxt_de_pll_disable()
1780 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in bxt_de_pll_enable()
1790 drm_err(display->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1792 display->cdclk.hw.vco = vco; in bxt_de_pll_enable()
1802 drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1804 display->cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1809 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in icl_cdclk_pll_enable()
1820 drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1822 display->cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1827 int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1841 drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1846 display->cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1875 drm_WARN_ON(display->drm, in bxt_cdclk_cd2x_div_sel()
1876 cdclk != display->cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1877 drm_WARN_ON(display->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1893 const struct intel_cdclk_vals *table = display->cdclk.table; in cdclk_squash_waveform()
1896 if (cdclk == display->cdclk.hw.bypass) in cdclk_squash_waveform()
1899 for (i = 0; table[i].refclk; i++) in cdclk_squash_waveform()
1900 if (table[i].refclk == display->cdclk.hw.ref && in cdclk_squash_waveform()
1904 drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1905 cdclk, display->cdclk.hw.ref); in cdclk_squash_waveform()
1912 if (display->cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1913 display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1916 if (display->cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1922 if (display->cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1923 display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1926 if (display->cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1969 return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); in intel_mdclk_cdclk_ratio()
1978 struct drm_i915_private *i915 = to_i915(display->drm); in xe2lpd_mdclk_cdclk_ratio_program()
1982 cdclk_config->joined_mbus); in xe2lpd_mdclk_cdclk_ratio_program()
1993 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ in cdclk_compute_crawl_and_squash_midpoint()
1994 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) in cdclk_compute_crawl_and_squash_midpoint()
2001 old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2002 new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
2005 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || in cdclk_compute_crawl_and_squash_midpoint()
2006 old_cdclk_config->vco == new_cdclk_config->vco || in cdclk_compute_crawl_and_squash_midpoint()
2010 old_div = cdclk_divider(old_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
2011 old_cdclk_config->vco, old_waveform); in cdclk_compute_crawl_and_squash_midpoint()
2012 new_div = cdclk_divider(new_cdclk_config->cdclk, in cdclk_compute_crawl_and_squash_midpoint()
2013 new_cdclk_config->vco, new_waveform); in cdclk_compute_crawl_and_squash_midpoint()
2019 if (drm_WARN_ON(display->drm, old_div != new_div)) in cdclk_compute_crawl_and_squash_midpoint()
2026 * - If moving to a higher cdclk, the desired action is squashing. in cdclk_compute_crawl_and_squash_midpoint()
2028 * - If moving to a lower cdclk, the desired action is crawling. in cdclk_compute_crawl_and_squash_midpoint()
2033 mid_cdclk_config->vco = old_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
2037 mid_cdclk_config->vco = new_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
2042 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * in cdclk_compute_crawl_and_squash_midpoint()
2043 mid_cdclk_config->vco, in cdclk_compute_crawl_and_squash_midpoint()
2048 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
2049 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); in cdclk_compute_crawl_and_squash_midpoint()
2050 drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
2051 display->cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
2052 drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
2060 struct drm_i915_private *dev_priv = to_i915(display->drm); in pll_enable_wa_needed()
2065 display->cdclk.hw.vco > 0; in pll_enable_wa_needed()
2072 struct drm_i915_private *i915 = to_i915(display->drm); in bxt_cdclk_ctl()
2073 int cdclk = cdclk_config->cdclk; in bxt_cdclk_ctl()
2074 int vco = cdclk_config->vco; in bxt_cdclk_ctl()
2103 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk()
2104 int vco = cdclk_config->vco; in _bxt_set_cdclk()
2106 if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2107 !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { in _bxt_set_cdclk()
2108 if (display->cdclk.hw.vco != vco) in _bxt_set_cdclk()
2136 struct drm_i915_private *dev_priv = to_i915(display->drm); in bxt_set_cdclk()
2138 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
2150 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2159 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
2164 drm_err(display->drm, in bxt_set_cdclk()
2170 if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) in bxt_set_cdclk()
2173 if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, in bxt_set_cdclk()
2181 if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) in bxt_set_cdclk()
2186 * NOOP - No Pcode communication needed for in bxt_set_cdclk()
2190 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2191 cdclk_config->voltage_level); in bxt_set_cdclk()
2199 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
2201 cdclk_config->voltage_level, in bxt_set_cdclk()
2205 drm_err(display->drm, in bxt_set_cdclk()
2218 display->cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2227 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2229 if (display->cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2230 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2234 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2235 if (cdclk != display->cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2240 if (vco != display->cdclk.hw.vco) in bxt_sanitize_cdclk()
2249 expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2264 drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2267 display->cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2270 display->cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2279 if (display->cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2280 display->cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2283 cdclk_config = display->cdclk.hw; in bxt_cdclk_init_hw()
2287 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
2300 struct intel_cdclk_config cdclk_config = display->cdclk.hw; in bxt_cdclk_uninit_hw()
2311 * intel_cdclk_init_hw - Initialize CDCLK hardware
2314 * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2321 struct drm_i915_private *i915 = to_i915(display->drm); in intel_cdclk_init_hw()
2330 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2338 struct drm_i915_private *i915 = to_i915(display->drm); in intel_cdclk_uninit_hw()
2353 drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); in intel_cdclk_can_crawl_and_squash()
2355 if (a->vco == 0 || b->vco == 0) in intel_cdclk_can_crawl_and_squash()
2361 old_waveform = cdclk_squash_waveform(display, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2362 new_waveform = cdclk_squash_waveform(display, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2364 return a->vco != b->vco && in intel_cdclk_can_crawl_and_squash()
2381 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2382 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2384 return a->vco != 0 && b->vco != 0 && in intel_cdclk_can_crawl()
2385 a->vco != b->vco && in intel_cdclk_can_crawl()
2387 a->ref == b->ref; in intel_cdclk_can_crawl()
2403 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2404 a->vco != 0 && in intel_cdclk_can_squash()
2405 a->vco == b->vco && in intel_cdclk_can_squash()
2406 a->ref == b->ref; in intel_cdclk_can_squash()
2410 * intel_cdclk_clock_changed - Check whether the clock changed
2415 * True if CDCLK changed in a way that requires re-programming and
2421 return a->cdclk != b->cdclk || in intel_cdclk_clock_changed()
2422 a->vco != b->vco || in intel_cdclk_clock_changed()
2423 a->ref != b->ref; in intel_cdclk_clock_changed()
2427 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2441 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_cdclk_can_cd2x_update()
2456 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2457 a->vco != 0 && in intel_cdclk_can_cd2x_update()
2458 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
2459 a->ref == b->ref; in intel_cdclk_can_cd2x_update()
2463 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2474 a->voltage_level != b->voltage_level; in intel_cdclk_changed()
2481 drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2482 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2483 cdclk_config->ref, cdclk_config->bypass, in intel_cdclk_dump_config()
2484 cdclk_config->voltage_level); in intel_cdclk_dump_config()
2494 struct drm_i915_private *i915 = to_i915(display->drm); in intel_pcode_notify()
2509 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, in intel_pcode_notify()
2515 drm_err(display->drm, in intel_pcode_notify()
2524 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_set_cdclk()
2527 if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) in intel_set_cdclk()
2530 if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2535 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_set_cdclk()
2548 mutex_lock(&display->gmbus.mutex); in intel_set_cdclk()
2549 for_each_intel_dp(display->drm, encoder) { in intel_set_cdclk()
2552 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, in intel_set_cdclk()
2553 &display->gmbus.mutex); in intel_set_cdclk()
2558 for_each_intel_dp(display->drm, encoder) { in intel_set_cdclk()
2561 mutex_unlock(&intel_dp->aux.hw_mutex); in intel_set_cdclk()
2563 mutex_unlock(&display->gmbus.mutex); in intel_set_cdclk()
2565 for_each_intel_encoder_with_psr(display->drm, encoder) { in intel_set_cdclk()
2573 if (drm_WARN(display->drm, in intel_set_cdclk()
2574 intel_cdclk_changed(&display->cdclk.hw, cdclk_config), in intel_set_cdclk()
2576 intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); in intel_set_cdclk()
2591 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_cdclk_pcode_pre_notify()
2592 &new_cdclk_state->actual) && in intel_cdclk_pcode_pre_notify()
2593 new_cdclk_state->active_pipes == in intel_cdclk_pcode_pre_notify()
2594 old_cdclk_state->active_pipes) in intel_cdclk_pcode_pre_notify()
2600 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2601 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > in intel_cdclk_pcode_pre_notify()
2602 hweight8(old_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2611 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2620 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2637 voltage_level = new_cdclk_state->actual.voltage_level; in intel_cdclk_pcode_post_notify()
2639 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2640 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < in intel_cdclk_pcode_post_notify()
2641 hweight8(old_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2648 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2657 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2670 return new_cdclk_state && !new_cdclk_state->disable_pipes && in intel_cdclk_is_decreasing_later()
2671 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk; in intel_cdclk_is_decreasing_later()
2675 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2685 struct drm_i915_private *i915 = to_i915(display->drm); in intel_set_cdclk_pre_plane_update()
2693 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_pre_plane_update()
2694 &new_cdclk_state->actual)) in intel_set_cdclk_pre_plane_update()
2700 if (new_cdclk_state->disable_pipes) { in intel_set_cdclk_pre_plane_update()
2701 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2704 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2705 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2706 pipe = new_cdclk_state->pipe; in intel_set_cdclk_pre_plane_update()
2708 cdclk_config = old_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2712 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, in intel_set_cdclk_pre_plane_update()
2713 old_cdclk_state->actual.voltage_level); in intel_set_cdclk_pre_plane_update()
2720 cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; in intel_set_cdclk_pre_plane_update()
2722 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2729 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2739 struct drm_i915_private *i915 = to_i915(display->drm); in intel_set_cdclk_post_plane_update()
2746 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_post_plane_update()
2747 &new_cdclk_state->actual)) in intel_set_cdclk_post_plane_update()
2753 if (!new_cdclk_state->disable_pipes && in intel_set_cdclk_post_plane_update()
2754 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) in intel_set_cdclk_post_plane_update()
2755 pipe = new_cdclk_state->pipe; in intel_set_cdclk_post_plane_update()
2759 drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2761 intel_set_cdclk(display, &new_cdclk_state->actual, pipe, in intel_set_cdclk_post_plane_update()
2774 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_cdclk_guardband()
2788 int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); in intel_pixel_rate_to_cdclk()
2790 int pixel_rate = crtc_state->pixel_rate; in intel_pixel_rate_to_cdclk()
2797 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_planes_min_cdclk()
2802 for_each_intel_plane_on_crtc(display->drm, crtc, plane) in intel_planes_min_cdclk()
2803 min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]); in intel_planes_min_cdclk()
2812 if (!crtc_state->hw.enable) in intel_crtc_compute_min_cdclk()
2828 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_compute_min_cdclk()
2844 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()
2847 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()
2849 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2858 if (cdclk_state->bw_min_cdclk != min_cdclk) { in intel_compute_min_cdclk()
2861 cdclk_state->bw_min_cdclk = min_cdclk; in intel_compute_min_cdclk()
2863 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2869 min_cdclk = max(cdclk_state->force_min_cdclk, in intel_compute_min_cdclk()
2870 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()
2872 min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); in intel_compute_min_cdclk()
2882 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && in intel_compute_min_cdclk()
2883 !is_power_of_2(cdclk_state->active_pipes)) in intel_compute_min_cdclk()
2886 if (min_cdclk > display->cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2887 drm_dbg_kms(display->drm, in intel_compute_min_cdclk()
2889 min_cdclk, display->cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2890 return -EINVAL; in intel_compute_min_cdclk()
2923 if (crtc_state->hw.enable) in bxt_compute_min_voltage_level()
2924 min_voltage_level = crtc_state->min_voltage_level; in bxt_compute_min_voltage_level()
2928 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) in bxt_compute_min_voltage_level()
2931 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; in bxt_compute_min_voltage_level()
2933 ret = intel_atomic_lock_global_state(&cdclk_state->base); in bxt_compute_min_voltage_level()
2941 cdclk_state->min_voltage_level[pipe]); in bxt_compute_min_voltage_level()
2959 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2960 cdclk_state->logical.voltage_level = in vlv_modeset_calc_cdclk()
2963 if (!cdclk_state->active_pipes) { in vlv_modeset_calc_cdclk()
2964 cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2966 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2967 cdclk_state->actual.voltage_level = in vlv_modeset_calc_cdclk()
2970 cdclk_state->actual = cdclk_state->logical; in vlv_modeset_calc_cdclk()
2988 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2989 cdclk_state->logical.voltage_level = in bdw_modeset_calc_cdclk()
2992 if (!cdclk_state->active_pipes) { in bdw_modeset_calc_cdclk()
2993 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2995 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2996 cdclk_state->actual.voltage_level = in bdw_modeset_calc_cdclk()
2999 cdclk_state->actual = cdclk_state->logical; in bdw_modeset_calc_cdclk()
3014 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
3016 vco = display->cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3019 if (!crtc_state->hw.enable) in skl_dpll0_vco()
3029 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
3057 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
3058 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
3059 cdclk_state->logical.voltage_level = in skl_modeset_calc_cdclk()
3062 if (!cdclk_state->active_pipes) { in skl_modeset_calc_cdclk()
3063 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
3065 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
3066 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
3067 cdclk_state->actual.voltage_level = in skl_modeset_calc_cdclk()
3070 cdclk_state->actual = cdclk_state->logical; in skl_modeset_calc_cdclk()
3094 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
3095 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3096 cdclk_state->logical.voltage_level = in bxt_modeset_calc_cdclk()
3100 if (!cdclk_state->active_pipes) { in bxt_modeset_calc_cdclk()
3101 cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3104 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
3105 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
3106 cdclk_state->actual.voltage_level = in bxt_modeset_calc_cdclk()
3109 cdclk_state->actual = cdclk_state->logical; in bxt_modeset_calc_cdclk()
3135 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_duplicate_state()
3139 cdclk_state->pipe = INVALID_PIPE; in intel_cdclk_duplicate_state()
3140 cdclk_state->disable_pipes = false; in intel_cdclk_duplicate_state()
3142 return &cdclk_state->base; in intel_cdclk_duplicate_state()
3162 cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); in intel_atomic_get_cdclk_state()
3198 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) in intel_cdclk_atomic_check()
3212 cdclk_state->actual.joined_mbus = joined_mbus; in intel_cdclk_state_set_joined_mbus()
3213 cdclk_state->logical.joined_mbus = joined_mbus; in intel_cdclk_state_set_joined_mbus()
3215 return intel_atomic_lock_global_state(&cdclk_state->base); in intel_cdclk_state_set_joined_mbus()
3224 return -ENOMEM; in intel_cdclk_init()
3226 intel_atomic_global_obj_init(display, &display->cdclk.obj, in intel_cdclk_init()
3227 &cdclk_state->base, &intel_cdclk_funcs); in intel_cdclk_init()
3236 struct drm_i915_private *i915 = to_i915(display->drm); in intel_cdclk_need_serialize()
3237 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != in intel_cdclk_need_serialize()
3238 hweight8(new_cdclk_state->active_pipes); in intel_cdclk_need_serialize()
3239 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, in intel_cdclk_need_serialize()
3240 &new_cdclk_state->actual); in intel_cdclk_need_serialize()
3262 new_cdclk_state->active_pipes = in intel_modeset_calc_cdclk()
3263 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3274 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3277 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || in intel_modeset_calc_cdclk()
3278 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || in intel_modeset_calc_cdclk()
3279 intel_cdclk_changed(&old_cdclk_state->logical, in intel_modeset_calc_cdclk()
3280 &new_cdclk_state->logical)) { in intel_modeset_calc_cdclk()
3281 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3288 if (is_power_of_2(new_cdclk_state->active_pipes) && in intel_modeset_calc_cdclk()
3290 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3291 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3295 pipe = ilog2(new_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3298 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_calc_cdclk()
3307 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3308 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3309 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3312 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3313 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3314 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3317 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3318 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3319 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3322 new_cdclk_state->pipe = pipe; in intel_modeset_calc_cdclk()
3324 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3327 } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3328 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3334 new_cdclk_state->disable_pipes = true; in intel_modeset_calc_cdclk()
3336 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3340 if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != in intel_modeset_calc_cdclk()
3341 intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3342 int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); in intel_modeset_calc_cdclk()
3349 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3351 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3352 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3353 drm_dbg_kms(display->drm, in intel_modeset_calc_cdclk()
3355 new_cdclk_state->logical.voltage_level, in intel_modeset_calc_cdclk()
3356 new_cdclk_state->actual.voltage_level); in intel_modeset_calc_cdclk()
3365 int max_cdclk_freq = display->cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3371 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3380 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_update_max_cdclk()
3383 display->cdclk.max_cdclk_freq = 691200; in intel_update_max_cdclk()
3385 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3386 display->cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3388 display->cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3390 if (display->cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3391 display->cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3393 display->cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3395 display->cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3397 display->cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3402 vco = display->cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3403 drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3419 display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3428 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3430 display->cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3432 display->cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3434 display->cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3436 display->cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3438 display->cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3441 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; in intel_update_max_cdclk()
3444 display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); in intel_update_max_cdclk()
3446 drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3447 display->cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3449 drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3450 display->cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3454 * intel_update_cdclk - Determine the current CDCLK frequency
3461 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_update_cdclk()
3463 intel_cdclk_get_cdclk(display, &display->cdclk.hw); in intel_update_cdclk()
3473 DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3490 struct drm_i915_private *dev_priv = to_i915(display->drm); in cnp_rawclk()
3509 fraction) - 1); in cnp_rawclk()
3525 struct drm_i915_private *dev_priv = to_i915(display->drm); in vlv_hrawclk()
3534 struct drm_i915_private *i915 = to_i915(display->drm); in i9xx_hrawclk()
3541 * intel_read_rawclk - Determine the current RAWCLK frequency
3549 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_read_rawclk()
3578 struct intel_display *display = m->private; in i915_cdclk_info_show()
3580 seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); in i915_cdclk_info_show()
3581 seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3582 seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); in i915_cdclk_info_show()
3591 struct drm_minor *minor = display->drm->primary; in intel_cdclk_debugfs_register()
3593 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, in intel_cdclk_debugfs_register()
3741 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3746 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_init_cdclk_hooks()
3749 display->funcs.cdclk = &xe3lpd_cdclk_funcs; in intel_init_cdclk_hooks()
3750 display->cdclk.table = xe3lpd_cdclk_table; in intel_init_cdclk_hooks()
3752 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3753 display->cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3755 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3756 display->cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3758 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3759 display->cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3761 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3762 display->cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3764 /* Wa_22011320316:adl-p[a0] */ in intel_init_cdclk_hooks()
3766 display->cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3767 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3769 display->cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3770 display->funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3772 display->cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3773 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3776 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3777 display->cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3779 display->funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3780 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3782 display->funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3783 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3785 display->funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3786 display->cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3788 display->funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3790 display->cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3792 display->cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3794 display->funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3796 display->funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3798 display->funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3800 display->funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3802 display->funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3804 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3806 display->funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3808 display->funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3810 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3812 display->funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3814 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3816 display->funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3818 display->funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3820 display->funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3822 display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3824 display->funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3826 display->funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3828 display->funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3830 display->funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3832 display->funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3834 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3837 if (drm_WARN(display->drm, !display->funcs.cdclk, in intel_init_cdclk_hooks()
3839 display->funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()