Lines Matching +full:0 +full:xe2000
11 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
16 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
18 #define _IBX_HDMIW_HDMIEDID_A 0xE2050
19 #define _IBX_HDMIW_HDMIEDID_B 0xE2150
22 #define _IBX_AUD_CNTL_ST_A 0xE20B4
23 #define _IBX_AUD_CNTL_ST_B 0xE21B4
29 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
31 #define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
33 #define _CPT_HDMIW_HDMIEDID_A 0xE5050
34 #define _CPT_HDMIW_HDMIEDID_B 0xE5150
36 #define _CPT_AUD_CNTL_ST_A 0xE50B4
37 #define _CPT_AUD_CNTL_ST_B 0xE51B4
39 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
41 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
42 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
44 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
45 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
47 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
49 #define _IBX_AUD_CONFIG_A 0xe2000
50 #define _IBX_AUD_CONFIG_B 0xe2100
52 #define _CPT_AUD_CONFIG_A 0xe5000
53 #define _CPT_AUD_CONFIG_B 0xe5100
55 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
56 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
65 REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))
67 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 0)
83 #define _HSW_AUD_CONFIG_A 0x65000
84 #define _HSW_AUD_CONFIG_B 0x65100
87 #define _HSW_AUD_MISC_CTRL_A 0x65010
88 #define _HSW_AUD_MISC_CTRL_B 0x65110
91 #define _HSW_AUD_M_CTS_ENABLE_A 0x65028
92 #define _HSW_AUD_M_CTS_ENABLE_B 0x65128
96 #define AUD_CONFIG_M_MASK REG_GENMASK(19, 0)
98 #define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
99 #define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
103 #define _HSW_AUD_DIG_CNVT_1 0x65080
104 #define _HSW_AUD_DIG_CNVT_2 0x65180
106 #define DIP_PORT_SEL_MASK 0x3
108 #define _HSW_AUD_EDID_DATA_A 0x65050
109 #define _HSW_AUD_EDID_DATA_B 0x65150
112 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
113 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
117 #define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
119 #define _AUD_TCA_DP_2DOT0_CTRL 0x650bc
120 #define _AUD_TCB_DP_2DOT0_CTRL 0x651bc
124 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
127 #define AUD_FREQ_CNTRL _MMIO(0x65900)
128 #define AUD_PIN_BUF_CTL _MMIO(0x48414)
131 #define AUD_TS_CDCLK_M _MMIO(0x65ea0)
133 #define AUD_TS_CDCLK_N _MMIO(0x65ea4)
136 #define AUD_CONFIG_BE _MMIO(0x65ef0)
137 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
138 #define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
139 #define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
140 #define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
141 #define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
142 #define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
144 #define HBLANK_START_COUNT_8 0
152 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
153 #define I915_HDMI_LPE_AUDIO_SIZE 0x1000
155 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
156 #define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
158 #define _VLV_AUD_PORT_EN_B_DBG 0x62F20
159 #define _VLV_AUD_PORT_EN_C_DBG 0x62F30
160 #define _VLV_AUD_PORT_EN_D_DBG 0x62F34
167 #define AUD_CHICKENBIT_REG3 _MMIO(0x65F1C)