Lines Matching +full:10 +full:base +full:- +full:te
75 drm_err(display->drm, "DSI header credits not released\n"); in wait_for_header_credits()
87 drm_err(display->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
112 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
119 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
120 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
121 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
122 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
125 drm_err(display->drm, in wait_for_cmds_dispatched_to_panel()
130 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
136 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
140 drm_err(display->drm, "LPTX bit not cleared\n"); in wait_for_cmds_dispatched_to_panel()
147 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_payld()
148 struct intel_display *display = to_intel_display(&intel_dsi->base); in dsi_send_pkt_payld()
149 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_payld()
150 const u8 *data = packet->payload; in dsi_send_pkt_payld()
151 u32 len = packet->payload_length; in dsi_send_pkt_payld()
156 drm_err(display->drm, "payload size exceeds max queue limit\n"); in dsi_send_pkt_payld()
157 return -EINVAL; in dsi_send_pkt_payld()
164 return -EBUSY; in dsi_send_pkt_payld()
166 for (j = 0; j < min_t(u32, len - i, 4); j++) in dsi_send_pkt_payld()
179 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_hdr()
180 struct intel_display *display = to_intel_display(&intel_dsi->base); in dsi_send_pkt_hdr()
181 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_hdr()
185 return -EBUSY; in dsi_send_pkt_hdr()
189 if (packet->payload) in dsi_send_pkt_hdr()
202 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); in dsi_send_pkt_hdr()
203 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); in dsi_send_pkt_hdr()
204 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); in dsi_send_pkt_hdr()
205 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); in dsi_send_pkt_hdr()
217 mode_flags = crtc_state->mode_flags; in icl_dsi_frame_update()
243 for_each_dsi_phy(phy, intel_dsi->phys) { in dsi_program_swing_and_deemphasis()
245 * Program voltage swing and pre-emphasis level values as per in dsi_program_swing_and_deemphasis()
290 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in configure_dual_link_mode()
292 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); in configure_dual_link_mode()
293 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); in configure_dual_link_mode()
302 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); in configure_dual_link_mode()
304 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in configure_dual_link_mode()
306 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
307 u16 hactive = adjusted_mode->crtc_hdisplay; in configure_dual_link_mode()
311 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; in configure_dual_link_mode()
314 drm_err(display->drm, in configure_dual_link_mode()
336 if (crtc_state->dsc.compression_enable) in afe_clk()
337 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in afe_clk()
339 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in afe_clk()
341 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); in afe_clk()
348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_program_esc_clk_div()
361 esc_clk_div_m_phy = (act_word_clk - 1) / 2; in gen11_dsi_program_esc_clk_div()
366 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
372 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
379 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
389 struct intel_display *display = to_intel_display(&intel_dsi->base); in get_dsi_io_power_domains()
390 struct drm_i915_private *dev_priv = to_i915(display->drm); in get_dsi_io_power_domains()
393 for_each_dsi_port(port, intel_dsi->ports) { in get_dsi_io_power_domains()
394 drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]); in get_dsi_io_power_domains()
395 intel_dsi->io_wakeref[port] = in get_dsi_io_power_domains()
409 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_enable_io_power()
418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_power_up_lanes()
422 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_power_up_lanes()
424 intel_dsi->lane_count, false); in gen11_dsi_power_up_lanes()
430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_config_phy_lanes_sequence()
437 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
446 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
479 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
491 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_voltage_swing_program_seq()
496 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
503 /* Program swing and de-emphasis */ in gen11_dsi_voltage_swing_program_seq()
507 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
521 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_ddi_buffer()
527 drm_err(display->drm, "DDI port:%c buffer idle\n", in gen11_dsi_enable_ddi_buffer()
537 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_dphy_timings()
543 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
545 intel_dsi->dphy_reg); in gen11_dsi_setup_dphy_timings()
548 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
550 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_dphy_timings()
560 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
568 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_setup_dphy_timings()
582 /* Program T-INIT master registers */ in gen11_dsi_setup_timings()
583 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
585 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); in gen11_dsi_setup_timings()
588 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
590 intel_dsi->dphy_reg); in gen11_dsi_setup_timings()
593 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
595 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_timings()
600 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timings()
616 mutex_lock(&display->dpll.lock); in gen11_dsi_gate_clocks()
618 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_gate_clocks()
622 mutex_unlock(&display->dpll.lock); in gen11_dsi_gate_clocks()
632 mutex_lock(&display->dpll.lock); in gen11_dsi_ungate_clocks()
634 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_ungate_clocks()
638 mutex_unlock(&display->dpll.lock); in gen11_dsi_ungate_clocks()
651 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_is_clock_enabled()
664 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()
668 mutex_lock(&display->dpll.lock); in gen11_dsi_map_pll()
671 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
673 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); in gen11_dsi_map_pll()
677 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
684 mutex_unlock(&display->dpll.lock); in gen11_dsi_map_pll()
693 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
694 enum pipe pipe = crtc->pipe; in gen11_dsi_configure_transcoder()
699 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
703 if (intel_dsi->eotp_pkt) in gen11_dsi_configure_transcoder()
716 if (intel_dsi->clock_stop) in gen11_dsi_configure_transcoder()
730 if (intel_dsi->bgr_enabled) in gen11_dsi_configure_transcoder()
735 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
738 switch (intel_dsi->pixel_format) { in gen11_dsi_configure_transcoder()
740 MISSING_CASE(intel_dsi->pixel_format); in gen11_dsi_configure_transcoder()
765 switch (intel_dsi->video_mode) { in gen11_dsi_configure_transcoder()
767 MISSING_CASE(intel_dsi->video_mode); in gen11_dsi_configure_transcoder()
780 * in TE GATE mode, TE comes from GPIO in gen11_dsi_configure_transcoder()
794 if (intel_dsi->dual_link) { in gen11_dsi_configure_transcoder()
795 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
806 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
813 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); in gen11_dsi_configure_transcoder()
842 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
846 drm_err(display->drm, "DSI link not ready\n"); in gen11_dsi_configure_transcoder()
857 &crtc_state->hw.adjusted_mode; in gen11_dsi_set_transcoder_timings()
872 * non-compressed link speeds, and simplifies down to the ratio between in gen11_dsi_set_transcoder_timings()
873 * compressed and non-compressed bpp. in gen11_dsi_set_transcoder_timings()
875 if (crtc_state->dsc.compression_enable) { in gen11_dsi_set_transcoder_timings()
876 mul = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in gen11_dsi_set_transcoder_timings()
877 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
880 hactive = adjusted_mode->crtc_hdisplay; in gen11_dsi_set_transcoder_timings()
883 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_set_transcoder_timings()
887 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_set_transcoder_timings()
888 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_set_transcoder_timings()
889 hsync_size = hsync_end - hsync_start; in gen11_dsi_set_transcoder_timings()
890 hback_porch = (adjusted_mode->crtc_htotal - in gen11_dsi_set_transcoder_timings()
891 adjusted_mode->crtc_hsync_end); in gen11_dsi_set_transcoder_timings()
892 vactive = adjusted_mode->crtc_vdisplay; in gen11_dsi_set_transcoder_timings()
895 vtotal = adjusted_mode->crtc_vtotal; in gen11_dsi_set_transcoder_timings()
899 if (crtc_state->dsc.compression_enable) in gen11_dsi_set_transcoder_timings()
900 bpp = fxp_q4_to_int(crtc_state->dsc.compressed_bpp_x16); in gen11_dsi_set_transcoder_timings()
902 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
905 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); in gen11_dsi_set_transcoder_timings()
908 vsync_start = adjusted_mode->crtc_vsync_start; in gen11_dsi_set_transcoder_timings()
909 vsync_end = adjusted_mode->crtc_vsync_end; in gen11_dsi_set_transcoder_timings()
910 vsync_shift = hsync_start - htotal / 2; in gen11_dsi_set_transcoder_timings()
912 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
914 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_set_transcoder_timings()
915 hactive += intel_dsi->pixel_overlap; in gen11_dsi_set_transcoder_timings()
920 if (adjusted_mode->crtc_hdisplay < 256) in gen11_dsi_set_transcoder_timings()
921 drm_err(display->drm, "hactive is less then 256 pixels\n"); in gen11_dsi_set_transcoder_timings()
924 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) in gen11_dsi_set_transcoder_timings()
925 drm_err(display->drm, in gen11_dsi_set_transcoder_timings()
929 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
932 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); in gen11_dsi_set_transcoder_timings()
937 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { in gen11_dsi_set_transcoder_timings()
940 drm_err(display->drm, in gen11_dsi_set_transcoder_timings()
945 drm_err(display->drm, "hback porch < 16 pixels\n"); in gen11_dsi_set_transcoder_timings()
947 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
952 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
956 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); in gen11_dsi_set_transcoder_timings()
961 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
965 * non-interlaced info from VBT is not saved inside in gen11_dsi_set_transcoder_timings()
970 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); in gen11_dsi_set_transcoder_timings()
974 drm_err(display->drm, "Invalid vsync_end value\n"); in gen11_dsi_set_transcoder_timings()
977 drm_err(display->drm, "vsync_start less than vactive\n"); in gen11_dsi_set_transcoder_timings()
981 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
985 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); in gen11_dsi_set_transcoder_timings()
996 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1011 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
1015 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); in gen11_dsi_set_transcoder_timings()
1027 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_transcoder()
1034 TRANSCONF_STATE_ENABLE, 10)) in gen11_dsi_enable_transcoder()
1035 drm_err(display->drm, in gen11_dsi_enable_transcoder()
1052 * UI (nsec) = (10^6)/Bitrate in gen11_dsi_setup_timeouts()
1053 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate in gen11_dsi_setup_timeouts()
1058 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, in gen11_dsi_setup_timeouts()
1060 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); in gen11_dsi_setup_timeouts()
1061 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); in gen11_dsi_setup_timeouts()
1063 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timeouts()
1095 * used as TE i/p for DSI0, in gen11_dsi_config_util_pin()
1096 * for dual link/DSI1 TE is from slave DSI1 in gen11_dsi_config_util_pin()
1099 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1120 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ in gen11_dsi_enable_port_and_phy()
1126 /* setup D-PHY timings */ in gen11_dsi_enable_port_and_phy()
1157 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_powerup_panel()
1168 dsi = intel_dsi->dsi_hosts[port]->device; in gen11_dsi_powerup_panel()
1171 drm_err(display->drm, in gen11_dsi_powerup_panel()
1191 msleep(intel_dsi->panel_on_delay); in gen11_dsi_pre_pll_enable()
1240 * Wa_16012360555:adl-p
1252 for_each_dsi_port(port, intel_dsi->ports) in adlp_set_lp_hs_wakeup_gb()
1265 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_enable()
1268 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); in gen11_dsi_enable()
1270 /* Wa_16012360555:adl-p */ in gen11_dsi_enable()
1292 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_transcoder()
1302 drm_err(display->drm, in gen11_dsi_disable_transcoder()
1327 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_deconfigure_trancoder()
1333 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1342 10)) in gen11_dsi_deconfigure_trancoder()
1343 drm_err(display->drm, "DSI link not in ULPS\n"); in gen11_dsi_deconfigure_trancoder()
1347 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1355 if (intel_dsi->dual_link) { in gen11_dsi_deconfigure_trancoder()
1356 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1372 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_port()
1378 drm_err(display->drm, in gen11_dsi_disable_port()
1388 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_io_power()
1392 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_io_power()
1395 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); in gen11_dsi_disable_io_power()
1404 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_disable_io_power()
1427 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in gen11_dsi_post_disable()
1435 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); in gen11_dsi_post_disable()
1456 msleep(intel_dsi->panel_off_delay); in gen11_dsi_post_disable()
1459 intel_dsi->panel_power_off_time = ktime_get_boottime(); in gen11_dsi_post_disable()
1465 struct drm_i915_private *i915 = to_i915(connector->dev); in gen11_dsi_mode_valid()
1481 &pipe_config->hw.adjusted_mode; in gen11_dsi_get_timings()
1483 if (pipe_config->dsc.compressed_bpp_x16) { in gen11_dsi_get_timings()
1484 int div = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); in gen11_dsi_get_timings()
1485 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_get_timings()
1487 adjusted_mode->crtc_htotal = in gen11_dsi_get_timings()
1488 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_get_timings()
1489 adjusted_mode->crtc_hsync_start = in gen11_dsi_get_timings()
1490 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_get_timings()
1491 adjusted_mode->crtc_hsync_end = in gen11_dsi_get_timings()
1492 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_get_timings()
1495 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1496 adjusted_mode->crtc_hdisplay *= 2; in gen11_dsi_get_timings()
1497 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_get_timings()
1498 adjusted_mode->crtc_hdisplay -= in gen11_dsi_get_timings()
1499 intel_dsi->pixel_overlap; in gen11_dsi_get_timings()
1500 adjusted_mode->crtc_htotal *= 2; in gen11_dsi_get_timings()
1502 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in gen11_dsi_get_timings()
1503 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in gen11_dsi_get_timings()
1505 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { in gen11_dsi_get_timings()
1506 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1507 adjusted_mode->crtc_hsync_start *= 2; in gen11_dsi_get_timings()
1508 adjusted_mode->crtc_hsync_end *= 2; in gen11_dsi_get_timings()
1511 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in gen11_dsi_get_timings()
1512 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in gen11_dsi_get_timings()
1517 struct intel_display *display = to_intel_display(&intel_dsi->base); in gen11_dsi_is_periodic_cmd_mode()
1521 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1533 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1534 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | in gen11_dsi_get_cmd_mode_config()
1536 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1537 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; in gen11_dsi_get_cmd_mode_config()
1539 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; in gen11_dsi_get_cmd_mode_config()
1545 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_get_config()
1550 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; in gen11_dsi_get_config()
1551 if (intel_dsi->dual_link) in gen11_dsi_get_config()
1552 pipe_config->hw.adjusted_mode.crtc_clock *= 2; in gen11_dsi_get_config()
1555 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in gen11_dsi_get_config()
1556 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1558 /* Get the details on which TE should be enabled */ in gen11_dsi_get_config()
1563 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; in gen11_dsi_get_config()
1576 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_sync_state()
1577 pipe = intel_crtc->pipe; in gen11_dsi_sync_state()
1582 drm_dbg_kms(display->drm, in gen11_dsi_sync_state()
1584 encoder->base.base.id, in gen11_dsi_sync_state()
1585 encoder->base.name); in gen11_dsi_sync_state()
1592 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config()
1593 int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10; in gen11_dsi_dsc_compute_config()
1601 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1602 return -EINVAL; in gen11_dsi_dsc_compute_config()
1605 if (crtc_state->dsc.slice_count > 1) in gen11_dsi_dsc_compute_config()
1606 crtc_state->dsc.num_streams = 2; in gen11_dsi_dsc_compute_config()
1608 crtc_state->dsc.num_streams = 1; in gen11_dsi_dsc_compute_config()
1611 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()
1613 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()
1620 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()
1621 drm_WARN_ON(display->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()
1622 drm_WARN_ON(display->drm, in gen11_dsi_dsc_compute_config()
1623 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
1624 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()
1625 drm_WARN_ON(display->drm, in gen11_dsi_dsc_compute_config()
1626 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()
1632 crtc_state->dsc.compression_enable = true; in gen11_dsi_dsc_compute_config()
1643 struct intel_connector *intel_connector = intel_dsi->attached_connector; in gen11_dsi_compute_config()
1645 &pipe_config->hw.adjusted_mode; in gen11_dsi_compute_config()
1648 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1649 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1659 adjusted_mode->flags = 0; in gen11_dsi_compute_config()
1662 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
1663 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; in gen11_dsi_compute_config()
1665 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; in gen11_dsi_compute_config()
1667 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in gen11_dsi_compute_config()
1668 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1670 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
1672 pipe_config->clock_set = true; in gen11_dsi_compute_config()
1675 drm_dbg_kms(display->drm, "Attempting to use DSC failed\n"); in gen11_dsi_compute_config()
1677 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; in gen11_dsi_compute_config()
1680 * In case of TE GATE cmd mode, we in gen11_dsi_compute_config()
1681 * receive TE from the slave if in gen11_dsi_compute_config()
1700 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_get_hw_state()
1709 encoder->power_domain); in gen11_dsi_get_hw_state()
1713 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_get_hw_state()
1731 drm_err(display->drm, "Invalid PIPE input\n"); in gen11_dsi_get_hw_state()
1739 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in gen11_dsi_get_hw_state()
1746 if (crtc_state->dsc.compression_enable) { in gen11_dsi_initial_fastset_check()
1747 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); in gen11_dsi_initial_fastset_check()
1748 crtc_state->uapi.mode_changed = true; in gen11_dsi_initial_fastset_check()
1807 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in gen11_dsi_host_transfer()
1811 if (mipi_dsi_packet_format_is_long(msg->type)) { in gen11_dsi_host_transfer()
1845 struct intel_display *display = to_intel_display(&intel_dsi->base); in icl_dphy_param_init()
1846 struct intel_connector *connector = intel_dsi->attached_connector; in icl_dphy_param_init()
1847 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; in icl_dphy_param_init()
1856 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in icl_dphy_param_init()
1857 ths_prepare_ns = max(mipi_config->ths_prepare, in icl_dphy_param_init()
1858 mipi_config->tclk_prepare); in icl_dphy_param_init()
1869 drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n", in icl_dphy_param_init()
1875 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - in icl_dphy_param_init()
1878 drm_dbg_kms(display->drm, in icl_dphy_param_init()
1886 drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n", in icl_dphy_param_init()
1892 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); in icl_dphy_param_init()
1894 drm_dbg_kms(display->drm, in icl_dphy_param_init()
1900 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - in icl_dphy_param_init()
1903 drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n", in icl_dphy_param_init()
1909 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); in icl_dphy_param_init()
1911 drm_dbg_kms(display->drm, in icl_dphy_param_init()
1918 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | in icl_dphy_param_init()
1928 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | in icl_dphy_param_init()
1945 intel_attach_scaling_mode_property(&connector->base); in icl_dsi_add_properties()
1947 drm_connector_set_panel_orientation_with_quirk(&connector->base, in icl_dsi_add_properties()
1949 fixed_mode->hdisplay, in icl_dsi_add_properties()
1950 fixed_mode->vdisplay); in icl_dsi_add_properties()
1976 encoder = &intel_dsi->base; in icl_dsi_init()
1977 intel_dsi->attached_connector = intel_connector; in icl_dsi_init()
1978 connector = &intel_connector->base; in icl_dsi_init()
1980 encoder->devdata = devdata; in icl_dsi_init()
1983 drm_encoder_init(display->drm, &encoder->base, in icl_dsi_init()
1987 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; in icl_dsi_init()
1988 encoder->pre_enable = gen11_dsi_pre_enable; in icl_dsi_init()
1989 encoder->enable = gen11_dsi_enable; in icl_dsi_init()
1990 encoder->disable = gen11_dsi_disable; in icl_dsi_init()
1991 encoder->post_disable = gen11_dsi_post_disable; in icl_dsi_init()
1992 encoder->port = port; in icl_dsi_init()
1993 encoder->get_config = gen11_dsi_get_config; in icl_dsi_init()
1994 encoder->sync_state = gen11_dsi_sync_state; in icl_dsi_init()
1995 encoder->update_pipe = intel_backlight_update; in icl_dsi_init()
1996 encoder->compute_config = gen11_dsi_compute_config; in icl_dsi_init()
1997 encoder->get_hw_state = gen11_dsi_get_hw_state; in icl_dsi_init()
1998 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; in icl_dsi_init()
1999 encoder->type = INTEL_OUTPUT_DSI; in icl_dsi_init()
2000 encoder->cloneable = 0; in icl_dsi_init()
2001 encoder->pipe_mask = ~0; in icl_dsi_init()
2002 encoder->power_domain = POWER_DOMAIN_PORT_DSI; in icl_dsi_init()
2003 encoder->get_power_domains = gen11_dsi_get_power_domains; in icl_dsi_init()
2004 encoder->disable_clock = gen11_dsi_gate_clocks; in icl_dsi_init()
2005 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; in icl_dsi_init()
2006 encoder->shutdown = intel_dsi_shutdown; in icl_dsi_init()
2009 drm_connector_init(display->drm, connector, in icl_dsi_init()
2013 connector->display_info.subpixel_order = SubPixelHorizontalRGB; in icl_dsi_init()
2014 intel_connector->get_hw_state = intel_connector_get_hw_state; in icl_dsi_init()
2019 intel_dsi->panel_power_off_time = ktime_get_boottime(); in icl_dsi_init()
2021 intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL); in icl_dsi_init()
2023 mutex_lock(&display->drm->mode_config.mutex); in icl_dsi_init()
2025 mutex_unlock(&display->drm->mode_config.mutex); in icl_dsi_init()
2028 drm_err(display->drm, "DSI fixed mode info missing\n"); in icl_dsi_init()
2036 if (intel_connector->panel.vbt.dsi.config->dual_link) in icl_dsi_init()
2037 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
2039 intel_dsi->ports = BIT(port); in icl_dsi_init()
2041 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in icl_dsi_init()
2042 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; in icl_dsi_init()
2044 if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in icl_dsi_init()
2045 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; in icl_dsi_init()
2047 for_each_dsi_port(port, intel_dsi->ports) { in icl_dsi_init()
2054 intel_dsi->dsi_hosts[port] = host; in icl_dsi_init()
2058 drm_dbg_kms(display->drm, "no device found\n"); in icl_dsi_init()
2069 drm_encoder_cleanup(&encoder->base); in icl_dsi_init()