27 	 * We can only enable IPS after we enable a plane and wait for a vblank  in hsw_ips_enable()
36 	if (display->ips.false_color)  in hsw_ips_enable()
45 		 * value in IPS_CTL bit 31 after enabling IPS through the  in hsw_ips_enable()
60 				"Timed out waiting for IPS enable\n");  in hsw_ips_enable()
78 		 * Wait for PCODE to finish disabling IPS. The BSpec specified  in hsw_ips_disable()
84 				"Timed out waiting for IPS disable\n");  in hsw_ips_disable()
113 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.  in hsw_ips_need_disable()
115 	 * Disable IPS before we program the LUT.  in hsw_ips_need_disable()
154 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.  in hsw_ips_need_enable()
156 	 * Re-enable IPS after the LUT has been programmed.  in hsw_ips_need_enable()
164 	 * We can't read out IPS on broadwell, assume the worst and  in hsw_ips_need_enable()
165 	 * forcibly enable IPS on the first fastset.  in hsw_ips_need_enable()
185 /* IPS only exists on ULT machines and is tied to pipe A. */
199 	/* IPS only exists on ULT machines and is tied to pipe A. */  in hsw_crtc_state_ips_capable()
214 	 * Should measure whether using a lower cdclk w/o IPS  in hsw_crtc_state_ips_capable()
233 	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */  in hsw_ips_min_cdclk()
250 	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets  in hsw_ips_compute_config()
258 	/* IPS should be fine as long as at least one plane is enabled. */  in hsw_ips_compute_config()
269 		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */  in hsw_ips_compute_config()
292 		 * We cannot readout IPS state on broadwell, set to  in hsw_ips_get_config()
305 	*val = display->ips.false_color;  in hsw_ips_debugfs_false_color_get()
321 	display->ips.false_color = val;  in hsw_ips_debugfs_false_color_set()