Lines Matching +full:0 +full:x114

7 #define HIBMC_DP_AUX_CMD_ADDR			0x50
8 #define HIBMC_DP_AUX_WR_DATA0			0x54
9 #define HIBMC_DP_AUX_WR_DATA1			0x58
10 #define HIBMC_DP_AUX_WR_DATA2			0x5c
11 #define HIBMC_DP_AUX_WR_DATA3			0x60
12 #define HIBMC_DP_AUX_RD_DATA0			0x64
13 #define HIBMC_DP_AUX_REQ			0x74
14 #define HIBMC_DP_AUX_STATUS			0x78
15 #define HIBMC_DP_PHYIF_CTRL0			0xa0
16 #define HIBMC_DP_VIDEO_CTRL			0x100
17 #define HIBMC_DP_VIDEO_CONFIG0			0x104
18 #define HIBMC_DP_VIDEO_CONFIG1			0x108
19 #define HIBMC_DP_VIDEO_CONFIG2			0x10c
20 #define HIBMC_DP_VIDEO_CONFIG3			0x110
21 #define HIBMC_DP_VIDEO_PACKET			0x114
22 #define HIBMC_DP_VIDEO_MSA0			0x118
23 #define HIBMC_DP_VIDEO_MSA1			0x11c
24 #define HIBMC_DP_VIDEO_MSA2			0x120
25 #define HIBMC_DP_VIDEO_HORIZONTAL_SIZE		0X124
26 #define HIBMC_DP_TIMING_GEN_CONFIG0		0x26c
27 #define HIBMC_DP_TIMING_GEN_CONFIG2		0x274
28 #define HIBMC_DP_TIMING_GEN_CONFIG3		0x278
29 #define HIBMC_DP_HDCP_CFG			0x600
30 #define HIBMC_DP_DPTX_RST_CTRL			0x700
31 #define HIBMC_DP_DPTX_CLK_CTRL			0x704
32 #define HIBMC_DP_DPTX_GCTL0			0x708
33 #define HIBMC_DP_INTR_ENABLE			0x720
34 #define HIBMC_DP_INTR_ORIGINAL_STATUS		0x728
35 #define HIBMC_DP_TIMING_MODEL_CTRL		0x884
36 #define HIBMC_DP_TIMING_SYNC_CTRL		0xFF0
44 #define HIBMC_DP_CFG_AUX_REQ			BIT(0)
46 #define HIBMC_DP_CFG_AUX_TIMEOUT		BIT(0)
50 #define HIBMC_DP_CFG_SCRAMBLE_EN		BIT(0)
53 #define HIBMC_DP_CFG_TIMING_GEN0_HBLANK		GENMASK(15, 0)
55 #define HIBMC_DP_CFG_TIMING_GEN0_VBLANK		GENMASK(15, 0)
58 #define HIBMC_DP_CFG_STREAM_HBLANK		GENMASK(15, 0)
59 #define HIBMC_DP_CFG_STREAM_HSYNC_WIDTH		GENMASK(15, 0)
61 #define HIBMC_DP_CFG_STREAM_VBLANK		GENMASK(15, 0)
63 #define HIBMC_DP_CFG_STREAM_VSYNC_WIDTH		GENMASK(15, 0)
65 #define HIBMC_DP_CFG_STREAM_HSTART		GENMASK(15, 0)
71 #define HIBMC_DP_CFG_STREAM_TU_SYMBOL_SIZE	GENMASK(5, 0)
74 #define HIBMC_DP_CFG_STREAM_HBLANK_SIZE		GENMASK(15, 0)