30 	if (value % 10 == 9) { /* 9 carry */  in hibmc_dp_set_tu()
31 		tu_symbol_size = value / 10 + 1;  in hibmc_dp_set_tu()
34 		tu_symbol_size = value / 10;  in hibmc_dp_set_tu()
35 		tu_symbol_frac_size = value % 10 + 1;  in hibmc_dp_set_tu()
65 		      (mode->clock * 10 * HIBMC_DP_SYMBOL_PER_FCLK);  in hibmc_dp_set_sst()
132 	writel(HIBMC_DP_MSA1, dp->base + HIBMC_DP_VIDEO_MSA1);  in hibmc_dp_link_cfg()
133 	writel(HIBMC_DP_MSA2, dp->base + HIBMC_DP_VIDEO_MSA2);  in hibmc_dp_link_cfg()
164 	dp_dev->base = dp->mmio + HIBMC_DP_OFFSET;  in hibmc_dp_hw_init()
172 	writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG);  in hibmc_dp_hw_init()
174 	writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE);  in hibmc_dp_hw_init()
175 	writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS);  in hibmc_dp_hw_init()
177 	writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL);  in hibmc_dp_hw_init()
179 	writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL);  in hibmc_dp_hw_init()
190 		writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);  in hibmc_dp_display_en()
191 		hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_DPTX_GCTL0, BIT(10), 0x1);  in hibmc_dp_display_en()
192 		writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);  in hibmc_dp_display_en()
194 		hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_DPTX_GCTL0, BIT(10), 0);  in hibmc_dp_display_en()
195 		writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);  in hibmc_dp_display_en()
197 		writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);  in hibmc_dp_display_en()