Lines Matching +full:mipi +full:- +full:to +full:- +full:edp
1 // SPDX-License-Identifier: GPL-2.0
116 /* fudge factor required to account for 8b/10b encoding */
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
140 * @dev: Pointer to the top level (i2c) device.
146 * @dsi: Our MIPI DSI source.
148 * @next_bridge: The bridge on the eDP side.
149 * @enable_gpio: The GPIO we toggle to enable the bridge.
152 * @ln_assign: Value to program to the LN_ASSIGN register.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
158 * @gchip_output: A cache of whether we've set GPIOs to output. This
159 * serves double-duty of keeping track of the direction and
165 * each other's read-modify-write.
168 * @pwm_enabled: Used to track if the PWM signal is currently enabled.
170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); in ti_sn65dsi86_read_u16()
244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); in ti_sn65dsi86_write_u16()
251 &pdata->bridge.encoder->crtc->state->adjusted_mode; in ti_sn_bridge_get_dsi_freq()
253 bit_rate_khz = mode->clock * in ti_sn_bridge_get_dsi_freq()
254 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); in ti_sn_bridge_get_dsi_freq()
255 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); in ti_sn_bridge_get_dsi_freq()
285 if (pdata->refclk) { in ti_sn_bridge_set_refclk_freq()
286 refclk_rate = clk_get_rate(pdata->refclk); in ti_sn_bridge_set_refclk_freq()
289 clk_prepare_enable(pdata->refclk); in ti_sn_bridge_set_refclk_freq()
296 /* for i equals to refclk_lut_size means default frequency */ in ti_sn_bridge_set_refclk_freq()
305 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, in ti_sn_bridge_set_refclk_freq()
309 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, in ti_sn_bridge_set_refclk_freq()
312 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; in ti_sn_bridge_set_refclk_freq()
317 mutex_lock(&pdata->comms_mutex); in ti_sn65dsi86_enable_comms()
323 * HPD on this bridge chip is a bit useless. This is an eDP bridge in ti_sn65dsi86_enable_comms()
324 * so the HPD is an internal signal that's only there to signal that in ti_sn65dsi86_enable_comms()
327 * voltage, and temperate--I measured it at about 200 ms). One in ti_sn65dsi86_enable_comms()
334 * If HPD somehow makes sense on some future panel we'll have to in ti_sn65dsi86_enable_comms()
335 * change this to be conditional on someone specifying that HPD should in ti_sn65dsi86_enable_comms()
338 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, in ti_sn65dsi86_enable_comms()
341 pdata->comms_enabled = true; in ti_sn65dsi86_enable_comms()
343 mutex_unlock(&pdata->comms_mutex); in ti_sn65dsi86_enable_comms()
348 mutex_lock(&pdata->comms_mutex); in ti_sn65dsi86_disable_comms()
350 pdata->comms_enabled = false; in ti_sn65dsi86_disable_comms()
351 clk_disable_unprepare(pdata->refclk); in ti_sn65dsi86_disable_comms()
353 mutex_unlock(&pdata->comms_mutex); in ti_sn65dsi86_disable_comms()
361 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); in ti_sn65dsi86_resume()
363 DRM_ERROR("failed to enable supplies %d\n", ret); in ti_sn65dsi86_resume()
370 gpiod_set_value_cansleep(pdata->enable_gpio, 1); in ti_sn65dsi86_resume()
376 * pre_enable(). Without a reference clock we need the MIPI reference in ti_sn65dsi86_resume()
379 if (pdata->refclk) in ti_sn65dsi86_resume()
390 if (pdata->refclk) in ti_sn65dsi86_suspend()
393 gpiod_set_value_cansleep(pdata->enable_gpio, 0); in ti_sn65dsi86_suspend()
395 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); in ti_sn65dsi86_suspend()
397 DRM_ERROR("failed to disable supplies %d\n", ret); in ti_sn65dsi86_suspend()
410 struct ti_sn65dsi86 *pdata = s->private; in status_show()
415 pm_runtime_get_sync(pdata->dev); in status_show()
419 regmap_read(pdata->regmap, reg, &val); in status_show()
423 pm_runtime_put_autosuspend(pdata->dev); in status_show()
437 struct device *dev = pdata->dev; in ti_sn65dsi86_debugfs_init()
457 /* -----------------------------------------------------------------------------
482 struct device *dev = pdata->dev; in ti_sn65dsi86_add_aux_device()
489 return -ENOMEM; in ti_sn65dsi86_add_aux_device()
491 aux->name = name; in ti_sn65dsi86_add_aux_device()
492 aux->id = (client->adapter->nr << 10) | client->addr; in ti_sn65dsi86_add_aux_device()
493 aux->dev.parent = dev; in ti_sn65dsi86_add_aux_device()
494 aux->dev.release = ti_sn65dsi86_aux_device_release; in ti_sn65dsi86_add_aux_device()
495 device_set_of_node_from_dev(&aux->dev, dev); in ti_sn65dsi86_add_aux_device()
515 /* -----------------------------------------------------------------------------
528 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); in ti_sn_aux_transfer()
529 u32 request_val = AUX_CMD_REQ(msg->request); in ti_sn_aux_transfer()
530 u8 *buf = msg->buffer; in ti_sn_aux_transfer()
531 unsigned int len = msg->size; in ti_sn_aux_transfer()
535 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; in ti_sn_aux_transfer()
538 return -EINVAL; in ti_sn_aux_transfer()
540 pm_runtime_get_sync(pdata->dev); in ti_sn_aux_transfer()
541 mutex_lock(&pdata->comms_mutex); in ti_sn_aux_transfer()
544 * If someone tries to do a DDC over AUX transaction before pre_enable() in ti_sn_aux_transfer()
546 * do it. Fail right away. This prevents non-refclk users from reading in ti_sn_aux_transfer()
549 if (!pdata->comms_enabled) { in ti_sn_aux_transfer()
550 ret = -EIO; in ti_sn_aux_transfer()
559 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); in ti_sn_aux_transfer()
561 msg->reply = 0; in ti_sn_aux_transfer()
564 ret = -EINVAL; in ti_sn_aux_transfer()
569 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, in ti_sn_aux_transfer()
571 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, in ti_sn_aux_transfer()
575 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); in ti_sn_aux_transfer()
578 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, in ti_sn_aux_transfer()
583 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); in ti_sn_aux_transfer()
586 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, in ti_sn_aux_transfer()
591 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); in ti_sn_aux_transfer()
601 ret = -ETIMEDOUT; in ti_sn_aux_transfer()
606 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len); in ti_sn_aux_transfer()
614 msg->reply |= DP_AUX_I2C_REPLY_NACK; in ti_sn_aux_transfer()
618 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; in ti_sn_aux_transfer()
626 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); in ti_sn_aux_transfer()
629 mutex_unlock(&pdata->comms_mutex); in ti_sn_aux_transfer()
630 pm_runtime_mark_last_busy(pdata->dev); in ti_sn_aux_transfer()
631 pm_runtime_put_autosuspend(pdata->dev); in ti_sn_aux_transfer()
642 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait in ti_sn_aux_wait_hpd_asserted()
645 * In case we are asked to wait forever (wait_us=0) take conservative in ti_sn_aux_wait_hpd_asserted()
659 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); in ti_sn_aux_probe()
662 pdata->aux.name = "ti-sn65dsi86-aux"; in ti_sn_aux_probe()
663 pdata->aux.dev = &adev->dev; in ti_sn_aux_probe()
664 pdata->aux.transfer = ti_sn_aux_transfer; in ti_sn_aux_probe()
665 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted; in ti_sn_aux_probe()
666 drm_dp_aux_init(&pdata->aux); in ti_sn_aux_probe()
668 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); in ti_sn_aux_probe()
673 * The eDP to MIPI bridge parts don't work until the AUX channel is in ti_sn_aux_probe()
676 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); in ti_sn_aux_probe()
690 /*------------------------------------------------------------------------------
704 struct device *dev = pdata->dev; in ti_sn_attach_host()
710 host = of_find_mipi_dsi_host_by_node(pdata->host_node); in ti_sn_attach_host()
712 return -EPROBE_DEFER; in ti_sn_attach_host()
714 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info); in ti_sn_attach_host()
718 /* TODO: setting to 4 MIPI lanes always for now */ in ti_sn_attach_host()
719 dsi->lanes = 4; in ti_sn_attach_host()
720 dsi->format = MIPI_DSI_FMT_RGB888; in ti_sn_attach_host()
721 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; in ti_sn_attach_host()
725 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); in ti_sn_attach_host()
728 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; in ti_sn_attach_host()
730 pdata->dsi = dsi; in ti_sn_attach_host()
732 return devm_mipi_dsi_attach(&adev->dev, dsi); in ti_sn_attach_host()
741 pdata->aux.drm_dev = bridge->dev; in ti_sn_bridge_attach()
742 ret = drm_dp_aux_register(&pdata->aux); in ti_sn_bridge_attach()
744 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); in ti_sn_bridge_attach()
750 * We never want the next bridge to *also* create a connector. in ti_sn_bridge_attach()
752 ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge, in ti_sn_bridge_attach()
753 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); in ti_sn_bridge_attach()
760 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, in ti_sn_bridge_attach()
761 pdata->bridge.encoder); in ti_sn_bridge_attach()
762 if (IS_ERR(pdata->connector)) { in ti_sn_bridge_attach()
763 ret = PTR_ERR(pdata->connector); in ti_sn_bridge_attach()
767 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); in ti_sn_bridge_attach()
772 drm_dp_aux_unregister(&pdata->aux); in ti_sn_bridge_attach()
778 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); in ti_sn_bridge_detach()
787 if (mode->clock > 594000) in ti_sn_bridge_mode_valid()
795 if ((mode->hsync_start - mode->hdisplay) > 0xff) in ti_sn_bridge_mode_valid()
798 if ((mode->vsync_start - mode->vdisplay) > 0xff) in ti_sn_bridge_mode_valid()
801 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) in ti_sn_bridge_mode_valid()
804 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) in ti_sn_bridge_mode_valid()
807 if ((mode->htotal - mode->hsync_end) > 0xff) in ti_sn_bridge_mode_valid()
810 if ((mode->vtotal - mode->vsync_end) > 0xff) in ti_sn_bridge_mode_valid()
822 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); in ti_sn_bridge_atomic_disable()
830 &pdata->bridge.encoder->crtc->state->adjusted_mode; in ti_sn_bridge_set_dsi_rate()
833 bit_rate_mhz = (mode->clock / 1000) * in ti_sn_bridge_set_dsi_rate()
834 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); in ti_sn_bridge_set_dsi_rate()
835 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); in ti_sn_bridge_set_dsi_rate()
839 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); in ti_sn_bridge_set_dsi_rate()
840 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); in ti_sn_bridge_set_dsi_rate()
845 if (connector->display_info.bpc <= 6) in ti_sn_bridge_get_bpp()
852 * LUT index corresponds to register value and
853 * LUT values corresponds to dp data rate supported
865 &pdata->bridge.encoder->crtc->state->adjusted_mode; in ti_sn_bridge_calc_min_dp_rate_idx()
868 bit_rate_khz = mode->clock * bpp; in ti_sn_bridge_calc_min_dp_rate_idx()
872 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); in ti_sn_bridge_calc_min_dp_rate_idx()
874 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) in ti_sn_bridge_calc_min_dp_rate_idx()
890 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); in ti_sn_bridge_read_valid_rates()
892 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
893 "Can't read eDP rev (%d), assuming 1.1\n", ret); in ti_sn_bridge_read_valid_rates()
898 /* eDP 1.4 devices must provide a custom table */ in ti_sn_bridge_read_valid_rates()
901 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, in ti_sn_bridge_read_valid_rates()
905 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
908 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ in ti_sn_bridge_read_valid_rates()
931 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
932 "No matching eDP rates in table; falling back\n"); in ti_sn_bridge_read_valid_rates()
936 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); in ti_sn_bridge_read_valid_rates()
938 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
946 DRM_DEV_ERROR(pdata->dev, in ti_sn_bridge_read_valid_rates()
967 &pdata->bridge.encoder->crtc->state->adjusted_mode; in ti_sn_bridge_set_video_timings()
970 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in ti_sn_bridge_set_video_timings()
972 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in ti_sn_bridge_set_video_timings()
976 mode->hdisplay); in ti_sn_bridge_set_video_timings()
978 mode->vdisplay); in ti_sn_bridge_set_video_timings()
979 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, in ti_sn_bridge_set_video_timings()
980 (mode->hsync_end - mode->hsync_start) & 0xFF); in ti_sn_bridge_set_video_timings()
981 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, in ti_sn_bridge_set_video_timings()
982 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | in ti_sn_bridge_set_video_timings()
984 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, in ti_sn_bridge_set_video_timings()
985 (mode->vsync_end - mode->vsync_start) & 0xFF); in ti_sn_bridge_set_video_timings()
986 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, in ti_sn_bridge_set_video_timings()
987 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | in ti_sn_bridge_set_video_timings()
990 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, in ti_sn_bridge_set_video_timings()
991 (mode->htotal - mode->hsync_end) & 0xFF); in ti_sn_bridge_set_video_timings()
992 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, in ti_sn_bridge_set_video_timings()
993 (mode->vtotal - mode->vsync_end) & 0xFF); in ti_sn_bridge_set_video_timings()
995 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, in ti_sn_bridge_set_video_timings()
996 (mode->hsync_start - mode->hdisplay) & 0xFF); in ti_sn_bridge_set_video_timings()
997 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, in ti_sn_bridge_set_video_timings()
998 (mode->vsync_start - mode->vdisplay) & 0xFF); in ti_sn_bridge_set_video_timings()
1008 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); in ti_sn_get_max_lanes()
1010 DRM_DEV_ERROR(pdata->dev, in ti_sn_get_max_lanes()
1026 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, in ti_sn_link_training()
1030 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); in ti_sn_link_training()
1032 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, in ti_sn_link_training()
1041 * We'll try to link train several times. As part of link training in ti_sn_link_training()
1042 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If in ti_sn_link_training()
1044 * we need to try again. in ti_sn_link_training()
1048 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); in ti_sn_link_training()
1049 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, in ti_sn_link_training()
1057 ret = -EIO; in ti_sn_link_training()
1066 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); in ti_sn_link_training()
1071 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); in ti_sn_link_training()
1085 int ret = -EINVAL; in ti_sn_bridge_atomic_enable()
1089 connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state, in ti_sn_bridge_atomic_enable()
1090 bridge->encoder); in ti_sn_bridge_atomic_enable()
1092 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); in ti_sn_bridge_atomic_enable()
1097 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); in ti_sn_bridge_atomic_enable()
1100 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); in ti_sn_bridge_atomic_enable()
1101 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, in ti_sn_bridge_atomic_enable()
1104 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); in ti_sn_bridge_atomic_enable()
1105 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, in ti_sn_bridge_atomic_enable()
1106 pdata->ln_polrs << LN_POLRS_OFFSET); in ti_sn_bridge_atomic_enable()
1113 * this method is enabled for eDP panels. An eDP panel must support this in ti_sn_bridge_atomic_enable()
1114 * authentication method. We need to enable this method in the eDP panel in ti_sn_bridge_atomic_enable()
1115 * at DisplayPort address 0x0010A prior to link training. in ti_sn_bridge_atomic_enable()
1118 * we need to disable the scrambler. in ti_sn_bridge_atomic_enable()
1120 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { in ti_sn_bridge_atomic_enable()
1121 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, in ti_sn_bridge_atomic_enable()
1124 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, in ti_sn_bridge_atomic_enable()
1127 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, in ti_sn_bridge_atomic_enable()
1134 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); in ti_sn_bridge_atomic_enable()
1137 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); in ti_sn_bridge_atomic_enable()
1138 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, in ti_sn_bridge_atomic_enable()
1155 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); in ti_sn_bridge_atomic_enable()
1163 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, in ti_sn_bridge_atomic_enable()
1172 pm_runtime_get_sync(pdata->dev); in ti_sn_bridge_atomic_pre_enable()
1174 if (!pdata->refclk) in ti_sn_bridge_atomic_pre_enable()
1187 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); in ti_sn_bridge_atomic_post_disable()
1188 /* Num lanes to 0 as per power sequencing in data sheet */ in ti_sn_bridge_atomic_post_disable()
1189 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); in ti_sn_bridge_atomic_post_disable()
1191 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); in ti_sn_bridge_atomic_post_disable()
1193 if (!pdata->refclk) in ti_sn_bridge_atomic_post_disable()
1196 pm_runtime_put_sync(pdata->dev); in ti_sn_bridge_atomic_post_disable()
1204 pm_runtime_get_sync(pdata->dev); in ti_sn_bridge_detect()
1205 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); in ti_sn_bridge_detect()
1206 pm_runtime_put_autosuspend(pdata->dev); in ti_sn_bridge_detect()
1217 return drm_edid_read_ddc(connector, &pdata->aux.ddc); in ti_sn_bridge_edid_read()
1249 * normal polarity if nothing is specified. It's OK to specify just in ti_sn_bridge_parse_lanes()
1250 * data-lanes but not lane-polarities but not vice versa. in ti_sn_bridge_parse_lanes()
1256 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); in ti_sn_bridge_parse_lanes()
1259 of_property_read_u32_array(endpoint, "data-lanes", in ti_sn_bridge_parse_lanes()
1261 of_property_read_u32_array(endpoint, "lane-polarities", in ti_sn_bridge_parse_lanes()
1270 * data-lanes had fewer elements so that we nicely initialize in ti_sn_bridge_parse_lanes()
1273 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { in ti_sn_bridge_parse_lanes()
1279 pdata->dp_lanes = dp_lanes; in ti_sn_bridge_parse_lanes()
1280 pdata->ln_assign = ln_assign; in ti_sn_bridge_parse_lanes()
1281 pdata->ln_polrs = ln_polrs; in ti_sn_bridge_parse_lanes()
1286 struct device_node *np = pdata->dev->of_node; in ti_sn_bridge_parse_dsi_host()
1288 pdata->host_node = of_graph_get_remote_node(np, 0, 0); in ti_sn_bridge_parse_dsi_host()
1290 if (!pdata->host_node) { in ti_sn_bridge_parse_dsi_host()
1292 return -ENODEV; in ti_sn_bridge_parse_dsi_host()
1301 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); in ti_sn_bridge_probe()
1302 struct device_node *np = pdata->dev->of_node; in ti_sn_bridge_probe()
1305 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0); in ti_sn_bridge_probe()
1306 if (IS_ERR(pdata->next_bridge)) in ti_sn_bridge_probe()
1307 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge), in ti_sn_bridge_probe()
1308 "failed to create panel bridge\n"); in ti_sn_bridge_probe()
1316 pdata->bridge.funcs = &ti_sn_bridge_funcs; in ti_sn_bridge_probe()
1317 pdata->bridge.of_node = np; in ti_sn_bridge_probe()
1318 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort in ti_sn_bridge_probe()
1321 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) in ti_sn_bridge_probe()
1322 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; in ti_sn_bridge_probe()
1324 drm_bridge_add(&pdata->bridge); in ti_sn_bridge_probe()
1328 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n"); in ti_sn_bridge_probe()
1335 drm_bridge_remove(&pdata->bridge); in ti_sn_bridge_probe()
1341 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); in ti_sn_bridge_remove()
1346 drm_bridge_remove(&pdata->bridge); in ti_sn_bridge_remove()
1348 of_node_put(pdata->host_node); in ti_sn_bridge_remove()
1363 /* -----------------------------------------------------------------------------
1369 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; in ti_sn_pwm_pin_request()
1374 atomic_set(&pdata->pwm_pin_busy, 0); in ti_sn_pwm_pin_release()
1398 * - The PWM signal is not driven when the chip is powered down, or in its
1400 * described in the documentation. In order to save power, state->enabled is
1401 * interpreted as denoting if the signal is expected to be valid, and is used
1402 * to determine if the chip needs to be kept powered.
1403 * - Changing both period and duty_cycle is not done atomically, neither is the
1404 * multi-byte register updates, so the output might briefly be undefined
1419 if (!pdata->pwm_enabled) { in ti_sn_pwm_apply()
1425 if (state->enabled) { in ti_sn_pwm_apply()
1426 if (!pdata->pwm_enabled) { in ti_sn_pwm_apply()
1432 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, in ti_sn_pwm_apply()
1436 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n"); in ti_sn_pwm_apply()
1445 * PWM_FREQ = ----------------------------------- in ti_sn_pwm_apply()
1456 * In order to keep BACKLIGHT_SCALE within its 16 bits, in ti_sn_pwm_apply()
1460 * PWM_PRE_DIV >= ------------------------- in ti_sn_pwm_apply()
1463 * To simplify the search and to favour higher resolution of in ti_sn_pwm_apply()
1469 * BACKLIGHT_SCALE = ---------------------- - 1 in ti_sn_pwm_apply()
1473 * to nanoseconds is necessary. in ti_sn_pwm_apply()
1477 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { in ti_sn_pwm_apply()
1478 ret = -EINVAL; in ti_sn_pwm_apply()
1484 * Limit period to this to avoid overflows in ti_sn_pwm_apply()
1487 pdata->pwm_refclk_freq); in ti_sn_pwm_apply()
1488 period = min(state->period, period_max); in ti_sn_pwm_apply()
1490 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, in ti_sn_pwm_apply()
1492 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; in ti_sn_pwm_apply()
1498 * ------- = --------------------- in ti_sn_pwm_apply()
1502 * to definition above and adjusting for nanosecond in ti_sn_pwm_apply()
1505 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, in ti_sn_pwm_apply()
1510 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); in ti_sn_pwm_apply()
1512 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n"); in ti_sn_pwm_apply()
1520 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | in ti_sn_pwm_apply()
1521 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); in ti_sn_pwm_apply()
1522 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); in ti_sn_pwm_apply()
1524 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n"); in ti_sn_pwm_apply()
1528 pdata->pwm_enabled = state->enabled; in ti_sn_pwm_apply()
1531 if (!pdata->pwm_enabled) in ti_sn_pwm_apply()
1547 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); in ti_sn_pwm_get_state()
1559 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); in ti_sn_pwm_get_state()
1563 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); in ti_sn_pwm_get_state()
1565 state->polarity = PWM_POLARITY_INVERSED; in ti_sn_pwm_get_state()
1567 state->polarity = PWM_POLARITY_NORMAL; in ti_sn_pwm_get_state()
1569 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), in ti_sn_pwm_get_state()
1570 pdata->pwm_refclk_freq); in ti_sn_pwm_get_state()
1571 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, in ti_sn_pwm_get_state()
1572 pdata->pwm_refclk_freq); in ti_sn_pwm_get_state()
1574 if (state->duty_cycle > state->period) in ti_sn_pwm_get_state()
1575 state->duty_cycle = state->period; in ti_sn_pwm_get_state()
1591 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); in ti_sn_pwm_probe()
1593 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0); in ti_sn_pwm_probe()
1599 chip->ops = &ti_sn_pwm_ops; in ti_sn_pwm_probe()
1600 chip->of_xlate = of_pwm_single_xlate; in ti_sn_pwm_probe()
1602 devm_pm_runtime_enable(&adev->dev); in ti_sn_pwm_probe()
1609 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); in ti_sn_pwm_remove()
1611 pwmchip_remove(pdata->pchip); in ti_sn_pwm_remove()
1613 if (pdata->pwm_enabled) in ti_sn_pwm_remove()
1614 pm_runtime_put_sync(&adev->dev); in ti_sn_pwm_remove()
1647 /* -----------------------------------------------------------------------------
1656 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) in tn_sn_bridge_of_xlate()
1657 return -EINVAL; in tn_sn_bridge_of_xlate()
1659 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) in tn_sn_bridge_of_xlate()
1660 return -EINVAL; in tn_sn_bridge_of_xlate()
1663 *flags = gpiospec->args[1]; in tn_sn_bridge_of_xlate()
1665 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; in tn_sn_bridge_of_xlate()
1674 * We already have to keep track of the direction because we use in ti_sn_bridge_gpio_get_direction()
1675 * that to figure out whether we've powered the device. We can in ti_sn_bridge_gpio_get_direction()
1677 * to ask its direction. in ti_sn_bridge_gpio_get_direction()
1679 return test_bit(offset, pdata->gchip_output) ? in ti_sn_bridge_gpio_get_direction()
1691 * powered--we just power it on to read the pin. NOTE: part of in ti_sn_bridge_gpio_get()
1693 * powered back on) to all 4 GPIOs being configured as GPIO input. in ti_sn_bridge_gpio_get()
1697 pm_runtime_get_sync(pdata->dev); in ti_sn_bridge_gpio_get()
1698 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); in ti_sn_bridge_gpio_get()
1699 pm_runtime_put_autosuspend(pdata->dev); in ti_sn_bridge_gpio_get()
1713 if (!test_bit(offset, pdata->gchip_output)) { in ti_sn_bridge_gpio_set()
1714 dev_err(pdata->dev, "Ignoring GPIO set while input\n"); in ti_sn_bridge_gpio_set()
1719 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, in ti_sn_bridge_gpio_set()
1723 dev_warn(pdata->dev, in ti_sn_bridge_gpio_set()
1724 "Failed to set bridge GPIO %u: %d\n", offset, ret); in ti_sn_bridge_gpio_set()
1734 if (!test_and_clear_bit(offset, pdata->gchip_output)) in ti_sn_bridge_gpio_direction_input()
1737 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, in ti_sn_bridge_gpio_direction_input()
1741 set_bit(offset, pdata->gchip_output); in ti_sn_bridge_gpio_direction_input()
1750 pm_runtime_put_autosuspend(pdata->dev); in ti_sn_bridge_gpio_direction_input()
1762 if (test_and_set_bit(offset, pdata->gchip_output)) in ti_sn_bridge_gpio_direction_output()
1765 pm_runtime_get_sync(pdata->dev); in ti_sn_bridge_gpio_direction_output()
1767 /* Set value first to avoid glitching */ in ti_sn_bridge_gpio_direction_output()
1771 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, in ti_sn_bridge_gpio_direction_output()
1775 clear_bit(offset, pdata->gchip_output); in ti_sn_bridge_gpio_direction_output()
1776 pm_runtime_put_autosuspend(pdata->dev); in ti_sn_bridge_gpio_direction_output()
1810 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); in ti_sn_gpio_probe()
1813 /* Only init if someone is going to use us as a GPIO controller */ in ti_sn_gpio_probe()
1814 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) in ti_sn_gpio_probe()
1817 pdata->gchip.label = dev_name(pdata->dev); in ti_sn_gpio_probe()
1818 pdata->gchip.parent = pdata->dev; in ti_sn_gpio_probe()
1819 pdata->gchip.owner = THIS_MODULE; in ti_sn_gpio_probe()
1820 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; in ti_sn_gpio_probe()
1821 pdata->gchip.of_gpio_n_cells = 2; in ti_sn_gpio_probe()
1822 pdata->gchip.request = ti_sn_bridge_gpio_request; in ti_sn_gpio_probe()
1823 pdata->gchip.free = ti_sn_bridge_gpio_free; in ti_sn_gpio_probe()
1824 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; in ti_sn_gpio_probe()
1825 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; in ti_sn_gpio_probe()
1826 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; in ti_sn_gpio_probe()
1827 pdata->gchip.get = ti_sn_bridge_gpio_get; in ti_sn_gpio_probe()
1828 pdata->gchip.set = ti_sn_bridge_gpio_set; in ti_sn_gpio_probe()
1829 pdata->gchip.can_sleep = true; in ti_sn_gpio_probe()
1830 pdata->gchip.names = ti_sn_bridge_gpio_names; in ti_sn_gpio_probe()
1831 pdata->gchip.ngpio = SN_NUM_GPIOS; in ti_sn_gpio_probe()
1832 pdata->gchip.base = -1; in ti_sn_gpio_probe()
1833 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); in ti_sn_gpio_probe()
1835 dev_err(pdata->dev, "can't add gpio chip\n"); in ti_sn_gpio_probe()
1870 /* -----------------------------------------------------------------------------
1888 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; in ti_sn65dsi86_parse_regulators()
1890 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, in ti_sn65dsi86_parse_regulators()
1891 pdata->supplies); in ti_sn65dsi86_parse_regulators()
1896 struct device *dev = &client->dev; in ti_sn65dsi86_probe()
1900 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { in ti_sn65dsi86_probe()
1902 return -ENODEV; in ti_sn65dsi86_probe()
1907 return -ENOMEM; in ti_sn65dsi86_probe()
1909 pdata->dev = dev; in ti_sn65dsi86_probe()
1911 mutex_init(&pdata->comms_mutex); in ti_sn65dsi86_probe()
1913 pdata->regmap = devm_regmap_init_i2c(client, in ti_sn65dsi86_probe()
1915 if (IS_ERR(pdata->regmap)) in ti_sn65dsi86_probe()
1916 return dev_err_probe(dev, PTR_ERR(pdata->regmap), in ti_sn65dsi86_probe()
1919 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", in ti_sn65dsi86_probe()
1921 if (IS_ERR(pdata->enable_gpio)) in ti_sn65dsi86_probe()
1922 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), in ti_sn65dsi86_probe()
1923 "failed to get enable gpio from DT\n"); in ti_sn65dsi86_probe()
1927 return dev_err_probe(dev, ret, "failed to parse regulators\n"); in ti_sn65dsi86_probe()
1929 pdata->refclk = devm_clk_get_optional(dev, "refclk"); in ti_sn65dsi86_probe()
1930 if (IS_ERR(pdata->refclk)) in ti_sn65dsi86_probe()
1931 return dev_err_probe(dev, PTR_ERR(pdata->refclk), in ti_sn65dsi86_probe()
1932 "failed to get reference clock\n"); in ti_sn65dsi86_probe()
1935 pm_runtime_set_autosuspend_delay(pdata->dev, 500); in ti_sn65dsi86_probe()
1936 pm_runtime_use_autosuspend(pdata->dev); in ti_sn65dsi86_probe()
1945 * motiviation here is to solve the chicken-and-egg problem of probe in ti_sn65dsi86_probe()
1946 * ordering. The bridge wants the panel to be there when it probes. in ti_sn65dsi86_probe()
1949 * bus or the pwm_chip. Having sub-devices allows the some sub devices in ti_sn65dsi86_probe()
1950 * to finish probing even if others return -EPROBE_DEFER and gets us in ti_sn65dsi86_probe()
1955 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); in ti_sn65dsi86_probe()
1961 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); in ti_sn65dsi86_probe()
1969 * AUX channel is there and this is a very simple solution to the in ti_sn65dsi86_probe()
1972 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); in ti_sn65dsi86_probe()
2047 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");