Lines Matching +full:hsic +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
33 /* System Control #1, default value: 0x00 */
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
52 #define BIT_DPD_PD_MHL_CLK_N BIT(1)
62 #define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1)
73 #define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1)
79 /* Video H Resolution #1, default value: 0x00 */
128 #define BIT_CTRL1_GPIO_I_6 BIT(1)
135 #define BIT_INT_CTRL_INTR_POLARITY BIT(1)
141 /* Interrupt Source #1, default value: 0x00 */
154 /* Interrupt #1 Mask, default value: 0x00 */
175 #define BIT_HPD_CTRL_GPIO_I_0 BIT(1)
186 #define BIT_CTRL_GPIO_I_2 BIT(1)
201 #define BIT_CEA_NEW_AVI BIT(1)
209 #define BIT_TMDS_CTRL4_SCDT_CKDT_SEL BIT(1)
220 #define BIT_BIST_RESET BIT(1)
249 #define BIT_LM_DDC_DDC_GRANT BIT(1)
260 #define BIT_DDC_MANUAL_IO_DSDA BIT(1)
273 /* DDC I2C Data In count #1, default value: 0x00 */
287 #define BIT_DDC_STATUS_DDC_FIFO_READ_IN_SUE BIT(1)
317 #define BIT_TEST_TXCTRL_HDMI_MODE BIT(1)
323 /* I2C Device Address re-assignment */
335 #define BIT_UTSRST_TTX_SRST BIT(1)
338 /* HSIC RX Control3, default value: 0x07 */
342 #define BIT_HRXCTRL3_STATUS_EN BIT(1)
345 /* HSIC RX INT Registers */
372 #define BIT_TTXINTL_TTX_INTR1 BIT(1)
383 #define BIT_TTXINTH_TTX_INTR9 BIT(1)
412 #define BIT_TDM_INTR_SYNC_WAIT BIT(1)
417 /* HSIC TX CRTL, default value: 0x00 */
422 #define BIT_HTXCTRL_HTX_DRVCONN1 BIT(1)
425 /* HSIC TX INT Low, default value: 0x00 */
428 /* HSIC TX INT High, default value: 0x00 */
431 /* HSIC Keeper, default value: 0x00 */
437 /* HSIC Flow Control General, default value: 0x02 */
439 #define BIT_FCGC_HSIC_HOSTMODE BIT(1)
442 /* HSIC Flow Control CTR13, default value: 0xfc */
445 /* HSIC Flow Control CTR14, default value: 0xff */
448 /* HSIC Flow Control CTR15, default value: 0xff */
451 /* HSIC Flow Control CTR50, default value: 0x03 */
454 /* HSIC Flow Control INTR0, default value: 0x00 */
469 #define BIT_TDMLLCTL_TTX_LL_TIE_LOW BIT(1)
519 #define BIT_PKT_FILTER_0_DROP_CTS_PKT BIT(1)
528 #define BIT_PKT_FILTER_1_DROP_GEN_PKT BIT(1)
538 #define BIT_TMDS_CSTAT_P3_SCDT BIT(1)
547 #define BIT_RX_HDMI_CTRL0_RX_HDMI_HDMI_MODE_EN BIT(1)
568 #define BIT_RX_HDMI_CLR_BUFFER_AIF_CLR_EN BIT(1)
597 #define BIT_TPI_CBUS_START_GET_EDID_START_0 BIT(1)
608 #define BIT_EDID_CTRL_INVALID_BKSV BIT(1)
633 #define BIT_TX_IP_BIST_CNTLSTA_TXBIST_EN BIT(1)
648 /* E-MSC General Control, default value: 0x80 */
656 #define BIT_GENCTL_START_TRAIN_SEQ BIT(1)
659 /* E-MSC Comma ErrorCNT, default value: 0x03 */
664 /* E-MSC RFIFO ByteCnt, default value: 0x00 */
678 /* E-MSC 1st Interrupt, default value: 0x00 */
686 #define BIT_EMSCINTR_EMSC_XMIT_GNT_TOUT BIT(1)
689 /* E-MSC Interrupt Mask, default value: 0x00 */
692 /* I2C E-MSC XMIT FIFO Write Port, default value: 0x00 */
695 /* I2C E-MSC RCV FIFO Write Port, default value: 0x00 */
698 /* E-MSC 2nd Interrupt, default value: 0x00 */
702 /* E-MSC Interrupt Mask, default value: 0x00 */
712 /* MHL DataPath 1st Ctl, default value: 0xbc */
748 /* MHL PLL 1st Ctl, default value: 0x05 */
768 #define BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL BIT(1)
778 /* MHL CBUS 1st Ctl, default value: 0x12 */
803 /* MHL CoC 1st Ctl, default value: 0xc3 */
826 /* MHL DoC 1st Ctl, default value: 0x18 */
839 #define BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN BIT(1)
870 #define BIT_HDCP2X_POLL_CS_HDCP2X_DIS_POLL_GNT BIT(1)
887 #define BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX BIT(1)
890 /* HDCP General Control 1, default value: 0x08 */
895 #define BIT_HDCP2X_CTRL_1_HDCP2X_CTL3MSK BIT(1)
903 #define BIT_HDCP2X_MISC_CTRL_HDCP2X_RPT_RCVID_RD_START BIT(1)
937 #define BIT_M3_CTRL_ENC_TMDS BIT(1)
952 #define BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED BIT(1)
964 /* HSIC Div Ctl, default value: 0x05 */
969 /* MHL Capability 1st Byte, default value: 0x00 */
972 /* MHL Interrupt 1st Byte, default value: 0x00 */
975 /* Device Status 1st byte, default value: 0x00 */
978 /* CBUS Scratch Pad 1st Byte, default value: 0x00 */
981 /* MHL Extended Capability 1st Byte, default value: 0x00 */
984 /* Device Extended Status 1st byte, default value: 0x00 */
1023 #define BIT_TPI_SC_DDC_TPI_SW BIT(1)
1037 #define BIT_TPI_COPP_DATA1_COPP_PROTYPE BIT(1)
1046 #define BIT_TPI_COPP_DATA2_DDC_SHORT_RI_RD BIT(1)
1059 #define BIT_TPI_INTR_ST0_READ_BKSV_BCAPS_ERR_STAT BIT(1)
1112 /* CoC 1st Ctl, default value: 0x40 */
1193 #define BIT_COC_CALIBRATION_DONE BIT(1)
1229 /* DoC 1st Ctl, default value: 0x40 */
1267 /* Interrupt Mask 1st, default value: 0x00 */
1292 #define BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_ALL BIT(1)
1306 #define BIT_MDT_XMIT_CTRL_XFIFO_CLR_ALL BIT(1)
1332 /* MDT Interrupt 1, default value: 0x00 */
1335 #define BIT_MDT_RCV_SM_ABORT_PKT_RCVD BIT(1)
1341 /* MDT Interrupt 1 Mask, default value: 0x00 */
1352 #define BIT_CBUS_STATUS_MHL_MODE BIT(1)
1355 /* CBUS Interrupt 1st, default value: 0x00 */
1363 #define BIT_CBUS_MSC_MT_DONE BIT(1)
1366 /* CBUS Interrupt Mask 1st, default value: 0x00 */
1374 #define BIT_CBUS_CEC_ABORT BIT(1)
1417 #define BIT_MSC_COMMAND_START_MSC_MSG BIT(1)
1453 #define BIT_CBUS3_CNVT_TEARCBUS_EN BIT(1)
1465 #define VAL_PUP_20K 1
1491 #define BIT_DISC_CTRL9_WAKE_PULSE_BYPASS BIT(1)
1524 #define BIT_MHL3_EST_INT BIT(1)