Lines Matching +full:0 +full:x8006
32 #define KEY_DDC_ACCS_DONE 0x02
33 #define DDC_NO_ACK 0x50
35 #define LT9611_4LANES 0
66 #define LT9611_PAGE_CONTROL 0xff
71 .range_min = 0,
72 .range_max = 0x85ff,
74 .selector_mask = 0xff,
75 .selector_shift = 0,
76 .window_start = 0,
77 .window_len = 0x100,
84 .max_register = 0xffff,
97 { 0x8106, 0x40 }, /* port A rx current */ in lt9611_mipi_input_analog()
98 { 0x810a, 0xfe }, /* port A ldo voltage set */ in lt9611_mipi_input_analog()
99 { 0x810b, 0xbf }, /* enable port A lprx */ in lt9611_mipi_input_analog()
100 { 0x8111, 0x40 }, /* port B rx current */ in lt9611_mipi_input_analog()
101 { 0x8115, 0xfe }, /* port B ldo voltage set */ in lt9611_mipi_input_analog()
102 { 0x8116, 0xbf }, /* enable port B lprx */ in lt9611_mipi_input_analog()
104 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */ in lt9611_mipi_input_analog()
105 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */ in lt9611_mipi_input_analog()
115 { 0x8300, LT9611_4LANES }, in lt9611_mipi_input_digital()
116 { 0x830a, 0x00 }, in lt9611_mipi_input_digital()
117 { 0x824f, 0x80 }, in lt9611_mipi_input_digital()
118 { 0x8250, 0x10 }, in lt9611_mipi_input_digital()
119 { 0x8302, 0x0a }, in lt9611_mipi_input_digital()
120 { 0x8306, 0x0a }, in lt9611_mipi_input_digital()
124 reg_cfg[1].def = 0x03; in lt9611_mipi_input_digital()
148 regmap_write(lt9611->regmap, 0x830d, (u8)(v_total / 256)); in lt9611_mipi_video_setup()
149 regmap_write(lt9611->regmap, 0x830e, (u8)(v_total % 256)); in lt9611_mipi_video_setup()
151 regmap_write(lt9611->regmap, 0x830f, (u8)(vactive / 256)); in lt9611_mipi_video_setup()
152 regmap_write(lt9611->regmap, 0x8310, (u8)(vactive % 256)); in lt9611_mipi_video_setup()
154 regmap_write(lt9611->regmap, 0x8311, (u8)(h_total / 256)); in lt9611_mipi_video_setup()
155 regmap_write(lt9611->regmap, 0x8312, (u8)(h_total % 256)); in lt9611_mipi_video_setup()
157 regmap_write(lt9611->regmap, 0x8313, (u8)(hactive / 256)); in lt9611_mipi_video_setup()
158 regmap_write(lt9611->regmap, 0x8314, (u8)(hactive % 256)); in lt9611_mipi_video_setup()
160 regmap_write(lt9611->regmap, 0x8315, (u8)(vsync_len % 256)); in lt9611_mipi_video_setup()
161 regmap_write(lt9611->regmap, 0x8316, (u8)(hsync_len % 256)); in lt9611_mipi_video_setup()
163 regmap_write(lt9611->regmap, 0x8317, (u8)(vfront_porch % 256)); in lt9611_mipi_video_setup()
165 regmap_write(lt9611->regmap, 0x8318, (u8)(vsync_porch % 256)); in lt9611_mipi_video_setup()
167 regmap_write(lt9611->regmap, 0x8319, (u8)(hfront_porch % 256)); in lt9611_mipi_video_setup()
169 regmap_write(lt9611->regmap, 0x831a, (u8)(hsync_porch / 256) | in lt9611_mipi_video_setup()
171 regmap_write(lt9611->regmap, 0x831b, (u8)(hsync_porch % 256)); in lt9611_mipi_video_setup()
178 { 0x830b, 0x01 }, in lt9611_pcr_setup()
179 { 0x830c, 0x10 }, in lt9611_pcr_setup()
180 { 0x8348, 0x00 }, in lt9611_pcr_setup()
181 { 0x8349, 0x81 }, in lt9611_pcr_setup()
184 { 0x8321, 0x4a }, in lt9611_pcr_setup()
185 { 0x8324, 0x71 }, in lt9611_pcr_setup()
186 { 0x8325, 0x30 }, in lt9611_pcr_setup()
187 { 0x832a, 0x01 }, in lt9611_pcr_setup()
190 { 0x834a, 0x40 }, in lt9611_pcr_setup()
193 { 0x832d, 0x38 }, in lt9611_pcr_setup()
194 { 0x8331, 0x08 }, in lt9611_pcr_setup()
196 u8 pol = 0x10; in lt9611_pcr_setup()
199 pol |= 0x2; in lt9611_pcr_setup()
201 pol |= 0x1; in lt9611_pcr_setup()
202 regmap_write(lt9611->regmap, 0x831d, pol); in lt9611_pcr_setup()
209 hact += 0x50; in lt9611_pcr_setup()
210 hact = min(hact, 0x3e0U); in lt9611_pcr_setup()
211 regmap_write(lt9611->regmap, 0x830b, hact / 256); in lt9611_pcr_setup()
212 regmap_write(lt9611->regmap, 0x830c, hact % 256); in lt9611_pcr_setup()
213 regmap_write(lt9611->regmap, 0x8348, hact / 256); in lt9611_pcr_setup()
214 regmap_write(lt9611->regmap, 0x8349, hact % 256); in lt9611_pcr_setup()
217 regmap_write(lt9611->regmap, 0x8326, pcr_m); in lt9611_pcr_setup()
220 regmap_write(lt9611->regmap, 0x8011, 0x5a); in lt9611_pcr_setup()
221 regmap_write(lt9611->regmap, 0x8011, 0xfa); in lt9611_pcr_setup()
229 { 0x8123, 0x40 }, in lt9611_pll_setup()
230 { 0x8124, 0x64 }, in lt9611_pll_setup()
231 { 0x8125, 0x80 }, in lt9611_pll_setup()
232 { 0x8126, 0x55 }, in lt9611_pll_setup()
233 { 0x812c, 0x37 }, in lt9611_pll_setup()
234 { 0x812f, 0x01 }, in lt9611_pll_setup()
235 { 0x8126, 0x55 }, in lt9611_pll_setup()
236 { 0x8127, 0x66 }, in lt9611_pll_setup()
237 { 0x8128, 0x88 }, in lt9611_pll_setup()
238 { 0x812a, 0x20 }, in lt9611_pll_setup()
244 regmap_write(lt9611->regmap, 0x812d, 0x88); in lt9611_pll_setup()
247 regmap_write(lt9611->regmap, 0x812d, 0x99); in lt9611_pll_setup()
250 regmap_write(lt9611->regmap, 0x812d, 0xaa); in lt9611_pll_setup()
258 * - write remainder to 7:0 bits, which means shift by 1 in lt9611_pll_setup()
260 regmap_write(lt9611->regmap, 0x82e3, pclk >> 17); /* pclk[19:16] */ in lt9611_pll_setup()
261 regmap_write(lt9611->regmap, 0x82e4, pclk >> 9); /* pclk[15:8] */ in lt9611_pll_setup()
262 regmap_write(lt9611->regmap, 0x82e5, pclk >> 1); /* pclk[7:0] */ in lt9611_pll_setup()
264 regmap_write(lt9611->regmap, 0x82de, 0x20); in lt9611_pll_setup()
265 regmap_write(lt9611->regmap, 0x82de, 0xe0); in lt9611_pll_setup()
267 regmap_write(lt9611->regmap, 0x8016, 0xf1); in lt9611_pll_setup()
268 regmap_write(lt9611->regmap, 0x8016, 0xf3); in lt9611_pll_setup()
270 return 0; in lt9611_pll_setup()
297 temp = lt9611_read_video_check(lt9611, 0x8282); in lt9611_video_check()
298 if (temp < 0) in lt9611_video_check()
303 temp = lt9611_read_video_check(lt9611, 0x826c); in lt9611_video_check()
304 if (temp < 0) in lt9611_video_check()
309 temp = lt9611_read_video_check(lt9611, 0x8286); in lt9611_video_check()
310 if (temp < 0) in lt9611_video_check()
315 temp = lt9611_read_video_check(lt9611, 0x8382); in lt9611_video_check()
316 if (temp < 0) in lt9611_video_check()
321 temp = lt9611_read_video_check(lt9611, 0x8386); in lt9611_video_check()
322 if (temp < 0) in lt9611_video_check()
330 return 0; in lt9611_video_check()
340 regmap_write(lt9611->regmap, 0x82d6, 0x8c); in lt9611_hdmi_tx_digital()
342 regmap_write(lt9611->regmap, 0x82d6, 0x0c); in lt9611_hdmi_tx_digital()
343 regmap_write(lt9611->regmap, 0x82d7, 0x04); in lt9611_hdmi_tx_digital()
349 { 0x8130, 0x6a }, in lt9611_hdmi_tx_phy()
350 { 0x8131, 0x44 }, /* HDMI DC mode */ in lt9611_hdmi_tx_phy()
351 { 0x8132, 0x4a }, in lt9611_hdmi_tx_phy()
352 { 0x8133, 0x0b }, in lt9611_hdmi_tx_phy()
353 { 0x8134, 0x00 }, in lt9611_hdmi_tx_phy()
354 { 0x8135, 0x00 }, in lt9611_hdmi_tx_phy()
355 { 0x8136, 0x00 }, in lt9611_hdmi_tx_phy()
356 { 0x8137, 0x44 }, in lt9611_hdmi_tx_phy()
357 { 0x813f, 0x0f }, in lt9611_hdmi_tx_phy()
358 { 0x8140, 0xa0 }, in lt9611_hdmi_tx_phy()
359 { 0x8141, 0xa0 }, in lt9611_hdmi_tx_phy()
360 { 0x8142, 0xa0 }, in lt9611_hdmi_tx_phy()
361 { 0x8143, 0xa0 }, in lt9611_hdmi_tx_phy()
362 { 0x8144, 0x0a }, in lt9611_hdmi_tx_phy()
367 reg_cfg[2].def = 0x73; in lt9611_hdmi_tx_phy()
375 unsigned int irq_flag0 = 0; in lt9611_irq_thread_handler()
376 unsigned int irq_flag3 = 0; in lt9611_irq_thread_handler()
378 regmap_read(lt9611->regmap, 0x820f, &irq_flag3); in lt9611_irq_thread_handler()
379 regmap_read(lt9611->regmap, 0x820c, &irq_flag0); in lt9611_irq_thread_handler()
382 if (irq_flag3 & 0x80) { in lt9611_irq_thread_handler()
385 regmap_write(lt9611->regmap, 0x8207, 0xbf); in lt9611_irq_thread_handler()
386 regmap_write(lt9611->regmap, 0x8207, 0x3f); in lt9611_irq_thread_handler()
390 if (irq_flag3 & 0x40) { in lt9611_irq_thread_handler()
393 regmap_write(lt9611->regmap, 0x8207, 0x7f); in lt9611_irq_thread_handler()
394 regmap_write(lt9611->regmap, 0x8207, 0x3f); in lt9611_irq_thread_handler()
397 if (irq_flag3 & 0xc0 && lt9611->bridge.dev) in lt9611_irq_thread_handler()
401 if (irq_flag0 & 0x01) { in lt9611_irq_thread_handler()
403 regmap_write(lt9611->regmap, 0x829e, 0xff); in lt9611_irq_thread_handler()
404 regmap_write(lt9611->regmap, 0x829e, 0xf7); in lt9611_irq_thread_handler()
405 regmap_write(lt9611->regmap, 0x8204, 0xff); in lt9611_irq_thread_handler()
406 regmap_write(lt9611->regmap, 0x8204, 0xfe); in lt9611_irq_thread_handler()
416 regmap_read(lt9611->regmap, 0x8203, &val); in lt9611_enable_hpd_interrupts()
418 val &= ~0xc0; in lt9611_enable_hpd_interrupts()
419 regmap_write(lt9611->regmap, 0x8203, val); in lt9611_enable_hpd_interrupts()
420 regmap_write(lt9611->regmap, 0x8207, 0xff); /* clear */ in lt9611_enable_hpd_interrupts()
421 regmap_write(lt9611->regmap, 0x8207, 0x3f); in lt9611_enable_hpd_interrupts()
427 { 0x8024, 0x76 }, in lt9611_sleep_setup()
428 { 0x8023, 0x01 }, in lt9611_sleep_setup()
429 { 0x8157, 0x03 }, /* set addr pin as output */ in lt9611_sleep_setup()
430 { 0x8149, 0x0b }, in lt9611_sleep_setup()
432 { 0x8102, 0x48 }, /* MIPI Rx power down */ in lt9611_sleep_setup()
433 { 0x8123, 0x80 }, in lt9611_sleep_setup()
434 { 0x8130, 0x00 }, in lt9611_sleep_setup()
435 { 0x8011, 0x0a }, in lt9611_sleep_setup()
448 { 0x8101, 0x18 }, /* sel xtal clock */ in lt9611_power_on()
451 { 0x821b, 0x69 }, /* timer 2 */ in lt9611_power_on()
452 { 0x821c, 0x78 }, in lt9611_power_on()
453 { 0x82cb, 0x69 }, /* timer 1 */ in lt9611_power_on()
454 { 0x82cc, 0x78 }, in lt9611_power_on()
457 { 0x8251, 0x01 }, in lt9611_power_on()
458 { 0x8258, 0x0a }, /* hpd irq */ in lt9611_power_on()
459 { 0x8259, 0x80 }, /* hpd debounce width */ in lt9611_power_on()
460 { 0x829e, 0xf7 }, /* video check irq */ in lt9611_power_on()
463 { 0x8004, 0xf0 }, in lt9611_power_on()
464 { 0x8006, 0xf0 }, in lt9611_power_on()
465 { 0x800a, 0x80 }, in lt9611_power_on()
466 { 0x800b, 0x40 }, in lt9611_power_on()
467 { 0x800d, 0xef }, in lt9611_power_on()
468 { 0x8011, 0xfa }, in lt9611_power_on()
472 return 0; in lt9611_power_on()
485 ret = regmap_write(lt9611->regmap, 0x8130, 0x6a); in lt9611_power_off()
497 gpiod_set_value_cansleep(lt9611->reset_gpio, 0); in lt9611_reset()
517 lt9611->supplies[0].supply = "vdd"; in lt9611_regulator_init()
521 if (ret < 0) in lt9611_regulator_init()
524 return regulator_set_load(lt9611->supplies[0].consumer, 300000); in lt9611_regulator_init()
531 ret = regulator_enable(lt9611->supplies[0].consumer); in lt9611_regulator_enable()
532 if (ret < 0) in lt9611_regulator_enable()
538 if (ret < 0) { in lt9611_regulator_enable()
539 regulator_disable(lt9611->supplies[0].consumer); in lt9611_regulator_enable()
543 return 0; in lt9611_regulator_enable()
549 unsigned int reg_val = 0; in lt9611_bridge_detect()
550 int connected = 0; in lt9611_bridge_detect()
552 regmap_read(lt9611->regmap, 0x825e, ®_val); in lt9611_bridge_detect()
553 connected = (reg_val & (BIT(2) | BIT(0))); in lt9611_bridge_detect()
564 int ret = 0; in lt9611_read_edid()
568 memset(lt9611->edid_buf, 0, sizeof(lt9611->edid_buf)); in lt9611_read_edid()
570 regmap_write(lt9611->regmap, 0x8503, 0xc9); in lt9611_read_edid()
572 /* 0xA0 is EDID device address */ in lt9611_read_edid()
573 regmap_write(lt9611->regmap, 0x8504, 0xa0); in lt9611_read_edid()
574 /* 0x00 is EDID offset address */ in lt9611_read_edid()
575 regmap_write(lt9611->regmap, 0x8505, 0x00); in lt9611_read_edid()
578 regmap_write(lt9611->regmap, 0x8506, EDID_LEN); in lt9611_read_edid()
579 regmap_write(lt9611->regmap, 0x8514, 0x7f); in lt9611_read_edid()
581 for (i = 0; i < EDID_LOOP; i++) { in lt9611_read_edid()
583 regmap_write(lt9611->regmap, 0x8505, i * EDID_LEN); in lt9611_read_edid()
584 regmap_write(lt9611->regmap, 0x8507, 0x36); in lt9611_read_edid()
585 regmap_write(lt9611->regmap, 0x8507, 0x31); in lt9611_read_edid()
586 regmap_write(lt9611->regmap, 0x8507, 0x37); in lt9611_read_edid()
589 regmap_read(lt9611->regmap, 0x8540, &temp); in lt9611_read_edid()
592 for (j = 0; j < EDID_LEN; j++) { in lt9611_read_edid()
593 regmap_read(lt9611->regmap, 0x8583, &temp); in lt9611_read_edid()
610 regmap_write(lt9611->regmap, 0x8507, 0x1f); in lt9611_read_edid()
628 if (block == 0) { in lt9611_get_edid_block()
639 return 0; in lt9611_get_edid_block()
689 regmap_write(lt9611->regmap, 0x8130, 0xea); in lt9611_bridge_atomic_enable()
700 ret = regmap_write(lt9611->regmap, 0x8130, 0x6a); in lt9611_bridge_atomic_disable()
715 const struct mipi_dsi_device_info info = { "lt9611", 0, lt9611->dev->of_node}; in lt9611_attach_dsi()
737 if (ret < 0) { in lt9611_attach_dsi()
774 { 0x8102, 0x12 }, in lt9611_bridge_atomic_pre_enable()
775 { 0x8123, 0x40 }, in lt9611_bridge_atomic_pre_enable()
776 { 0x8130, 0xea }, in lt9611_bridge_atomic_pre_enable()
777 { 0x8011, 0xfa }, in lt9611_bridge_atomic_pre_enable()
826 *num_input_fmts = 0; in lt9611_atomic_get_input_bus_fmts()
834 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; in lt9611_atomic_get_input_bus_fmts()
842 * - 0x01, 0x84df
843 * - 0x04, 0x84c0
845 #define LT9611_INFOFRAME_AUDIO 0x02
846 #define LT9611_INFOFRAME_AVI 0x08
847 #define LT9611_INFOFRAME_SPD 0x10
848 #define LT9611_INFOFRAME_VENDOR 0x20
875 mask = 0; in lt9611_hdmi_clear_infoframe()
880 regmap_update_bits(lt9611->regmap, 0x843d, mask, 0); in lt9611_hdmi_clear_infoframe()
882 return 0; in lt9611_hdmi_clear_infoframe()
896 addr = 0x84b2; in lt9611_hdmi_write_infoframe()
901 addr = 0x8440; in lt9611_hdmi_write_infoframe()
906 addr = 0x8493; in lt9611_hdmi_write_infoframe()
911 addr = 0x8474; in lt9611_hdmi_write_infoframe()
916 mask = 0; in lt9611_hdmi_write_infoframe()
921 for (i = 0; i < len; i++) in lt9611_hdmi_write_infoframe()
924 regmap_update_bits(lt9611->regmap, 0x843d, mask, mask); in lt9611_hdmi_write_infoframe()
927 return 0; in lt9611_hdmi_write_infoframe()
947 regmap_write(lt9611->regmap, 0x82d6, 0x8c); in lt9611_hdmi_audio_startup()
948 regmap_write(lt9611->regmap, 0x82d7, 0x04); in lt9611_hdmi_audio_startup()
950 regmap_write(lt9611->regmap, 0x8406, 0x08); in lt9611_hdmi_audio_startup()
951 regmap_write(lt9611->regmap, 0x8407, 0x10); in lt9611_hdmi_audio_startup()
953 regmap_write(lt9611->regmap, 0x8434, 0xd5); in lt9611_hdmi_audio_startup()
955 return 0; in lt9611_hdmi_audio_startup()
966 regmap_write(lt9611->regmap, 0x840f, 0x2b); in lt9611_hdmi_audio_prepare()
968 regmap_write(lt9611->regmap, 0x840f, 0xab); in lt9611_hdmi_audio_prepare()
972 regmap_write(lt9611->regmap, 0x8435, 0x00); in lt9611_hdmi_audio_prepare()
973 regmap_write(lt9611->regmap, 0x8436, 0x18); in lt9611_hdmi_audio_prepare()
974 regmap_write(lt9611->regmap, 0x8437, 0x00); in lt9611_hdmi_audio_prepare()
987 regmap_write(lt9611->regmap, 0x8406, 0x00); in lt9611_hdmi_audio_shutdown()
988 regmap_write(lt9611->regmap, 0x8407, 0x00); in lt9611_hdmi_audio_shutdown()
1019 lt9611->dsi0_node = of_graph_get_remote_node(dev->of_node, 0, -1); in lt9611_parse_dt()
1049 return 0; in lt9611_gpio_init()
1057 regmap_write(lt9611->regmap, 0x80ee, 0x01); in lt9611_read_device_rev()
1058 ret = regmap_read(lt9611->regmap, 0x8002, &rev); in lt9611_read_device_rev()
1062 dev_info(lt9611->dev, "LT9611 revision: 0x%x\n", rev); in lt9611_read_device_rev()
1099 if (ret < 0) in lt9611_probe()
1103 if (ret < 0) in lt9611_probe()
1131 regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AUDIO, 0); in lt9611_probe()
1165 return 0; in lt9611_probe()