1 // SPDX-License-Identifier: GPL-2.0+
28 	if (mode->clock < 13500)  in imx8mp_hdmi_mode_valid()
31 	if (mode->clock > 297000)  in imx8mp_hdmi_mode_valid()
34 	round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000);  in imx8mp_hdmi_mode_valid()
35 	/* imx8mp's pixel clock generator (fsl-samsung-hdmi) cannot generate  in imx8mp_hdmi_mode_valid()
39 	 * 0.5% = 5/1000 tolerance (mode->clock is 1/1000)  in imx8mp_hdmi_mode_valid()
41 	if (abs(round_rate - mode->clock * 1000) > mode->clock * 5)  in imx8mp_hdmi_mode_valid()
44 	/* We don't support double-clocked and Interlaced modes */  in imx8mp_hdmi_mode_valid()
45 	if ((mode->flags & DRM_MODE_FLAG_DBLCLK) ||  in imx8mp_hdmi_mode_valid()
46 	    (mode->flags & DRM_MODE_FLAG_INTERLACE))  in imx8mp_hdmi_mode_valid()
66 	 * Just release PHY core from reset, all other power management is done  in im8mp_hdmi_phy_setup_hpd()
84 	struct device *dev = &pdev->dev;  in imx8mp_dw_hdmi_probe()
90 		return -ENOMEM;  in imx8mp_dw_hdmi_probe()
92 	plat_data = &hdmi->plat_data;  in imx8mp_dw_hdmi_probe()
94 	hdmi->pixclk = devm_clk_get(dev, "pix");  in imx8mp_dw_hdmi_probe()
95 	if (IS_ERR(hdmi->pixclk))  in imx8mp_dw_hdmi_probe()
96 		return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),  in imx8mp_dw_hdmi_probe()
99 	plat_data->mode_valid = imx8mp_hdmi_mode_valid;  in imx8mp_dw_hdmi_probe()
100 	plat_data->phy_ops = &imx8mp_hdmi_phy_ops;  in imx8mp_dw_hdmi_probe()
101 	plat_data->phy_name = "SAMSUNG HDMI TX PHY";  in imx8mp_dw_hdmi_probe()
102 	plat_data->priv_data = hdmi;  in imx8mp_dw_hdmi_probe()
103 	plat_data->phy_force_vendor = true;  in imx8mp_dw_hdmi_probe()
105 	hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);  in imx8mp_dw_hdmi_probe()
106 	if (IS_ERR(hdmi->dw_hdmi))  in imx8mp_dw_hdmi_probe()
107 		return PTR_ERR(hdmi->dw_hdmi);  in imx8mp_dw_hdmi_probe()
118 	dw_hdmi_remove(hdmi->dw_hdmi);  in imx8mp_dw_hdmi_remove()
130 	dw_hdmi_resume(hdmi->dw_hdmi);  in imx8mp_dw_hdmi_pm_resume()
140 	{ .compatible = "fsl,imx8mp-hdmi-tx" },
149 		.name	= "imx8mp-dw-hdmi-tx",