Lines Matching +full:0 +full:x2c
39 .regs_offset = 0x40,
40 .id = 0,
42 .cfgs_offset = 0x2c,
48 .clut_offset = 0x400,
53 .min_width = 0,
54 .min_height = 0,
57 .max_spw = 0x3f,
58 .max_vpw = 0x3f,
59 .max_hpw = 0xff,
70 .regs_offset = 0x40,
71 .id = 0,
73 .cfgs_offset = 0x2c,
81 .clut_offset = 0x400,
86 .regs_offset = 0x100,
89 .cfgs_offset = 0x2c,
100 .clut_offset = 0x800,
105 .regs_offset = 0x280,
108 .cfgs_offset = 0x4c,
122 .clut_offset = 0x1000,
127 .regs_offset = 0x340,
132 .cfgs_offset = 0x2c,
142 .clut_offset = 0x1400,
147 .min_width = 0,
148 .min_height = 0,
151 .max_spw = 0x3f,
152 .max_vpw = 0x3f,
153 .max_hpw = 0xff,
164 .regs_offset = 0x40,
165 .id = 0,
167 .cfgs_offset = 0x2c,
175 .clut_offset = 0x600,
180 .regs_offset = 0x140,
183 .cfgs_offset = 0x2c,
194 .clut_offset = 0xa00,
199 .regs_offset = 0x240,
202 .cfgs_offset = 0x2c,
213 .clut_offset = 0xe00,
218 .regs_offset = 0x340,
221 .cfgs_offset = 0x4c,
239 .clut_offset = 0x1200,
244 .regs_offset = 0x440,
249 .cfgs_offset = 0x2c,
261 .clut_offset = 0x1600,
266 .min_width = 0,
267 .min_height = 0,
270 .max_spw = 0x3f,
271 .max_vpw = 0x3f,
272 .max_hpw = 0x1ff,
283 .regs_offset = 0x40,
284 .id = 0,
286 .cfgs_offset = 0x2c,
294 .clut_offset = 0x600,
299 .regs_offset = 0x140,
302 .cfgs_offset = 0x2c,
313 .clut_offset = 0xa00,
318 .regs_offset = 0x240,
321 .cfgs_offset = 0x2c,
332 .clut_offset = 0xe00,
337 .regs_offset = 0x340,
340 .cfgs_offset = 0x4c,
358 .clut_offset = 0x1200,
363 .min_width = 0,
364 .min_height = 0,
367 .max_spw = 0xff,
368 .max_vpw = 0xff,
369 .max_hpw = 0x3ff,
379 .regs_offset = 0x60,
380 .id = 0,
382 .cfgs_offset = 0x2c,
390 .clut_offset = 0x600,
395 .regs_offset = 0x160,
398 .cfgs_offset = 0x2c,
409 .clut_offset = 0xa00,
414 .regs_offset = 0x260,
417 .cfgs_offset = 0x2c,
428 .clut_offset = 0xe00,
433 .regs_offset = 0x360,
436 .cfgs_offset = 0x4c,
454 .clut_offset = 0x1200,
459 .min_width = 0,
460 .min_height = 0,
463 .max_spw = 0xff,
464 .max_vpw = 0xff,
465 .max_hpw = 0x3ff,
476 .regs_offset = 0x60,
477 .id = 0,
479 .cfgs_offset = 0x1c,
487 .clut_offset = 0x700,
492 .regs_offset = 0x160,
495 .cfgs_offset = 0x1c,
506 .clut_offset = 0xb00,
511 .regs_offset = 0x260,
514 .cfgs_offset = 0x1c,
525 .clut_offset = 0xf00,
530 .regs_offset = 0x360,
533 .cfgs_offset = 0x30,
549 .clut_offset = 0x1300,
554 .min_width = 0,
555 .min_height = 0,
558 .max_spw = 0x3ff,
559 .max_vpw = 0x3ff,
560 .max_hpw = 0x3ff,
624 vback_porch > dc->desc->max_vpw || vback_porch < 0 || in atmel_hlcdc_dc_mode_valid()
659 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) { in atmel_hlcdc_dc_irq_handler()
670 unsigned int cfg = 0; in atmel_hlcdc_dc_irq_postinstall()
674 for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) { in atmel_hlcdc_dc_irq_postinstall()
687 regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff); in atmel_hlcdc_dc_irq_disable()
697 ret = devm_request_irq(dev->dev, irq, atmel_hlcdc_dc_irq_handler, 0, in atmel_hlcdc_dc_irq_install()
704 return 0; in atmel_hlcdc_dc_irq_install()
750 return 0; in atmel_hlcdc_dc_modeset_init()
788 if (ret < 0) { in atmel_hlcdc_dc_load()
794 if (ret < 0) { in atmel_hlcdc_dc_load()
804 if (ret < 0) { in atmel_hlcdc_dc_load()
813 return 0; in atmel_hlcdc_dc_load()
850 .minor = 0,
866 ret = drm_dev_register(ddev, 0); in atmel_hlcdc_dc_drm_probe()
872 return 0; in atmel_hlcdc_dc_drm_probe()
914 return 0; in atmel_hlcdc_dc_drm_suspend()