Lines Matching full:indirect
515 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_mc_resume_dpg_mode() argument
522 if (!indirect) { in vcn_v2_5_mc_resume_dpg_mode()
525 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
528 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
530 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
533 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
535 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
537 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
543 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
546 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
550 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
553 if (!indirect) in vcn_v2_5_mc_resume_dpg_mode()
555 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
558 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
561 if (!indirect) { in vcn_v2_5_mc_resume_dpg_mode()
564 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
567 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
569 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
572 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
574 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
576 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
579 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
584 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
587 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
589 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
591 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
596 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
599 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
601 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
604 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
608 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
729 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v2_5_clock_gating_dpg_mode() argument
761 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
765 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
769 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
773 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
839 bool indirect) in vcn_v2_6_enable_ras() argument
852 tmp, 0, indirect); in vcn_v2_6_enable_ras()
857 tmp, 0, indirect); in vcn_v2_6_enable_ras()
862 tmp, 0, indirect); in vcn_v2_6_enable_ras()
865 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_start_dpg_mode() argument
880 if (indirect) in vcn_v2_5_start_dpg_mode()
884 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
891 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
895 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
907 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
911 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); in vcn_v2_5_start_dpg_mode()
918 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
925 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
931 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); in vcn_v2_5_start_dpg_mode()
933 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
936 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v2_5_start_dpg_mode()
938 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v2_5_start_dpg_mode()
942 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
944 vcn_v2_6_enable_ras(adev, inst_idx, indirect); in vcn_v2_5_start_dpg_mode()
948 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
953 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
958 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); in vcn_v2_5_start_dpg_mode()
960 if (indirect) in vcn_v2_5_start_dpg_mode()