Lines Matching +full:5 +full:x
61 #define PACKETJ_CONDITION_CHECK5 5
70 #define PACKETJ_TYPE5 5
80 #define CP_PACKETJ_GET_REG(x) ((x) & 0x3FFFF) argument
81 #define CP_PACKETJ_GET_RES(x) (((x) >> 18) & 0x3F) argument
82 #define CP_PACKETJ_GET_COND(x) (((x) >> 24) & 0xF) argument
83 #define CP_PACKETJ_GET_TYPE(x) (((x) >> 28) & 0xF) argument
88 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
116 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
122 * 5 - memory (async - direct)
126 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) argument
130 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
142 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
148 * 5 - >=
151 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
155 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) argument
159 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
165 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) argument
170 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) argument
171 #define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) argument
176 #define EVENT_TYPE(x) ((x) << 0) argument
177 #define EVENT_INDEX(x) ((x) << 8) argument
185 #define EVENT_TYPE(x) ((x) << 0) argument
186 #define EVENT_INDEX(x) ((x) << 8) argument
196 #define DATA_SEL(x) ((x) << 29) argument
203 #define INT_SEL(x) ((x) << 24) argument
208 #define DST_SEL(x) ((x) << 16) argument
223 * 5. DST_ADDR_LO [31:0]
228 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) argument
232 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) argument
236 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) argument
241 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) argument
245 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) argument
270 * 5. COHER_BASE_LO [31:0]
275 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_NC_ACTION_ENA(x) ((x) << 3) argument
276 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WC_ACTION_ENA(x) ((x) << 4) argument
277 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_INV_METADATA_ACTION_ENA(x) ((x) << 5) argument
278 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_VOL_ACTION_ENA(x) ((x) << 15) argument
279 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(x) ((x) << 18) argument
280 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(x) ((x) << 22) argument
281 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(x) ((x) << 23) argument
282 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_CB_ACTION_ENA(x) ((x) << 25) argument
283 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_DB_ACTION_ENA(x) ((x) << 26) argument
284 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(x) ((x) << 27) argument
285 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_VOL_ACTION_ENA(x) ((x) << 28) argument
286 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(x) ((x) << 29) argument
287 #define PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_WB_ACTION_ENA(x) ((x) << 30) argument
321 # define FRAME_CMD(x) ((x) << 28) argument
323 * x=0: tmz_begin
324 * x=1: tmz_end
328 # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) argument
329 # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) argument
330 # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) argument
331 # define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) argument
337 * 5. GWS_MASK_LO [31:0]
340 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
342 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) argument
343 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) argument
344 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) argument
350 * 5. MQD_ADDR_HI [31:0]
355 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
356 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) argument
357 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) argument
358 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) argument
359 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) argument
360 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) argument
361 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) argument
362 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
363 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
365 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) argument
366 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) argument
372 * 5. CONTROL4
376 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) argument
382 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) argument
383 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) argument
384 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) argument
386 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) argument
388 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) argument
390 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) argument
392 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) argument
394 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) argument
396 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) argument
402 * 5. ADDR_HI [31:0]
407 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) argument
408 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) argument
409 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) argument
411 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) argument
413 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) argument
414 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) argument