Lines Matching +full:sdma +full:- +full:event +full:- +full:remap
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
204 return -EINVAL; in soc15_query_video_codecs()
236 return -EINVAL; in soc15_query_video_codecs()
249 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
252 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
263 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
266 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
277 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
280 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
291 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
294 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
302 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
305 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
313 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
316 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
324 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
327 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
335 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
338 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
343 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
348 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
410 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
418 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
430 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
432 return adev->gfx.config.db_debug2; in soc15_get_register_value()
446 if (!adev->reg_offset[en->hwip][en->inst]) in soc15_read_register()
448 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
449 + en->reg_offset)) in soc15_read_register()
457 return -EINVAL; in soc15_read_register()
462 * soc15_program_register_sequence - program an array of registers.
482 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
484 if (entry->and_mask == 0xffffffff) { in soc15_program_register_sequence()
485 tmp = entry->or_mask; in soc15_program_register_sequence()
487 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
490 tmp &= ~(entry->and_mask); in soc15_program_register_sequence()
491 tmp |= (entry->or_mask & entry->and_mask); in soc15_program_register_sequence()
500 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
513 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
514 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
520 /* re-enable doorbell interrupt after BACO exit */ in soc15_asic_baco_reset()
521 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
522 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
534 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) in soc15_asic_reset_method()
547 if (amdgpu_reset_method != -1) in soc15_asic_reset_method()
548 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc15_asic_reset_method()
559 if (adev->asic_type == CHIP_VEGA20) { in soc15_asic_reset_method()
560 if (adev->psp.sos.fw_version >= 0x80067) in soc15_asic_reset_method()
566 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
567 adev->pm.fw_version <= 0x283400) in soc15_asic_reset_method()
590 else if (!(adev->flags & AMD_IS_APU)) in soc15_asic_reset_method()
611 if (adev->flags & AMD_IS_APU && adev->in_s3 && in soc15_need_reset_on_resume()
626 if ((adev->apu_flags & AMD_APU_IS_PICASSO || in soc15_asic_reset()
627 !(adev->apu_flags & AMD_APU_IS_RAVEN)) && in soc15_asic_reset()
631 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || in soc15_asic_reset()
632 (adev->apu_flags & AMD_APU_IS_RAVEN2)) in soc15_asic_reset()
638 dev_info(adev->dev, "PCI reset\n"); in soc15_asic_reset()
641 dev_info(adev->dev, "BACO reset\n"); in soc15_asic_reset()
644 dev_info(adev->dev, "MODE2 reset\n"); in soc15_asic_reset()
647 dev_info(adev->dev, "MODE1 reset\n"); in soc15_asic_reset()
657 if (adev->asic_type == CHIP_VEGA20) { in soc15_supports_baco()
658 if (adev->psp.sos.fw_version >= 0x80067) in soc15_supports_baco()
701 if (adev->nbio.funcs->program_aspm) in soc15_program_aspm()
702 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
717 switch (adev->asic_type) { in soc15_reg_base_init()
734 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); in soc15_reg_base_init()
741 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_virt_ops()
765 if (adev->flags & AMD_IS_APU) in soc15_get_pcie_usage()
812 if (adev->flags & AMD_IS_APU) in vega20_get_pcie_usage()
856 if (adev->asic_type == CHIP_RENOIR) in soc15_need_reset_on_init()
869 if (adev->flags & AMD_IS_APU) in soc15_need_reset_on_init()
965 struct amdgpu_device *adev = ip_block->adev; in soc15_common_early_init()
967 adev->nbio.funcs->set_reg_remap(adev); in soc15_common_early_init()
968 adev->smc_rreg = NULL; in soc15_common_early_init()
969 adev->smc_wreg = NULL; in soc15_common_early_init()
970 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in soc15_common_early_init()
971 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in soc15_common_early_init()
972 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; in soc15_common_early_init()
973 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; in soc15_common_early_init()
974 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in soc15_common_early_init()
975 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in soc15_common_early_init()
976 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; in soc15_common_early_init()
977 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; in soc15_common_early_init()
978 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
979 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
980 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
981 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
982 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
983 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
984 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
985 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
987 adev->rev_id = amdgpu_device_get_rev_id(adev); in soc15_common_early_init()
988 adev->external_rev_id = 0xFF; in soc15_common_early_init()
994 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
995 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1014 adev->pg_flags = 0; in soc15_common_early_init()
1015 adev->external_rev_id = 0x1; in soc15_common_early_init()
1018 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1019 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1037 adev->pg_flags = 0; in soc15_common_early_init()
1038 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1041 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1042 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1060 adev->pg_flags = 0; in soc15_common_early_init()
1061 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1065 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1067 if (adev->rev_id >= 0x8) in soc15_common_early_init()
1068 adev->apu_flags |= AMD_APU_IS_RAVEN2; in soc15_common_early_init()
1070 if (adev->apu_flags & AMD_APU_IS_RAVEN2) in soc15_common_early_init()
1071 adev->external_rev_id = adev->rev_id + 0x79; in soc15_common_early_init()
1072 else if (adev->apu_flags & AMD_APU_IS_PICASSO) in soc15_common_early_init()
1073 adev->external_rev_id = adev->rev_id + 0x41; in soc15_common_early_init()
1074 else if (adev->rev_id == 1) in soc15_common_early_init()
1075 adev->external_rev_id = adev->rev_id + 0x20; in soc15_common_early_init()
1077 adev->external_rev_id = adev->rev_id + 0x01; in soc15_common_early_init()
1079 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { in soc15_common_early_init()
1080 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1095 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1096 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { in soc15_common_early_init()
1097 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1115 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1118 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1137 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1141 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1142 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1156 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1157 adev->external_rev_id = adev->rev_id + 0x32; in soc15_common_early_init()
1160 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1162 if (adev->apu_flags & AMD_APU_IS_RENOIR) in soc15_common_early_init()
1163 adev->external_rev_id = adev->rev_id + 0x91; in soc15_common_early_init()
1165 adev->external_rev_id = adev->rev_id + 0xa1; in soc15_common_early_init()
1166 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1185 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1191 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1192 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1200 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1201 adev->external_rev_id = adev->rev_id + 0x3c; in soc15_common_early_init()
1206 adev->asic_funcs = &aqua_vanjaram_asic_funcs; in soc15_common_early_init()
1207 adev->cg_flags = in soc15_common_early_init()
1213 adev->pg_flags = in soc15_common_early_init()
1218 adev->external_rev_id = adev->rev_id + 0x46; in soc15_common_early_init()
1222 return -EINVAL; in soc15_common_early_init()
1235 struct amdgpu_device *adev = ip_block->adev; in soc15_common_late_init()
1243 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc15_common_late_init()
1250 struct amdgpu_device *adev = ip_block->adev; in soc15_common_sw_init()
1255 if (adev->df.funcs && in soc15_common_sw_init()
1256 adev->df.funcs->sw_init) in soc15_common_sw_init()
1257 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1264 struct amdgpu_device *adev = ip_block->adev; in soc15_common_sw_fini()
1266 if (adev->df.funcs && in soc15_common_sw_fini()
1267 adev->df.funcs->sw_fini) in soc15_common_sw_fini()
1268 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1276 /* sdma doorbell range is programed by hypervisor */ in soc15_sdma_doorbell_range_init()
1278 for (i = 0; i < adev->sdma.num_instances; i++) { in soc15_sdma_doorbell_range_init()
1279 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_sdma_doorbell_range_init()
1280 true, adev->doorbell_index.sdma_engine[i] << 1, in soc15_sdma_doorbell_range_init()
1281 adev->doorbell_index.sdma_doorbell_range); in soc15_sdma_doorbell_range_init()
1288 struct amdgpu_device *adev = ip_block->adev; in soc15_common_hw_init()
1293 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1294 /* remap HDP registers to a hole in mmio space, in soc15_common_hw_init()
1298 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1299 adev->nbio.funcs->remap_hdp_registers(adev); in soc15_common_hw_init()
1302 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
1305 * in SDMA/IH/MM/ACV range will be routed to CP. So in soc15_common_hw_init()
1306 * we need to init SDMA doorbell range prior in soc15_common_hw_init()
1317 struct amdgpu_device *adev = ip_block->adev; in soc15_common_hw_fini()
1324 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
1325 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in soc15_common_hw_fini()
1335 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && in soc15_common_hw_fini()
1336 adev->nbio.ras_if && in soc15_common_hw_fini()
1337 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { in soc15_common_hw_fini()
1338 if (adev->nbio.ras && in soc15_common_hw_fini()
1339 adev->nbio.ras->init_ras_controller_interrupt) in soc15_common_hw_fini()
1340 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); in soc15_common_hw_fini()
1341 if (adev->nbio.ras && in soc15_common_hw_fini()
1342 adev->nbio.ras->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
1343 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc15_common_hw_fini()
1356 struct amdgpu_device *adev = ip_block->adev; in soc15_common_resume()
1359 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); in soc15_common_resume()
1376 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
1405 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
1417 struct amdgpu_device *adev = ip_block->adev; in soc15_common_set_clockgating_state()
1426 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1428 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1430 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1436 adev->smuio.funcs->update_rom_clock_gating(adev, in soc15_common_set_clockgating_state()
1438 adev->df.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1444 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1446 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1448 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1457 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1474 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1475 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
1477 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1478 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1496 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1497 adev->smuio.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1499 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1500 adev->df.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()