Lines Matching full:nv
231 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
232 GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */
233 GFX_FW_TYPE_RLC_IRAM = 26, /* RLC_IRAM NV */
234 GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */
235 GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */
236 GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */
237 GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */
238 GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */
239 GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */
240 GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */
241 GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */
242 GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */
243 GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */
244 GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */
245 GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */
246 GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */
247 GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */
248 GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */
249 GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */
250 GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */
251 GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */
252 GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */
253 GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */
254 GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */
255 GFX_FW_TYPE_RLC_DRAM_BOOT = 48, /* RLC DRAM BOOT NV */
256 GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */
257 GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */
267 GFX_FW_TYPE_SE2_TAP_DELAYS = 65, /* SE2 TAP DELAYS NV */
268 GFX_FW_TYPE_SE3_TAP_DELAYS = 66, /* SE3 TAP DELAYS NV */