167 	uint32_t def, data;  in nbio_v6_1_update_medium_grain_clock_gating()  local
169 	def = data = RREG32_PCIE(smnCPM_CONTROL);  in nbio_v6_1_update_medium_grain_clock_gating()
171 		data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |  in nbio_v6_1_update_medium_grain_clock_gating()
179 		data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |  in nbio_v6_1_update_medium_grain_clock_gating()
188 	if (def != data)  in nbio_v6_1_update_medium_grain_clock_gating()
189 		WREG32_PCIE(smnCPM_CONTROL, data);  in nbio_v6_1_update_medium_grain_clock_gating()
195 	uint32_t def, data;  in nbio_v6_1_update_medium_grain_light_sleep()  local
197 	def = data = RREG32_PCIE(smnPCIE_CNTL2);  in nbio_v6_1_update_medium_grain_light_sleep()
199 		data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |  in nbio_v6_1_update_medium_grain_light_sleep()
203 		data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |  in nbio_v6_1_update_medium_grain_light_sleep()
208 	if (def != data)  in nbio_v6_1_update_medium_grain_light_sleep()
209 		WREG32_PCIE(smnPCIE_CNTL2, data);  in nbio_v6_1_update_medium_grain_light_sleep()
215 	int data;  in nbio_v6_1_get_clockgating_state()  local
218 	data = RREG32_PCIE(smnCPM_CONTROL);  in nbio_v6_1_get_clockgating_state()
219 	if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)  in nbio_v6_1_get_clockgating_state()
223 	data = RREG32_PCIE(smnPCIE_CNTL2);  in nbio_v6_1_get_clockgating_state()
224 	if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)  in nbio_v6_1_get_clockgating_state()
265 	uint32_t def, data;  in nbio_v6_1_init_registers()  local
267 	def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);  in nbio_v6_1_init_registers()
268 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);  in nbio_v6_1_init_registers()
269 	data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);  in nbio_v6_1_init_registers()
271 	if (def != data)  in nbio_v6_1_init_registers()
272 		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);  in nbio_v6_1_init_registers()
274 	def = data = RREG32_PCIE(smnPCIE_CI_CNTL);  in nbio_v6_1_init_registers()
275 	data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);  in nbio_v6_1_init_registers()
277 	if (def != data)  in nbio_v6_1_init_registers()
278 		WREG32_PCIE(smnPCIE_CI_CNTL, data);  in nbio_v6_1_init_registers()
284 	uint32_t def, data;  in nbio_v6_1_program_ltr()  local
288 	def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);  in nbio_v6_1_program_ltr()
289 	data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;  in nbio_v6_1_program_ltr()
290 	if (def != data)  in nbio_v6_1_program_ltr()
291 		WREG32_PCIE(smnRCC_BIF_STRAP2, data);  in nbio_v6_1_program_ltr()
293 	def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);  in nbio_v6_1_program_ltr()
294 	data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;  in nbio_v6_1_program_ltr()
295 	if (def != data)  in nbio_v6_1_program_ltr()
296 		WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);  in nbio_v6_1_program_ltr()
298 	def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);  in nbio_v6_1_program_ltr()
299 	data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;  in nbio_v6_1_program_ltr()
300 	if (def != data)  in nbio_v6_1_program_ltr()
301 		WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);  in nbio_v6_1_program_ltr()
308 	uint32_t def, data;  in nbio_v6_1_program_aspm()  local
310 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);  in nbio_v6_1_program_aspm()
311 	data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;  in nbio_v6_1_program_aspm()
312 	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;  in nbio_v6_1_program_aspm()
313 	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;  in nbio_v6_1_program_aspm()
314 	if (def != data)  in nbio_v6_1_program_aspm()
315 		WREG32_PCIE(smnPCIE_LC_CNTL, data);  in nbio_v6_1_program_aspm()
317 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);  in nbio_v6_1_program_aspm()
318 	data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;  in nbio_v6_1_program_aspm()
319 	if (def != data)  in nbio_v6_1_program_aspm()
320 		WREG32_PCIE(smnPCIE_LC_CNTL7, data);  in nbio_v6_1_program_aspm()
322 	def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);  in nbio_v6_1_program_aspm()
323 	data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;  in nbio_v6_1_program_aspm()
324 	if (def != data)  in nbio_v6_1_program_aspm()
325 		WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);  in nbio_v6_1_program_aspm()
327 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);  in nbio_v6_1_program_aspm()
328 	data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;  in nbio_v6_1_program_aspm()
329 	if (def != data)  in nbio_v6_1_program_aspm()
330 		WREG32_PCIE(smnPCIE_LC_CNTL3, data);  in nbio_v6_1_program_aspm()
332 	def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);  in nbio_v6_1_program_aspm()
333 	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;  in nbio_v6_1_program_aspm()
334 	data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;  in nbio_v6_1_program_aspm()
335 	if (def != data)  in nbio_v6_1_program_aspm()
336 		WREG32_PCIE(smnRCC_BIF_STRAP3, data);  in nbio_v6_1_program_aspm()
338 	def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);  in nbio_v6_1_program_aspm()
339 	data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;  in nbio_v6_1_program_aspm()
340 	if (def != data)  in nbio_v6_1_program_aspm()
341 		WREG32_PCIE(smnRCC_BIF_STRAP5, data);  in nbio_v6_1_program_aspm()
343 	def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);  in nbio_v6_1_program_aspm()
344 	data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;  in nbio_v6_1_program_aspm()
345 	if (def != data)  in nbio_v6_1_program_aspm()
346 		WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);  in nbio_v6_1_program_aspm()
350 	def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);  in nbio_v6_1_program_aspm()
351 	data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |  in nbio_v6_1_program_aspm()
353 	data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;  in nbio_v6_1_program_aspm()
354 	if (def != data)  in nbio_v6_1_program_aspm()
355 		WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);  in nbio_v6_1_program_aspm()
357 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);  in nbio_v6_1_program_aspm()
358 	data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |  in nbio_v6_1_program_aspm()
360 	if (def != data)  in nbio_v6_1_program_aspm()
361 		WREG32_PCIE(smnPCIE_LC_CNTL6, data);  in nbio_v6_1_program_aspm()
368 	def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);  in nbio_v6_1_program_aspm()
369 	data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;  in nbio_v6_1_program_aspm()
370 	data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;  in nbio_v6_1_program_aspm()
371 	if (def != data)  in nbio_v6_1_program_aspm()
372 		WREG32_PCIE(smnRCC_BIF_STRAP3, data);  in nbio_v6_1_program_aspm()
374 	def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);  in nbio_v6_1_program_aspm()
375 	data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;  in nbio_v6_1_program_aspm()
376 	if (def != data)  in nbio_v6_1_program_aspm()
377 		WREG32_PCIE(smnRCC_BIF_STRAP5, data);  in nbio_v6_1_program_aspm()
379 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL);  in nbio_v6_1_program_aspm()
380 	data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;  in nbio_v6_1_program_aspm()
381 	data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;  in nbio_v6_1_program_aspm()
382 	data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;  in nbio_v6_1_program_aspm()
383 	if (def != data)  in nbio_v6_1_program_aspm()
384 		WREG32_PCIE(smnPCIE_LC_CNTL, data);  in nbio_v6_1_program_aspm()
386 	def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);  in nbio_v6_1_program_aspm()
387 	data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;  in nbio_v6_1_program_aspm()
388 	if (def != data)  in nbio_v6_1_program_aspm()
389 		WREG32_PCIE(smnPCIE_LC_CNTL3, data);  in nbio_v6_1_program_aspm()