201 				adev->virt.req_init_data_ver = 0;  in xgpu_nv_send_access_requests_with_param()
204 				adev->virt.req_init_data_ver =  in xgpu_nv_send_access_requests_with_param()
208 				if (adev->virt.req_init_data_ver < 1)  in xgpu_nv_send_access_requests_with_param()
209 					adev->virt.req_init_data_ver = 1;  in xgpu_nv_send_access_requests_with_param()
215 			adev->virt.fw_reserve.checksum_key =  in xgpu_nv_send_access_requests_with_param()
318 	struct amdgpu_virt *virt = container_of(work, struct amdgpu_virt, flr_work);  in xgpu_nv_mailbox_flr_work()  local
319 	struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt);  in xgpu_nv_mailbox_flr_work()
369 				   &adev->virt.flr_work),  in xgpu_nv_mailbox_rcv_irq()
399 	adev->virt.ack_irq.num_types = 1;  in xgpu_nv_mailbox_set_irq_funcs()
400 	adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs;  in xgpu_nv_mailbox_set_irq_funcs()
401 	adev->virt.rcv_irq.num_types = 1;  in xgpu_nv_mailbox_set_irq_funcs()
402 	adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs;  in xgpu_nv_mailbox_set_irq_funcs()
409 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq);  in xgpu_nv_mailbox_add_irq_id()
413 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq);  in xgpu_nv_mailbox_add_irq_id()
415 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_nv_mailbox_add_irq_id()
426 	r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0);  in xgpu_nv_mailbox_get_irq()
429 	r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0);  in xgpu_nv_mailbox_get_irq()
431 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_nv_mailbox_get_irq()
435 	INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work);  in xgpu_nv_mailbox_get_irq()
442 	amdgpu_irq_put(adev, &adev->virt.ack_irq, 0);  in xgpu_nv_mailbox_put_irq()
443 	amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);  in xgpu_nv_mailbox_put_irq()