Lines Matching +full:0 +full:xf0ffffff
57 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
58 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
60 #define regCGTT_WD_CLK_CTRL 0x5086
62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1 0x4e7e
64 #define regPC_CONFIG_CNTL_1 0x194d
103 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
104 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
105 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
116 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
118 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
119 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
120 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
121 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
122 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
123 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
124 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
125 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE),
126 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR),
127 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR),
128 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
136 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
137 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
138 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
139 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT),
140 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT),
141 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
142 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
143 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
144 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS),
145 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
146 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
147 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
148 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
149 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
150 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS),
151 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
152 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
153 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR),
155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR),
156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
166 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
167 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
168 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
169 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3),
170 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE4),
171 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE5)
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
196 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
205 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
206 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
207 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
208 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS)
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
234 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)
247 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
252 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
253 SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
257 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
258 SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
259 SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
260 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
304 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
305 PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */ in gfx11_kiq_set_resources()
306 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ in gfx11_kiq_set_resources()
311 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_set_resources()
312 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx11_kiq_set_resources()
320 uint32_t me = 0, eng_sel = 0; in gfx11_kiq_map_queues()
325 eng_sel = 0; in gfx11_kiq_map_queues()
328 me = 0; in gfx11_kiq_map_queues()
340 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ in gfx11_kiq_map_queues()
341 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_map_queues()
342 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ in gfx11_kiq_map_queues()
343 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ in gfx11_kiq_map_queues()
347 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ in gfx11_kiq_map_queues()
348 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ in gfx11_kiq_map_queues()
364 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx11_kiq_unmap_queues()
366 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx11_kiq_unmap_queues()
372 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_unmap_queues()
374 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | in gfx11_kiq_unmap_queues()
385 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
386 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
387 amdgpu_ring_write(kiq_ring, 0); in gfx11_kiq_unmap_queues()
396 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx11_kiq_query_status()
400 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | in gfx11_kiq_query_status()
401 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | in gfx11_kiq_query_status()
403 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ in gfx11_kiq_query_status()
434 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
442 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_init_golden_registers()
443 case IP_VERSION(11, 0, 1): in gfx_v11_0_init_golden_registers()
444 case IP_VERSION(11, 0, 4): in gfx_v11_0_init_golden_registers()
463 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()
465 amdgpu_ring_write(ring, 0); in gfx_v11_0_write_data_to_reg()
476 /* memory (1) or register (0) */ in gfx_v11_0_wait_reg_mem()
483 BUG_ON(addr0 & 0x3); /* Dword align */ in gfx_v11_0_wait_reg_mem()
499 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ in gfx_v11_ring_insert_nop()
500 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); in gfx_v11_ring_insert_nop()
502 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ in gfx_v11_ring_insert_nop()
509 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_ring_test_ring()
510 uint32_t tmp = 0; in gfx_v11_0_ring_test_ring()
514 WREG32(scratch, 0xCAFEDEAD); in gfx_v11_0_ring_test_ring()
523 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF); in gfx_v11_0_ring_test_ring()
528 amdgpu_ring_write(ring, 0xDEADBEEF); in gfx_v11_0_ring_test_ring()
532 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_ring_test_ring()
534 if (tmp == 0xDEADBEEF) in gfx_v11_0_ring_test_ring()
560 return 0; in gfx_v11_0_ring_test_ib()
562 memset(&ib, 0, sizeof(ib)); in gfx_v11_0_ring_test_ib()
576 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); in gfx_v11_0_ring_test_ib()
583 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); in gfx_v11_0_ring_test_ib()
593 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v11_0_ring_test_ib()
597 ib.ptr[4] = 0xDEADBEEF; in gfx_v11_0_ring_test_ib()
605 if (r == 0) { in gfx_v11_0_ring_test_ib()
608 } else if (r < 0) { in gfx_v11_0_ring_test_ib()
612 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) in gfx_v11_0_ring_test_ib()
613 r = 0; in gfx_v11_0_ring_test_ib()
639 int err = 0; in gfx_v11_0_init_toc_microcode()
653 return 0; in gfx_v11_0_init_toc_microcode()
661 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_check_fw_cp_gfx_shadow()
662 case IP_VERSION(11, 0, 0): in gfx_v11_0_check_fw_cp_gfx_shadow()
663 case IP_VERSION(11, 0, 2): in gfx_v11_0_check_fw_cp_gfx_shadow()
664 case IP_VERSION(11, 0, 3): in gfx_v11_0_check_fw_cp_gfx_shadow()
699 adev->gfx.pfp_fw->data, 2, 0); in gfx_v11_0_init_microcode()
723 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) && in gfx_v11_0_init_microcode()
724 adev->pdev->revision == 0xCE) in gfx_v11_0_init_microcode()
761 /* only one MEC for gfx 11.0.0. */ in gfx_v11_0_init_microcode()
786 u32 count = 0; in gfx_v11_0_get_csb_size()
800 return 0; in gfx_v11_0_get_csb_size()
817 u32 count = 0, i; in gfx_v11_0_get_csb_buffer()
827 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_get_csb_buffer()
831 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v11_0_get_csb_buffer()
832 buffer[count++] = cpu_to_le32(0x80000000); in gfx_v11_0_get_csb_buffer()
841 for (i = 0; i < ext->reg_count; i++) in gfx_v11_0_get_csb_buffer()
850 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_get_csb_buffer()
855 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_get_csb_buffer()
858 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_get_csb_buffer()
859 buffer[count++] = cpu_to_le32(0); in gfx_v11_0_get_csb_buffer()
879 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
880 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
881 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
882 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
883 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
884 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
885 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
886 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
906 /* init spm vmid with 0xf */ in gfx_v11_0_rlc_init()
908 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v11_0_rlc_init()
910 return 0; in gfx_v11_0_rlc_init()
933 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); in gfx_v11_0_mec_init()
951 memset(hpd, 0, mec_hpd_size); in gfx_v11_0_mec_init()
957 return 0; in gfx_v11_0_mec_init()
962 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_ind()
965 return RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_ind()
972 WREG32_SOC15(GC, 0, regSQ_IND_INDEX, in wave_read_regs()
978 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA); in wave_read_regs()
986 WARN_ON(simd != 0); in gfx_v11_0_read_wave_data()
1011 WARN_ON(simd != 0); in gfx_v11_0_read_wave_sgprs()
1014 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, in gfx_v11_0_read_wave_sgprs()
1048 return 0; in gfx_v11_0_get_gfx_shadow_info()
1050 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info)); in gfx_v11_0_get_gfx_shadow_info()
1068 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_gpu_early_init()
1069 case IP_VERSION(11, 0, 0): in gfx_v11_0_gpu_early_init()
1070 case IP_VERSION(11, 0, 2): in gfx_v11_0_gpu_early_init()
1072 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1073 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1074 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
1075 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
1077 case IP_VERSION(11, 0, 3): in gfx_v11_0_gpu_early_init()
1080 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1081 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1082 adev->gfx.config.sc_hiz_tile_fifo_size = 0; in gfx_v11_0_gpu_early_init()
1083 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; in gfx_v11_0_gpu_early_init()
1085 case IP_VERSION(11, 0, 1): in gfx_v11_0_gpu_early_init()
1086 case IP_VERSION(11, 0, 4): in gfx_v11_0_gpu_early_init()
1087 case IP_VERSION(11, 5, 0): in gfx_v11_0_gpu_early_init()
1091 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; in gfx_v11_0_gpu_early_init()
1092 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; in gfx_v11_0_gpu_early_init()
1093 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; in gfx_v11_0_gpu_early_init()
1094 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300; in gfx_v11_0_gpu_early_init()
1101 return 0; in gfx_v11_0_gpu_early_init()
1124 ring->vm_hub = AMDGPU_GFXHUB(0); in gfx_v11_0_gfx_ring_init()
1154 ring->vm_hub = AMDGPU_GFXHUB(0); in gfx_v11_0_compute_ring_init()
1168 return 0; in gfx_v11_0_compute_ring_init()
1193 uint32_t total_size = 0; in gfx_v11_0_calc_toc_total_size()
1228 return 0; in gfx_v11_0_rlc_autoload_buffer_init()
1247 if (fw_size == 0) in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1256 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); in gfx_v11_0_rlc_backdoor_autoload_copy_ucode()
1269 *(uint64_t *)fw_autoload_mask |= 0x1; in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1271 DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask); in gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode()
1418 adev->sdma.instance[0].fw->data; in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1419 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1426 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + in gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode()
1442 for (pipe = 0; pipe < 2; pipe++) { in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1443 if (pipe==0) { in gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode()
1476 memset(autoload_fw_id, 0, sizeof(uint32_t) * 2); in gfx_v11_0_rlc_backdoor_autoload_enable()
1488 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1489 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr)); in gfx_v11_0_rlc_backdoor_autoload_enable()
1491 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size); in gfx_v11_0_rlc_backdoor_autoload_enable()
1505 return 0; in gfx_v11_0_rlc_backdoor_autoload_enable()
1551 int i, j, k, r, ring_id = 0; in gfx_v11_0_sw_init()
1552 int xcc_id = 0; in gfx_v11_0_sw_init()
1555 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_sw_init()
1556 case IP_VERSION(11, 0, 0): in gfx_v11_0_sw_init()
1557 case IP_VERSION(11, 0, 2): in gfx_v11_0_sw_init()
1558 case IP_VERSION(11, 0, 3): in gfx_v11_0_sw_init()
1566 case IP_VERSION(11, 0, 1): in gfx_v11_0_sw_init()
1567 case IP_VERSION(11, 0, 4): in gfx_v11_0_sw_init()
1568 case IP_VERSION(11, 5, 0): in gfx_v11_0_sw_init()
1588 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_sw_init()
1589 case IP_VERSION(11, 0, 0): in gfx_v11_0_sw_init()
1590 case IP_VERSION(11, 0, 2): in gfx_v11_0_sw_init()
1591 case IP_VERSION(11, 0, 3): in gfx_v11_0_sw_init()
1597 adev->mes.fw_version[0] >= 99) { in gfx_v11_0_sw_init()
1612 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) && in gfx_v11_0_sw_init()
1668 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_sw_init()
1669 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1670 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_sw_init()
1683 ring_id = 0; in gfx_v11_0_sw_init()
1685 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_sw_init()
1686 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_sw_init()
1687 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_sw_init()
1688 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i, in gfx_v11_0_sw_init()
1703 amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); in gfx_v11_0_sw_init()
1705 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); in gfx_v11_0_sw_init()
1706 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_sw_init()
1707 case IP_VERSION(11, 0, 0): in gfx_v11_0_sw_init()
1708 case IP_VERSION(11, 0, 2): in gfx_v11_0_sw_init()
1709 case IP_VERSION(11, 0, 3): in gfx_v11_0_sw_init()
1721 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0); in gfx_v11_0_sw_init()
1732 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0); in gfx_v11_0_sw_init()
1758 return 0; in gfx_v11_0_sw_init()
1795 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_sw_fini()
1797 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_sw_fini()
1800 amdgpu_gfx_mqd_sw_fini(adev, 0); in gfx_v11_0_sw_fini()
1803 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); in gfx_v11_0_sw_fini()
1804 amdgpu_gfx_kiq_fini(adev, 0); in gfx_v11_0_sw_fini()
1825 return 0; in gfx_v11_0_sw_fini()
1833 if (instance == 0xffffffff) in gfx_v11_0_select_se_sh()
1834 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v11_0_select_se_sh()
1837 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v11_0_select_se_sh()
1840 if (se_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1846 if (sh_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1852 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); in gfx_v11_0_select_se_sh()
1859 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1863 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); in gfx_v11_0_get_sa_active_bitmap()
1878 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1882 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); in gfx_v11_0_get_rb_active_bitmap()
1899 u32 active_rb_bitmap = 0; in gfx_v11_0_setup_rb()
1914 for (i = 0; i < max_sa; i++) { in gfx_v11_0_setup_rb()
1924 #define DEFAULT_SH_MEM_BASES (0x6000)
1925 #define LDS_APP_BASE 0x1
1926 #define SCRATCH_APP_BASE 0x2
1936 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) in gfx_v11_0_init_compute_vmid()
1937 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) in gfx_v11_0_init_compute_vmid()
1938 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) in gfx_v11_0_init_compute_vmid()
1945 soc21_grbm_select(adev, 0, 0, 0, i); in gfx_v11_0_init_compute_vmid()
1947 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_init_compute_vmid()
1948 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases); in gfx_v11_0_init_compute_vmid()
1951 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL); in gfx_v11_0_init_compute_vmid()
1953 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data); in gfx_v11_0_init_compute_vmid()
1955 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_init_compute_vmid()
1963 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1964 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); in gfx_v11_0_init_compute_vmid()
1965 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
1966 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0); in gfx_v11_0_init_compute_vmid()
1981 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
1982 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0); in gfx_v11_0_init_gds_vmid()
1983 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
1984 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0); in gfx_v11_0_init_gds_vmid()
1996 uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) | in gfx_v11_0_get_tcc_info()
1997 RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE); in gfx_v11_0_get_tcc_info()
2010 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); in gfx_v11_0_constants_init()
2015 adev->gfx.config.pa_sc_tile_steering_override = 0; in gfx_v11_0_constants_init()
2018 tmp = RREG32_SOC15(GC, 0, regTA_CNTL2); in gfx_v11_0_constants_init()
2025 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { in gfx_v11_0_constants_init()
2026 soc21_grbm_select(adev, 0, 0, 0, i); in gfx_v11_0_constants_init()
2028 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); in gfx_v11_0_constants_init()
2029 if (i != 0) { in gfx_v11_0_constants_init()
2030 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, in gfx_v11_0_constants_init()
2034 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp); in gfx_v11_0_constants_init()
2037 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_constants_init()
2048 if (me != 0) in gfx_v11_0_get_cpg_int_cntl()
2049 return 0; in gfx_v11_0_get_cpg_int_cntl()
2052 case 0: in gfx_v11_0_get_cpg_int_cntl()
2053 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_get_cpg_int_cntl()
2055 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_get_cpg_int_cntl()
2057 return 0; in gfx_v11_0_get_cpg_int_cntl()
2070 return 0; in gfx_v11_0_get_cpc_int_cntl()
2073 case 0: in gfx_v11_0_get_cpc_int_cntl()
2074 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2076 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2078 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2080 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_get_cpc_int_cntl()
2082 return 0; in gfx_v11_0_get_cpc_int_cntl()
2095 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_enable_gui_idle_interrupt()
2096 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_enable_gui_idle_interrupt()
2102 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2104 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2106 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2108 enable ? 1 : 0); in gfx_v11_0_enable_gui_idle_interrupt()
2119 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI, in gfx_v11_0_init_csb()
2121 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO, in gfx_v11_0_init_csb()
2122 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); in gfx_v11_0_init_csb()
2123 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v11_0_init_csb()
2125 return 0; in gfx_v11_0_init_csb()
2130 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_rlc_stop()
2132 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v11_0_rlc_stop()
2133 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
2138 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v11_0_rlc_reset()
2140 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v11_0_rlc_reset()
2149 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_0_rlc_smu_handshake_cntl()
2152 /* RLC_PG_CNTL[23] = 0 (default) in gfx_v11_0_rlc_smu_handshake_cntl()
2163 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v11_0_rlc_smu_handshake_cntl()
2173 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v11_0_rlc_start()
2182 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL)); in gfx_v11_0_rlc_enable_srm()
2185 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp); in gfx_v11_0_rlc_enable_srm()
2199 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, in gfx_v11_0_load_rlcg_microcode()
2202 for (i = 0; i < fw_size; i++) in gfx_v11_0_load_rlcg_microcode()
2203 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA, in gfx_v11_0_load_rlcg_microcode()
2206 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcg_microcode()
2222 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2224 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlc_iram_dram_microcode()
2227 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
2231 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2237 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2238 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlc_iram_dram_microcode()
2241 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA, in gfx_v11_0_load_rlc_iram_dram_microcode()
2245 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlc_iram_dram_microcode()
2247 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL); in gfx_v11_0_load_rlc_iram_dram_microcode()
2249 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); in gfx_v11_0_load_rlc_iram_dram_microcode()
2250 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp); in gfx_v11_0_load_rlc_iram_dram_microcode()
2266 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
2268 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlcp_rlcv_microcode()
2271 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
2275 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2277 tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE); in gfx_v11_0_load_rlcp_rlcv_microcode()
2279 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
2285 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0); in gfx_v11_0_load_rlcp_rlcv_microcode()
2287 for (i = 0; i < fw_size; i++) { in gfx_v11_0_load_rlcp_rlcv_microcode()
2290 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA, in gfx_v11_0_load_rlcp_rlcv_microcode()
2294 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version); in gfx_v11_0_load_rlcp_rlcv_microcode()
2296 tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL); in gfx_v11_0_load_rlcp_rlcv_microcode()
2298 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp); in gfx_v11_0_load_rlcp_rlcv_microcode()
2325 return 0; in gfx_v11_0_rlc_load_microcode()
2343 return 0; in gfx_v11_0_rlc_resume()
2349 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0); in gfx_v11_0_rlc_resume()
2352 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v11_0_rlc_resume()
2365 return 0; in gfx_v11_0_rlc_resume()
2375 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2377 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache()
2380 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache()
2381 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache()
2396 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache()
2397 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache()
2398 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache()
2399 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_me_cache()
2401 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache()
2404 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache()
2405 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_me_cache()
2406 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache()
2409 return 0; in gfx_v11_0_config_me_cache()
2419 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2421 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2424 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache()
2425 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache()
2440 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache()
2441 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache()
2442 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache()
2443 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_pfp_cache()
2445 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache()
2448 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache()
2449 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_pfp_cache()
2450 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache()
2453 return 0; in gfx_v11_0_config_pfp_cache()
2463 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2466 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2469 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache()
2470 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2485 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache()
2486 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache()
2487 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_mec_cache()
2489 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2492 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v11_0_config_mec_cache()
2493 lower_32_bits(addr) & 0xFFFFF000); in gfx_v11_0_config_mec_cache()
2494 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache()
2497 return 0; in gfx_v11_0_config_mec_cache()
2510 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_config_pfp_cache_rs64()
2512 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_config_pfp_cache_rs64()
2515 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2516 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2517 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache_rs64()
2518 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_pfp_cache_rs64()
2519 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2526 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2527 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2540 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2542 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2544 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2545 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2558 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_pfp_cache_rs64()
2559 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_pfp_cache_rs64()
2560 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_pfp_cache_rs64()
2563 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_pfp_cache_rs64()
2570 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2571 if (pipe_id == 0) in gfx_v11_0_config_pfp_cache_rs64()
2577 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2580 if (pipe_id == 0) in gfx_v11_0_config_pfp_cache_rs64()
2582 PFP_PIPE0_RESET, 0); in gfx_v11_0_config_pfp_cache_rs64()
2585 PFP_PIPE1_RESET, 0); in gfx_v11_0_config_pfp_cache_rs64()
2586 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2588 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_config_pfp_cache_rs64()
2590 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_config_pfp_cache_rs64()
2593 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_pfp_cache_rs64()
2596 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2597 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_pfp_cache_rs64()
2598 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_pfp_cache_rs64()
2599 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2602 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2604 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_pfp_cache_rs64()
2606 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_pfp_cache_rs64()
2607 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_pfp_cache_rs64()
2619 return 0; in gfx_v11_0_config_pfp_cache_rs64()
2632 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_config_me_cache_rs64()
2634 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_config_me_cache_rs64()
2637 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2638 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2639 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache_rs64()
2640 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_me_cache_rs64()
2641 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2648 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2649 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2662 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2664 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2667 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2668 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2681 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_config_me_cache_rs64()
2682 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_me_cache_rs64()
2683 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_me_cache_rs64()
2686 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_me_cache_rs64()
2693 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_me_cache_rs64()
2694 if (pipe_id == 0) in gfx_v11_0_config_me_cache_rs64()
2700 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2703 if (pipe_id == 0) in gfx_v11_0_config_me_cache_rs64()
2705 ME_PIPE0_RESET, 0); in gfx_v11_0_config_me_cache_rs64()
2708 ME_PIPE1_RESET, 0); in gfx_v11_0_config_me_cache_rs64()
2709 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2711 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_config_me_cache_rs64()
2713 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_config_me_cache_rs64()
2716 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_me_cache_rs64()
2719 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_config_me_cache_rs64()
2720 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_me_cache_rs64()
2721 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_me_cache_rs64()
2722 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2725 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2727 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_config_me_cache_rs64()
2729 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_me_cache_rs64()
2730 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_config_me_cache_rs64()
2742 return 0; in gfx_v11_0_config_me_cache_rs64()
2755 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2756 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2757 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_config_mec_cache_rs64()
2758 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache_rs64()
2759 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2761 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2762 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_config_mec_cache_rs64()
2763 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_config_mec_cache_rs64()
2764 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2767 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_config_mec_cache_rs64()
2768 soc21_grbm_select(adev, 1, i, 0, 0); in gfx_v11_0_config_mec_cache_rs64()
2770 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2); in gfx_v11_0_config_mec_cache_rs64()
2771 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2774 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_mec_cache_rs64()
2777 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_mec_cache_rs64()
2780 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); in gfx_v11_0_config_mec_cache_rs64()
2781 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_config_mec_cache_rs64()
2785 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_mec_cache_rs64()
2788 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2790 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2793 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache_rs64()
2794 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2807 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2809 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2812 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_config_mec_cache_rs64()
2813 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2825 return 0; in gfx_v11_0_config_mec_cache_rs64()
2843 for (pipe_id = 0; pipe_id < 2; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2844 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2845 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2848 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2851 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2854 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2857 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2860 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2861 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2862 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2865 for (pipe_id = 0; pipe_id < 2; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2866 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2867 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2870 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2873 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2876 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_config_gfx_rs64()
2879 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2882 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2883 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2884 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2887 for (pipe_id = 0; pipe_id < 4; pipe_id++) { in gfx_v11_0_config_gfx_rs64()
2888 soc21_grbm_select(adev, 1, pipe_id, 0, 0); in gfx_v11_0_config_gfx_rs64()
2889 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_config_gfx_rs64()
2892 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_config_gfx_rs64()
2895 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_config_gfx_rs64()
2898 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_config_gfx_rs64()
2903 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2906 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2907 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2908 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2909 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); in gfx_v11_0_config_gfx_rs64()
2910 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp); in gfx_v11_0_config_gfx_rs64()
2920 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_wait_for_rlc_autoload_complete()
2921 cp_status = RREG32_SOC15(GC, 0, regCP_STAT); in gfx_v11_0_wait_for_rlc_autoload_complete()
2923 if (amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v11_0_wait_for_rlc_autoload_complete()
2924 IP_VERSION(11, 0, 1) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2925 amdgpu_ip_version(adev, GC_HWIP, 0) == in gfx_v11_0_wait_for_rlc_autoload_complete()
2926 IP_VERSION(11, 0, 4) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2927 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2928 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || in gfx_v11_0_wait_for_rlc_autoload_complete()
2929 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2)) in gfx_v11_0_wait_for_rlc_autoload_complete()
2930 bootload_status = RREG32_SOC15(GC, 0, in gfx_v11_0_wait_for_rlc_autoload_complete()
2933 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS); in gfx_v11_0_wait_for_rlc_autoload_complete()
2935 if ((cp_status == 0) && in gfx_v11_0_wait_for_rlc_autoload_complete()
2990 return 0; in gfx_v11_0_wait_for_rlc_autoload_complete()
2996 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_enable()
2998 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v11_0_cp_gfx_enable()
2999 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v11_0_cp_gfx_enable()
3000 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_enable()
3002 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_cp_gfx_enable()
3003 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0) in gfx_v11_0_cp_gfx_enable()
3011 return 0; in gfx_v11_0_cp_gfx_enable()
3048 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3050 for (i = 0; i < pfp_hdr->jt_size; i++) in gfx_v11_0_cp_gfx_load_pfp_microcode()
3051 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA, in gfx_v11_0_cp_gfx_load_pfp_microcode()
3054 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); in gfx_v11_0_cp_gfx_load_pfp_microcode()
3056 return 0; in gfx_v11_0_cp_gfx_load_pfp_microcode()
3120 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3122 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3125 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3126 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3127 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3128 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3129 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3136 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3137 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3150 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3152 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3154 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3155 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3168 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3169 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3170 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3173 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3180 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3181 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3187 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3190 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3192 PFP_PIPE0_RESET, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3195 PFP_PIPE1_RESET, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3196 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3198 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3200 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3203 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3206 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3207 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3208 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3209 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3212 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3214 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3216 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3217 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3229 return 0; in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3266 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0); in gfx_v11_0_cp_gfx_load_me_microcode()
3268 for (i = 0; i < me_hdr->jt_size; i++) in gfx_v11_0_cp_gfx_load_me_microcode()
3269 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA, in gfx_v11_0_cp_gfx_load_me_microcode()
3272 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); in gfx_v11_0_cp_gfx_load_me_microcode()
3274 return 0; in gfx_v11_0_cp_gfx_load_me_microcode()
3338 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3340 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3343 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3344 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3345 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3346 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3347 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3354 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3355 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3368 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3370 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3373 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3374 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3387 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3388 soc21_grbm_select(adev, 0, pipe_id, 0, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3389 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3392 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3399 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3400 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3406 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3409 if (pipe_id == 0) in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3411 ME_PIPE0_RESET, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3414 ME_PIPE1_RESET, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3415 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3417 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3419 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI, in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3422 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3425 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3426 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3427 tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3428 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3431 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3433 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3435 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3436 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL); in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3448 return 0; in gfx_v11_0_cp_gfx_load_me_microcode_rs64()
3478 return 0; in gfx_v11_0_cp_gfx_load_microcode()
3490 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT, in gfx_v11_0_cp_gfx_start()
3492 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1); in gfx_v11_0_cp_gfx_start()
3497 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_start()
3504 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_cp_gfx_start()
3508 amdgpu_ring_write(ring, 0x80000000); in gfx_v11_0_cp_gfx_start()
3509 amdgpu_ring_write(ring, 0x80000000); in gfx_v11_0_cp_gfx_start()
3519 for (i = 0; i < ext->reg_count; i++) in gfx_v11_0_cp_gfx_start()
3526 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
3531 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v11_0_cp_gfx_start()
3534 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_cp_gfx_start()
3535 amdgpu_ring_write(ring, 0); in gfx_v11_0_cp_gfx_start()
3539 /* submit cs packet to copy state 0 to next available state */ in gfx_v11_0_cp_gfx_start()
3549 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v11_0_cp_gfx_start()
3550 amdgpu_ring_write(ring, 0); in gfx_v11_0_cp_gfx_start()
3554 return 0; in gfx_v11_0_cp_gfx_start()
3562 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_cp_gfx_switch_pipe()
3565 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp); in gfx_v11_0_cp_gfx_switch_pipe()
3573 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_cp_gfx_set_doorbell()
3581 DOORBELL_EN, 0); in gfx_v11_0_cp_gfx_set_doorbell()
3583 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3585 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_gfx_set_doorbell()
3587 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp); in gfx_v11_0_cp_gfx_set_doorbell()
3589 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_gfx_set_doorbell()
3601 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0); in gfx_v11_0_cp_gfx_resume()
3603 /* set the RB to use vmid 0 */ in gfx_v11_0_cp_gfx_resume()
3604 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0); in gfx_v11_0_cp_gfx_resume()
3606 /* Init gfx ring 0 for pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3611 ring = &adev->gfx.gfx_ring[0]; in gfx_v11_0_cp_gfx_resume()
3613 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3615 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3618 ring->wptr = 0; in gfx_v11_0_cp_gfx_resume()
3619 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3620 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3624 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3625 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3629 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3631 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3635 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3638 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3639 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3641 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3653 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3655 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3657 ring->wptr = 0; in gfx_v11_0_cp_gfx_resume()
3658 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3659 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); in gfx_v11_0_cp_gfx_resume()
3662 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume()
3663 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
3666 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, in gfx_v11_0_cp_gfx_resume()
3668 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, in gfx_v11_0_cp_gfx_resume()
3672 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3675 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr); in gfx_v11_0_cp_gfx_resume()
3676 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()
3677 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1); in gfx_v11_0_cp_gfx_resume()
3682 /* Switch to pipe 0 */ in gfx_v11_0_cp_gfx_resume()
3690 return 0; in gfx_v11_0_cp_gfx_resume()
3698 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL); in gfx_v11_0_cp_compute_enable()
3700 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3702 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3704 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3706 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3708 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3710 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3712 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3714 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3716 enable ? 1 : 0); in gfx_v11_0_cp_compute_enable()
3718 enable ? 0 : 1); in gfx_v11_0_cp_compute_enable()
3719 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data); in gfx_v11_0_cp_compute_enable()
3721 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL); in gfx_v11_0_cp_compute_enable()
3724 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); in gfx_v11_0_cp_compute_enable()
3727 MEC_ME2_HALT, 0); in gfx_v11_0_cp_compute_enable()
3732 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data); in gfx_v11_0_cp_compute_enable()
3778 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0); in gfx_v11_0_cp_compute_load_microcode()
3780 for (i = 0; i < mec_hdr->jt_size; i++) in gfx_v11_0_cp_compute_load_microcode()
3781 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA, in gfx_v11_0_cp_compute_load_microcode()
3784 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); in gfx_v11_0_cp_compute_load_microcode()
3786 return 0; in gfx_v11_0_cp_compute_load_microcode()
3848 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3849 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3850 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3851 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3852 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3854 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3855 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3856 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3857 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3860 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3861 soc21_grbm_select(adev, 1, i, 0, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3863 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3864 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3867 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START, in gfx_v11_0_cp_compute_load_microcode_rs64()
3870 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3873 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
3874 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI, in gfx_v11_0_cp_compute_load_microcode_rs64()
3878 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_cp_compute_load_microcode_rs64()
3881 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3883 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3886 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3887 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3900 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3902 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
3905 for (i = 0; i < usec_timeout; i++) { in gfx_v11_0_cp_compute_load_microcode_rs64()
3906 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3918 return 0; in gfx_v11_0_cp_compute_load_microcode_rs64()
3927 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in gfx_v11_0_kiq_setting()
3928 tmp &= 0xffffff00; in gfx_v11_0_kiq_setting()
3930 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in gfx_v11_0_kiq_setting()
3936 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
3938 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
3942 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_cp_set_doorbell_range()
3944 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_cp_set_doorbell_range()
3952 bool priority = 0; in gfx_v11_0_gfx_mqd_set_priority()
3956 * 0x0 = low priority, 0x1 = high priority in gfx_v11_0_gfx_mqd_set_priority()
3961 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY); in gfx_v11_0_gfx_mqd_set_priority()
3975 mqd->cp_gfx_hqd_wptr = 0; in gfx_v11_0_gfx_mqd_init()
3976 mqd->cp_gfx_hqd_wptr_hi = 0; in gfx_v11_0_gfx_mqd_init()
3979 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
3983 tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL); in gfx_v11_0_gfx_mqd_init()
3984 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); in gfx_v11_0_gfx_mqd_init()
3986 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); in gfx_v11_0_gfx_mqd_init()
3989 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ in gfx_v11_0_gfx_mqd_init()
3990 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID); in gfx_v11_0_gfx_mqd_init()
3991 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); in gfx_v11_0_gfx_mqd_init()
3992 mqd->cp_gfx_hqd_vmid = 0; in gfx_v11_0_gfx_mqd_init()
3998 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM); in gfx_v11_0_gfx_mqd_init()
4009 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4011 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
4015 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_gfx_mqd_init()
4016 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_gfx_mqd_init()
4020 tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL); in gfx_v11_0_gfx_mqd_init()
4029 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL); in gfx_v11_0_gfx_mqd_init()
4037 DOORBELL_EN, 0); in gfx_v11_0_gfx_mqd_init()
4041 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR); in gfx_v11_0_gfx_mqd_init()
4046 return 0; in gfx_v11_0_gfx_mqd_init()
4053 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; in gfx_v11_0_kgq_init_queue()
4056 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kgq_init_queue()
4058 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kgq_init_queue()
4060 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kgq_init_queue()
4069 ring->wptr = 0; in gfx_v11_0_kgq_init_queue()
4070 *ring->wptr_cpu_addr = 0; in gfx_v11_0_kgq_init_queue()
4074 return 0; in gfx_v11_0_kgq_init_queue()
4082 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_async_gfx_ring_resume()
4086 if (unlikely(r != 0)) in gfx_v11_0_cp_async_gfx_ring_resume()
4100 r = amdgpu_gfx_enable_kgq(adev, 0); in gfx_v11_0_cp_async_gfx_ring_resume()
4114 mqd->header = 0xC0310800; in gfx_v11_0_compute_mqd_init()
4115 mqd->compute_pipelinestat_enable = 0x00000001; in gfx_v11_0_compute_mqd_init()
4116 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4117 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4118 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4119 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in gfx_v11_0_compute_mqd_init()
4120 mqd->compute_misc_reserved = 0x00000007; in gfx_v11_0_compute_mqd_init()
4127 tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL); in gfx_v11_0_compute_mqd_init()
4134 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
4142 DOORBELL_SOURCE, 0); in gfx_v11_0_compute_mqd_init()
4144 DOORBELL_HIT, 0); in gfx_v11_0_compute_mqd_init()
4147 DOORBELL_EN, 0); in gfx_v11_0_compute_mqd_init()
4153 mqd->cp_hqd_dequeue_request = 0; in gfx_v11_0_compute_mqd_init()
4154 mqd->cp_hqd_pq_rptr = 0; in gfx_v11_0_compute_mqd_init()
4155 mqd->cp_hqd_pq_wptr_lo = 0; in gfx_v11_0_compute_mqd_init()
4156 mqd->cp_hqd_pq_wptr_hi = 0; in gfx_v11_0_compute_mqd_init()
4159 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4162 /* set MQD vmid to 0 */ in gfx_v11_0_compute_mqd_init()
4163 tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); in gfx_v11_0_compute_mqd_init()
4164 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v11_0_compute_mqd_init()
4173 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL); in gfx_v11_0_compute_mqd_init()
4187 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4189 upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
4193 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; in gfx_v11_0_compute_mqd_init()
4194 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()
4196 tmp = 0; in gfx_v11_0_compute_mqd_init()
4199 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
4206 DOORBELL_SOURCE, 0); in gfx_v11_0_compute_mqd_init()
4208 DOORBELL_HIT, 0); in gfx_v11_0_compute_mqd_init()
4214 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR); in gfx_v11_0_compute_mqd_init()
4217 mqd->cp_hqd_vmid = 0; in gfx_v11_0_compute_mqd_init()
4219 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE); in gfx_v11_0_compute_mqd_init()
4220 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55); in gfx_v11_0_compute_mqd_init()
4224 tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL); in gfx_v11_0_compute_mqd_init()
4234 return 0; in gfx_v11_0_compute_mqd_init()
4245 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0); in gfx_v11_0_kiq_init_register()
4248 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v11_0_kiq_init_register()
4251 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR, in gfx_v11_0_kiq_init_register()
4253 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
4257 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL, in gfx_v11_0_kiq_init_register()
4261 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4265 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in gfx_v11_0_kiq_init_register()
4266 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in gfx_v11_0_kiq_init_register()
4267 for (j = 0; j < adev->usec_timeout; j++) { in gfx_v11_0_kiq_init_register()
4268 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in gfx_v11_0_kiq_init_register()
4272 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, in gfx_v11_0_kiq_init_register()
4274 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, in gfx_v11_0_kiq_init_register()
4276 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4278 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
4283 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, in gfx_v11_0_kiq_init_register()
4285 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, in gfx_v11_0_kiq_init_register()
4288 /* set MQD vmid to 0 */ in gfx_v11_0_kiq_init_register()
4289 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, in gfx_v11_0_kiq_init_register()
4293 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, in gfx_v11_0_kiq_init_register()
4295 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, in gfx_v11_0_kiq_init_register()
4299 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, in gfx_v11_0_kiq_init_register()
4303 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in gfx_v11_0_kiq_init_register()
4305 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in gfx_v11_0_kiq_init_register()
4309 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in gfx_v11_0_kiq_init_register()
4311 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v11_0_kiq_init_register()
4316 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER, in gfx_v11_0_kiq_init_register()
4318 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER, in gfx_v11_0_kiq_init_register()
4322 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
4326 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, in gfx_v11_0_kiq_init_register()
4328 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, in gfx_v11_0_kiq_init_register()
4332 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid); in gfx_v11_0_kiq_init_register()
4334 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, in gfx_v11_0_kiq_init_register()
4338 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, in gfx_v11_0_kiq_init_register()
4342 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v11_0_kiq_init_register()
4344 return 0; in gfx_v11_0_kiq_init_register()
4356 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4357 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4360 ring->wptr = 0; in gfx_v11_0_kiq_init_queue()
4364 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kiq_init_queue()
4366 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kiq_init_queue()
4369 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4373 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kiq_init_queue()
4376 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kiq_init_queue()
4379 if (adev->gfx.kiq[0].mqd_backup) in gfx_v11_0_kiq_init_queue()
4380 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd)); in gfx_v11_0_kiq_init_queue()
4383 return 0; in gfx_v11_0_kiq_init_queue()
4390 int mqd_idx = ring - &adev->gfx.compute_ring[0]; in gfx_v11_0_kcq_init_queue()
4393 memset((void *)mqd, 0, sizeof(*mqd)); in gfx_v11_0_kcq_init_queue()
4395 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); in gfx_v11_0_kcq_init_queue()
4397 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_kcq_init_queue()
4407 ring->wptr = 0; in gfx_v11_0_kcq_init_queue()
4408 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); in gfx_v11_0_kcq_init_queue()
4412 return 0; in gfx_v11_0_kcq_init_queue()
4420 ring = &adev->gfx.kiq[0].ring; in gfx_v11_0_kiq_resume()
4423 if (unlikely(r != 0)) in gfx_v11_0_kiq_resume()
4427 if (unlikely(r != 0)) { in gfx_v11_0_kiq_resume()
4437 return 0; in gfx_v11_0_kiq_resume()
4443 int r = 0, i; in gfx_v11_0_kcq_resume()
4448 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_kcq_resume()
4452 if (unlikely(r != 0)) in gfx_v11_0_kcq_resume()
4465 r = amdgpu_gfx_enable_kcq(adev, 0); in gfx_v11_0_kcq_resume()
4520 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_cp_resume()
4527 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_cp_resume()
4534 return 0; in gfx_v11_0_cp_resume()
4560 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); in gfx_v11_0_gfxhub_enable()
4562 return 0; in gfx_v11_0_gfxhub_enable()
4571 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL); in gfx_v11_0_select_cp_fw_arch()
4573 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4575 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL); in gfx_v11_0_select_cp_fw_arch()
4577 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp); in gfx_v11_0_select_cp_fw_arch()
4588 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG); in get_gb_addr_config()
4589 if (gb_addr_config == 0) in get_gb_addr_config()
4617 return 0; in get_gb_addr_config()
4624 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4626 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4628 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4630 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
4653 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { in gfx_v11_0_hw_init()
4728 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0); in gfx_v11_0_hw_init()
4737 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_hw_fini()
4738 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_hw_fini()
4739 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); in gfx_v11_0_hw_fini()
4743 if (amdgpu_gfx_disable_kgq(adev, 0)) in gfx_v11_0_hw_fini()
4747 if (amdgpu_gfx_disable_kcq(adev, 0)) in gfx_v11_0_hw_fini()
4759 return 0; in gfx_v11_0_hw_fini()
4768 return 0; in gfx_v11_0_hw_fini()
4785 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS), in gfx_v11_0_is_idle()
4798 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_wait_for_idle()
4800 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) & in gfx_v11_0_wait_for_idle()
4804 return 0; in gfx_v11_0_wait_for_idle()
4815 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_request_gfx_index_mutex()
4816 /* Request with MeId=2, PipeId=0 */ in gfx_v11_0_request_gfx_index_mutex()
4817 tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); in gfx_v11_0_request_gfx_index_mutex()
4819 WREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX, tmp); in gfx_v11_0_request_gfx_index_mutex()
4821 val = RREG32_SOC15(GC, 0, regCP_GFX_INDEX_MUTEX); in gfx_v11_0_request_gfx_index_mutex()
4839 return 0; in gfx_v11_0_request_gfx_index_mutex()
4844 u32 grbm_soft_reset = 0; in gfx_v11_0_soft_reset()
4849 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_soft_reset()
4851 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4852 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4853 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4854 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4855 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); in gfx_v11_0_soft_reset()
4856 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4859 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { in gfx_v11_0_soft_reset()
4860 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4861 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { in gfx_v11_0_soft_reset()
4862 soc21_grbm_select(adev, i, k, j, 0); in gfx_v11_0_soft_reset()
4864 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in gfx_v11_0_soft_reset()
4865 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in gfx_v11_0_soft_reset()
4869 for (i = 0; i < adev->gfx.me.num_me; ++i) { in gfx_v11_0_soft_reset()
4870 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { in gfx_v11_0_soft_reset()
4871 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { in gfx_v11_0_soft_reset()
4872 soc21_grbm_select(adev, i, k, j, 0); in gfx_v11_0_soft_reset()
4874 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1); in gfx_v11_0_soft_reset()
4878 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_0_soft_reset()
4890 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); in gfx_v11_0_soft_reset()
4893 // to get sufficient time for GFX_HQD_ACTIVE reach 0 in gfx_v11_0_soft_reset()
4894 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4895 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4896 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4906 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_soft_reset()
4907 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) && in gfx_v11_0_soft_reset()
4908 !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE)) in gfx_v11_0_soft_reset()
4918 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
4929 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
4931 grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); in gfx_v11_0_soft_reset()
4933 SOFT_RESET_CP, 0); in gfx_v11_0_soft_reset()
4935 SOFT_RESET_GFX, 0); in gfx_v11_0_soft_reset()
4937 SOFT_RESET_CPF, 0); in gfx_v11_0_soft_reset()
4939 SOFT_RESET_CPC, 0); in gfx_v11_0_soft_reset()
4941 SOFT_RESET_CPG, 0); in gfx_v11_0_soft_reset()
4942 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset); in gfx_v11_0_soft_reset()
4944 tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL); in gfx_v11_0_soft_reset()
4945 tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1); in gfx_v11_0_soft_reset()
4946 WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp); in gfx_v11_0_soft_reset()
4948 WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0); in gfx_v11_0_soft_reset()
4949 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0); in gfx_v11_0_soft_reset()
4951 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_soft_reset()
4952 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) in gfx_v11_0_soft_reset()
4957 printk("Failed to wait CP_VMID_RESET to 0\n"); in gfx_v11_0_soft_reset()
4961 tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_soft_reset()
4966 WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); in gfx_v11_0_soft_reset()
4968 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_soft_reset()
4980 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_check_soft_reset()
4987 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_check_soft_reset()
5014 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
5015 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
5016 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI); in gfx_v11_0_get_gpu_clock_counter()
5018 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO); in gfx_v11_0_get_gpu_clock_counter()
5023 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in gfx_v11_0_get_gpu_clock_counter()
5024 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in gfx_v11_0_get_gpu_clock_counter()
5025 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); in gfx_v11_0_get_gpu_clock_counter()
5027 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); in gfx_v11_0_get_gpu_clock_counter()
5044 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
5045 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
5049 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
5050 SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid, in gfx_v11_0_ring_emit_gds_switch()
5054 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
5055 SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
5059 gfx_v11_0_write_data_to_reg(ring, 0, false, in gfx_v11_0_ring_emit_gds_switch()
5060 SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid, in gfx_v11_0_ring_emit_gds_switch()
5092 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); in gfx_v11_0_late_init()
5096 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); in gfx_v11_0_late_init()
5100 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); in gfx_v11_0_late_init()
5103 return 0; in gfx_v11_0_late_init()
5111 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_is_rlc_enabled()
5123 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data); in gfx_v11_0_set_safe_mode()
5126 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_set_safe_mode()
5127 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE), in gfx_v11_0_set_safe_mode()
5136 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); in gfx_v11_0_unset_safe_mode()
5147 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_perf_clk()
5155 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_perf_clk()
5166 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_sram_fgcg()
5174 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_sram_fgcg()
5185 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_repeater_fgcg()
5193 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_repeater_fgcg()
5208 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
5215 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
5219 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_medium_grain_clock_gating()
5226 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_medium_grain_clock_gating()
5244 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_update_coarse_grain_clock_gating()
5257 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5259 /* enable cgcg FSM(0x0000363F) */ in gfx_v11_0_update_coarse_grain_clock_gating()
5260 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5264 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5270 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5275 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5278 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5282 data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5288 data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5293 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5295 /* set IDLE_POLL_COUNT(0x00900100) */ in gfx_v11_0_update_coarse_grain_clock_gating()
5296 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5299 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | in gfx_v11_0_update_coarse_grain_clock_gating()
5300 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v11_0_update_coarse_grain_clock_gating()
5303 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5305 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL); in gfx_v11_0_update_coarse_grain_clock_gating()
5310 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5312 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5314 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5318 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5320 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5324 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5333 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5336 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_update_coarse_grain_clock_gating()
5344 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5346 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5348 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5352 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5354 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5362 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_update_gfx_clock_gating()
5382 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_update_gfx_clock_gating()
5384 return 0; in gfx_v11_0_update_gfx_clock_gating()
5392 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_update_spm_vmid()
5403 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5405 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5434 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_cntl_power_gating()
5441 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); in gfx_v11_cntl_power_gating()
5445 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_cntl_power_gating()
5446 case IP_VERSION(11, 0, 1): in gfx_v11_cntl_power_gating()
5447 case IP_VERSION(11, 0, 4): in gfx_v11_cntl_power_gating()
5448 case IP_VERSION(11, 5, 0): in gfx_v11_cntl_power_gating()
5451 WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); in gfx_v11_cntl_power_gating()
5461 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_cntl_pg()
5465 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_cntl_pg()
5475 return 0; in gfx_v11_0_set_powergating_state()
5477 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_set_powergating_state()
5478 case IP_VERSION(11, 0, 0): in gfx_v11_0_set_powergating_state()
5479 case IP_VERSION(11, 0, 2): in gfx_v11_0_set_powergating_state()
5480 case IP_VERSION(11, 0, 3): in gfx_v11_0_set_powergating_state()
5483 case IP_VERSION(11, 0, 1): in gfx_v11_0_set_powergating_state()
5484 case IP_VERSION(11, 0, 4): in gfx_v11_0_set_powergating_state()
5485 case IP_VERSION(11, 5, 0): in gfx_v11_0_set_powergating_state()
5501 return 0; in gfx_v11_0_set_powergating_state()
5510 return 0; in gfx_v11_0_set_clockgating_state()
5512 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in gfx_v11_0_set_clockgating_state()
5513 case IP_VERSION(11, 0, 0): in gfx_v11_0_set_clockgating_state()
5514 case IP_VERSION(11, 0, 1): in gfx_v11_0_set_clockgating_state()
5515 case IP_VERSION(11, 0, 2): in gfx_v11_0_set_clockgating_state()
5516 case IP_VERSION(11, 0, 3): in gfx_v11_0_set_clockgating_state()
5517 case IP_VERSION(11, 0, 4): in gfx_v11_0_set_clockgating_state()
5518 case IP_VERSION(11, 5, 0): in gfx_v11_0_set_clockgating_state()
5528 return 0; in gfx_v11_0_set_clockgating_state()
5537 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE); in gfx_v11_0_get_clockgating_state()
5554 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL); in gfx_v11_0_get_clockgating_state()
5563 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D); in gfx_v11_0_get_clockgating_state()
5587 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR); in gfx_v11_0_ring_get_wptr_gfx()
5588 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32; in gfx_v11_0_ring_get_wptr_gfx()
5604 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, in gfx_v11_0_ring_set_wptr_gfx()
5606 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, in gfx_v11_0_ring_set_wptr_gfx()
5660 reg_mem_engine = 0; in gfx_v11_0_ring_emit_hdp_flush()
5666 gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, in gfx_v11_0_ring_emit_hdp_flush()
5669 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
5678 u32 header, control = 0; in gfx_v11_0_ring_emit_ib_gfx()
5699 control |= 0x400000; in gfx_v11_0_ring_emit_ib_gfx()
5702 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ in gfx_v11_0_ring_emit_ib_gfx()
5705 (2 << 0) | in gfx_v11_0_ring_emit_ib_gfx()
5722 control |= 0x40000000; in gfx_v11_0_ring_emit_ib_compute()
5732 * GDS to 0 for this ring (me/pipe). in gfx_v11_0_ring_emit_ib_compute()
5741 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ in gfx_v11_0_ring_emit_ib_compute()
5744 (2 << 0) | in gfx_v11_0_ring_emit_ib_compute()
5767 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); in gfx_v11_0_ring_emit_fence()
5774 BUG_ON(addr & 0x7); in gfx_v11_0_ring_emit_fence()
5776 BUG_ON(addr & 0x3); in gfx_v11_0_ring_emit_fence()
5782 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); in gfx_v11_0_ring_emit_fence()
5791 gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), in gfx_v11_0_ring_emit_pipeline_sync()
5792 upper_32_bits(addr), seq, 0xffffffff, 4); in gfx_v11_0_ring_emit_pipeline_sync()
5799 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); in gfx_v11_0_ring_invalidate_tlbs()
5811 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); in gfx_v11_0_ring_emit_vm_flush()
5818 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in gfx_v11_0_ring_emit_vm_flush()
5819 amdgpu_ring_write(ring, 0x0); in gfx_v11_0_ring_emit_vm_flush()
5825 ring->set_q_mode_offs = 0; in gfx_v11_0_ring_emit_vm_flush()
5839 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v11_0_ring_emit_fence_kiq()
5848 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | in gfx_v11_0_ring_emit_fence_kiq()
5849 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()
5850 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS)); in gfx_v11_0_ring_emit_fence_kiq()
5851 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_fence_kiq()
5852 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ in gfx_v11_0_ring_emit_fence_kiq()
5859 uint32_t dw2 = 0; in gfx_v11_0_ring_emit_cntxcntl()
5861 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ in gfx_v11_0_ring_emit_cntxcntl()
5864 dw2 |= 0x8001; in gfx_v11_0_ring_emit_cntxcntl()
5866 dw2 |= 0x01000000; in gfx_v11_0_ring_emit_cntxcntl()
5868 dw2 |= 0x10002; in gfx_v11_0_ring_emit_cntxcntl()
5873 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_cntxcntl()
5884 /* discard following DWs if *cond_exec_gpu_addr==0 */ in gfx_v11_0_ring_emit_init_cond_exec()
5885 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_init_cond_exec()
5888 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_init_cond_exec()
5924 amdgpu_ring_write(ring, shadow_va ? 1 : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5925 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_gfx_shadow()
5948 amdgpu_ring_write(ring, 0x1); in gfx_v11_0_ring_emit_gfx_shadow()
5959 PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5961 PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0); in gfx_v11_0_ring_emit_gfx_shadow()
5974 *ring->set_q_mode_ptr = 0; in gfx_v11_0_ring_emit_gfx_shadow()
5986 int i, r = 0; in gfx_v11_0_ring_preempt_ib()
5988 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; in gfx_v11_0_ring_preempt_ib()
6017 for (i = 0; i < adev->usec_timeout; i++) { in gfx_v11_0_ring_preempt_ib()
6037 struct v10_de_ib_state de_payload = {0}; in gfx_v11_0_ring_emit_de_meta()
6044 gfx[0].gfx_meta_data) + in gfx_v11_0_ring_emit_de_meta()
6052 gfx[0].gds_backup) + in gfx_v11_0_ring_emit_de_meta()
6073 WRITE_DATA_CACHE_POLICY(0)); in gfx_v11_0_ring_emit_de_meta()
6088 uint32_t v = secure ? FRAME_TMZ : 0; in gfx_v11_0_ring_emit_frame_cntl()
6090 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); in gfx_v11_0_ring_emit_frame_cntl()
6091 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); in gfx_v11_0_ring_emit_frame_cntl()
6100 amdgpu_ring_write(ring, 0 | /* src: register*/ in gfx_v11_0_ring_emit_rreg()
6104 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_rreg()
6114 uint32_t cmd = 0; in gfx_v11_0_ring_emit_wreg()
6130 amdgpu_ring_write(ring, 0); in gfx_v11_0_ring_emit_wreg()
6137 gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); in gfx_v11_0_ring_emit_reg_wait()
6146 gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, in gfx_v11_0_ring_emit_reg_write_reg_wait()
6147 ref, mask, 0x20); in gfx_v11_0_ring_emit_reg_write_reg_wait()
6154 uint32_t value = 0; in gfx_v11_0_ring_soft_recovery()
6156 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); in gfx_v11_0_ring_soft_recovery()
6157 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); in gfx_v11_0_ring_soft_recovery()
6160 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); in gfx_v11_0_ring_soft_recovery()
6161 WREG32_SOC15(GC, 0, regSQ_CMD, value); in gfx_v11_0_ring_soft_recovery()
6162 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); in gfx_v11_0_ring_soft_recovery()
6174 case 0: in gfx_v11_0_set_gfx_eop_interrupt_state()
6175 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6178 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_set_gfx_eop_interrupt_state()
6193 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6195 GENERIC0_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6225 case 0: in gfx_v11_0_set_compute_eop_interrupt_state()
6226 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6229 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6232 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6235 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()
6250 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
6252 GENERIC0_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
6275 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); in gfx_v11_0_set_eop_interrupt_state()
6278 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); in gfx_v11_0_set_eop_interrupt_state()
6281 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state); in gfx_v11_0_set_eop_interrupt_state()
6295 return 0; in gfx_v11_0_set_eop_interrupt_state()
6305 uint32_t mes_queue_id = entry->src_data[0]; in gfx_v11_0_eop_irq()
6322 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v11_0_eop_irq()
6323 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v11_0_eop_irq()
6324 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v11_0_eop_irq()
6327 case 0: in gfx_v11_0_eop_irq()
6328 if (pipe_id == 0) in gfx_v11_0_eop_irq()
6329 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); in gfx_v11_0_eop_irq()
6335 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_eop_irq()
6350 return 0; in gfx_v11_0_eop_irq()
6364 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6365 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6372 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6377 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_priv_reg_fault_state()
6378 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_priv_reg_fault_state()
6386 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_reg_fault_state()
6396 return 0; in gfx_v11_0_set_priv_reg_fault_state()
6410 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_bad_op_fault_state()
6411 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_bad_op_fault_state()
6418 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6423 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_0_set_bad_op_fault_state()
6424 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_0_set_bad_op_fault_state()
6432 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_bad_op_fault_state()
6441 return 0; in gfx_v11_0_set_bad_op_fault_state()
6455 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_0_set_priv_inst_fault_state()
6456 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_0_set_priv_inst_fault_state()
6463 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v11_0_set_priv_inst_fault_state()
6473 return 0; in gfx_v11_0_set_priv_inst_fault_state()
6483 me_id = (entry->ring_id & 0x0c) >> 2; in gfx_v11_0_handle_priv_fault()
6484 pipe_id = (entry->ring_id & 0x03) >> 0; in gfx_v11_0_handle_priv_fault()
6485 queue_id = (entry->ring_id & 0x70) >> 4; in gfx_v11_0_handle_priv_fault()
6488 case 0: in gfx_v11_0_handle_priv_fault()
6489 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { in gfx_v11_0_handle_priv_fault()
6498 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_handle_priv_fault()
6517 return 0; in gfx_v11_0_priv_reg_irq()
6526 return 0; in gfx_v11_0_bad_op_irq()
6535 return 0; in gfx_v11_0_priv_inst_irq()
6545 return 0; in gfx_v11_0_rlc_gc_fed_irq()
6548 #if 0
6555 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6557 target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6563 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6565 GENERIC2_INT_ENABLE, 0);
6566 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6570 GENERIC2_INT_ENABLE, 0);
6573 tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6576 WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6588 return 0;
6606 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ in gfx_v11_0_emit_mem_sync()
6607 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ in gfx_v11_0_emit_mem_sync()
6608 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ in gfx_v11_0_emit_mem_sync()
6609 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ in gfx_v11_0_emit_mem_sync()
6610 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ in gfx_v11_0_emit_mem_sync()
6611 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ in gfx_v11_0_emit_mem_sync()
6628 if (unlikely(r != 0)) { in gfx_v11_0_reset_kgq()
6656 int r = 0; in gfx_v11_0_reset_kcq()
6668 if (unlikely(r != 0)) { in gfx_v11_0_reset_kcq()
6695 uint32_t i, j, k, reg, index = 0; in gfx_v11_ip_print()
6701 for (i = 0; i < reg_count; i++) in gfx_v11_ip_print()
6702 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6716 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_print()
6717 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_print()
6718 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
6720 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_print()
6721 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6734 index = 0; in gfx_v11_ip_print()
6741 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_print()
6742 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_print()
6743 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_print()
6745 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_print()
6746 drm_printf(p, "%-50s \t 0x%08x\n", in gfx_v11_ip_print()
6759 uint32_t i, j, k, reg, index = 0; in gfx_v11_ip_dump()
6766 for (i = 0; i < reg_count; i++) in gfx_v11_ip_dump()
6777 for (i = 0; i < adev->gfx.mec.num_mec; i++) { in gfx_v11_ip_dump()
6778 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { in gfx_v11_ip_dump()
6779 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()
6781 soc21_grbm_select(adev, adev->gfx.me.num_me + i, j, k, 0); in gfx_v11_ip_dump()
6782 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_dump()
6791 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_ip_dump()
6799 index = 0; in gfx_v11_ip_dump()
6803 for (i = 0; i < adev->gfx.me.num_me; i++) { in gfx_v11_ip_dump()
6804 for (j = 0; j < adev->gfx.me.num_pipe_per_me; j++) { in gfx_v11_ip_dump()
6805 for (k = 0; k < adev->gfx.me.num_queue_per_pipe; k++) { in gfx_v11_ip_dump()
6806 soc21_grbm_select(adev, i, j, k, 0); in gfx_v11_ip_dump()
6808 for (reg = 0; reg < reg_count; reg++) { in gfx_v11_ip_dump()
6817 soc21_grbm_select(adev, 0, 0, 0, 0); in gfx_v11_ip_dump()
6825 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); in gfx_v11_0_ring_emit_cleaner_shader()
6826 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ in gfx_v11_0_ring_emit_cleaner_shader()
6853 .align_mask = 0xff,
6854 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6909 .align_mask = 0xff,
6910 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6951 .align_mask = 0xff,
6952 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6982 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq; in gfx_v11_0_set_ring_funcs()
6984 for (i = 0; i < adev->gfx.num_gfx_rings; i++) in gfx_v11_0_set_ring_funcs()
6987 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_set_ring_funcs()
7029 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */ in gfx_v11_0_set_irq_funcs()
7055 adev->gds.gds_size = 0x1000; in gfx_v11_0_set_gds_init()
7086 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data); in gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh()
7092 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7093 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG); in gfx_v11_0_get_wgp_active_bitmap_per_sh()
7110 cu_active_bitmap = 0; in gfx_v11_0_get_cu_active_bitmap_per_sh()
7112 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { in gfx_v11_0_get_cu_active_bitmap_per_sh()
7125 int i, j, k, counter, active_cu_number = 0; in gfx_v11_0_get_cu_info()
7135 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { in gfx_v11_0_get_cu_info()
7136 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
7141 counter = 0; in gfx_v11_0_get_cu_info()
7142 gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); in gfx_v11_0_get_cu_info()
7154 * SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]} in gfx_v11_0_get_cu_info()
7155 * SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]} in gfx_v11_0_get_cu_info()
7156 * SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]} in gfx_v11_0_get_cu_info()
7157 * SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]} in gfx_v11_0_get_cu_info()
7158 * SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]} in gfx_v11_0_get_cu_info()
7163 cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; in gfx_v11_0_get_cu_info()
7165 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { in gfx_v11_0_get_cu_info()
7174 gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in gfx_v11_0_get_cu_info()
7180 return 0; in gfx_v11_0_get_cu_info()
7187 .minor = 0,
7188 .rev = 0,