Lines Matching +full:0 +full:xd800
27 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
28 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
29 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
30 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
31 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
32 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
33 #define MC_SEQ_MISC0__MT__HBM 0x60000000
34 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
39 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c)
40 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c)
41 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c)
42 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c)
43 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c)
44 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c)
47 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807)
48 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807)
49 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807)
50 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807)
51 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807)
52 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807)
54 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
55 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
57 #define PIPEID(x) ((x) << 0)
62 #define mmCC_DRM_ID_STRAPS 0x1559
63 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000
65 #define mmCHUB_CONTROL 0x619
66 #define BYPASS_VM (1 << 0)
68 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
70 #define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02
73 # define CURSOR_MONO 0
77 # define CURSOR_URGENT_ALWAYS 0
83 # define GRPH_DEPTH_8BPP 0
87 # define GRPH_FORMAT_INDEXED 0
89 # define GRPH_FORMAT_ARGB1555 0
96 # define GRPH_FORMAT_ARGB8888 0
104 # define ADDR_SURF_MACRO_TILE_ASPECT_1 0
108 # define GRPH_ARRAY_LINEAR_GENERAL 0
112 # define DISPLAY_MICRO_TILING 0
116 # define GRPH_ENDIAN_NONE 0
120 # define GRPH_RED_SEL_R 0
124 # define GRPH_GREEN_SEL_G 0
128 # define GRPH_BLUE_SEL_B 0
132 # define GRPH_ALPHA_SEL_A 0
136 # define INPUT_GAMMA_USE_LUT 0
141 # define INPUT_CSC_BYPASS 0
145 # define OUTPUT_CSC_BYPASS 0
152 # define DEGAMMA_BYPASS 0
155 # define GAMUT_REMAP_BYPASS 0
160 # define REGAMMA_BYPASS 0
166 # define FMT_CLAMP_6BPC 0
170 # define HDMI_24BIT_DEEP_COLOR 0
173 # define HDMI_ACR_HW 0
180 # define AFMT_AVI_INFO_Y_RGB 0
184 #define NO_AUTO 0
194 # define BANK_WIDTH(x) ((x) << 0)
200 #define MSG_EXIT_RLC_SAFE_MODE 0
205 #define PACKET_TYPE0 0
211 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
212 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
213 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
215 ((reg) & 0xFFFF) | \
216 ((n) & 0x3FFF) << 16)
217 #define CP_PACKET2 0x80000000
218 #define PACKET2_PAD_SHIFT 0
219 #define PACKET2_PAD_MASK (0x3fffffff << 0)
224 (((op) & 0xFF) << 8) | \
225 ((n) & 0x3FFF) << 16)
230 #define PACKET3_NOP 0x10
231 #define PACKET3_SET_BASE 0x11
232 #define PACKET3_BASE_INDEX(x) ((x) << 0)
234 #define PACKET3_CLEAR_STATE 0x12
235 #define PACKET3_INDEX_BUFFER_SIZE 0x13
236 #define PACKET3_DISPATCH_DIRECT 0x15
237 #define PACKET3_DISPATCH_INDIRECT 0x16
238 #define PACKET3_ATOMIC_GDS 0x1D
239 #define PACKET3_ATOMIC_MEM 0x1E
240 #define PACKET3_OCCLUSION_QUERY 0x1F
241 #define PACKET3_SET_PREDICATION 0x20
242 #define PACKET3_REG_RMW 0x21
243 #define PACKET3_COND_EXEC 0x22
244 #define PACKET3_PRED_EXEC 0x23
245 #define PACKET3_DRAW_INDIRECT 0x24
246 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
247 #define PACKET3_INDEX_BASE 0x26
248 #define PACKET3_DRAW_INDEX_2 0x27
249 #define PACKET3_CONTEXT_CONTROL 0x28
250 #define PACKET3_INDEX_TYPE 0x2A
251 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C
252 #define PACKET3_DRAW_INDEX_AUTO 0x2D
253 #define PACKET3_NUM_INSTANCES 0x2F
254 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
255 #define PACKET3_INDIRECT_BUFFER_CONST 0x33
256 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
257 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
258 #define PACKET3_DRAW_PREAMBLE 0x36
259 #define PACKET3_WRITE_DATA 0x37
261 /* 0 - register
271 /* 0 - LRU
275 /* 0 - me
279 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
280 #define PACKET3_MEM_SEMAPHORE 0x39
281 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
282 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
283 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
284 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
285 # define PACKET3_SEM_SEL_WAIT (0x7 << 29)
286 #define PACKET3_COPY_DW 0x3B
287 #define PACKET3_WAIT_REG_MEM 0x3C
288 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
289 /* 0 - always
298 /* 0 - reg
302 /* 0 - wait_reg_mem
306 /* 0 - me
309 #define PACKET3_INDIRECT_BUFFER 0x3F
313 /* 0 - LRU
317 #define PACKET3_COPY_DATA 0x40
318 #define PACKET3_PFP_SYNC_ME 0x42
319 #define PACKET3_SURFACE_SYNC 0x43
320 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
343 #define PACKET3_COND_WRITE 0x45
344 #define PACKET3_EVENT_WRITE 0x46
345 #define EVENT_TYPE(x) ((x) << 0)
347 /* 0 - any non-TS event
355 #define PACKET3_EVENT_WRITE_EOP 0x47
363 /* 0 - LRU
369 /* 0 - discard
376 /* 0 - none
377 * 1 - interrupt only (DATA_SEL = 0)
381 /* 0 - MC
384 #define PACKET3_EVENT_WRITE_EOS 0x48
385 #define PACKET3_RELEASE_MEM 0x49
386 #define PACKET3_PREAMBLE_CNTL 0x4A
389 #define PACKET3_DMA_DATA 0x50
392 * 3. SRC_ADDR_LO or DATA [31:0]
393 * 4. SRC_ADDR_HI [31:0]
394 * 5. DST_ADDR_LO [31:0]
395 * 6. DST_ADDR_HI [7:0]
396 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
399 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
400 /* 0 - ME
404 /* 0 - LRU
410 /* 0 - DST_ADDR using DAS
415 /* 0 - LRU
421 /* 0 - SRC_ADDR using SAS
430 /* 0 - none
436 /* 0 - none
442 /* 0 - memory
446 /* 0 - memory
452 #define PACKET3_ACQUIRE_MEM 0x58
453 #define PACKET3_REWIND 0x59
454 #define PACKET3_LOAD_UCONFIG_REG 0x5E
455 #define PACKET3_LOAD_SH_REG 0x5F
456 #define PACKET3_LOAD_CONFIG_REG 0x60
457 #define PACKET3_LOAD_CONTEXT_REG 0x61
458 #define PACKET3_SET_CONFIG_REG 0x68
459 #define PACKET3_SET_CONFIG_REG_START 0x00002000
460 #define PACKET3_SET_CONFIG_REG_END 0x00002c00
461 #define PACKET3_SET_CONTEXT_REG 0x69
462 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000
463 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400
464 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
465 #define PACKET3_SET_SH_REG 0x76
466 #define PACKET3_SET_SH_REG_START 0x00002c00
467 #define PACKET3_SET_SH_REG_END 0x00003000
468 #define PACKET3_SET_SH_REG_OFFSET 0x77
469 #define PACKET3_SET_QUEUE_REG 0x78
470 #define PACKET3_SET_UCONFIG_REG 0x79
471 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000
472 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400
473 #define PACKET3_SCRATCH_RAM_WRITE 0x7D
474 #define PACKET3_SCRATCH_RAM_READ 0x7E
475 #define PACKET3_LOAD_CONST_RAM 0x80
476 #define PACKET3_WRITE_CONST_RAM 0x81
477 #define PACKET3_DUMP_CONST_RAM 0x83
478 #define PACKET3_INCREMENT_CE_COUNTER 0x84
479 #define PACKET3_INCREMENT_DE_COUNTER 0x85
480 #define PACKET3_WAIT_ON_CE_COUNTER 0x86
481 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
482 #define PACKET3_SWITCH_BUFFER 0x8B
484 /* SDMA - first instance at 0xd000, second at 0xd800 */
485 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
486 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */
489 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
490 (((sub_op) & 0xFF) << 8) | \
491 (((op) & 0xFF) << 0))
493 #define SDMA_OPCODE_NOP 0
494 # define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16)
496 # define SDMA_COPY_SUB_OPCODE_LINEAR 0
503 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0
510 /* 0 - increment
514 /* 0 - wait
521 /* 0 - wait_reg_mem
525 /* 0 - always
534 /* 0 = register
540 /* 0 = byte fill
545 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
552 #define VCE_CMD_NO_OP 0x00000000
553 #define VCE_CMD_END 0x00000001
554 #define VCE_CMD_IB 0x00000002
555 #define VCE_CMD_FENCE 0x00000003
556 #define VCE_CMD_TRAP 0x00000004
557 #define VCE_CMD_IB_AUTO 0x00000005
558 #define VCE_CMD_SEMAPHORE 0x00000006
561 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */
568 MTYPE_CACHED = 0,
573 #define RB_MAP_PKR0(x) ((x) << 0)
574 #define RB_MAP_PKR0_MASK (0x3 << 0)
576 #define RB_MAP_PKR1_MASK (0x3 << 2)
578 #define RB_XSEL2_MASK (0x3 << 4)
582 #define PKR_MAP_MASK (0x3 << 8)
584 #define PKR_XSEL_MASK (0x3 << 10)
586 #define PKR_YSEL_MASK (0x3 << 12)
588 #define SC_MAP_MASK (0x3 << 16)
590 #define SC_XSEL_MASK (0x3 << 18)
592 #define SC_YSEL_MASK (0x3 << 20)
594 #define SE_MAP_MASK (0x3 << 24)
596 #define SE_XSEL_MASK (0x3 << 26)
598 #define SE_YSEL_MASK (0x3 << 28)
601 #define SE_PAIR_MAP(x) ((x) << 0)
602 #define SE_PAIR_MAP_MASK (0x3 << 0)
604 #define SE_PAIR_XSEL_MASK (0x3 << 2)
606 #define SE_PAIR_YSEL_MASK (0x3 << 4)