128  * add to control->i2c_address, and then tell I2C layer to read
172 				  struct amdgpu_ras_eeprom_control *control)  in __get_eeprom_i2c_addr()  argument
177 	if (!control)  in __get_eeprom_i2c_addr()
190 		control->i2c_address = ((u32) i2c_addr) << 16;  in __get_eeprom_i2c_addr()
199 			control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
203 			control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
205 			control->i2c_address = EEPROM_I2C_MADDR_4;  in __get_eeprom_i2c_addr()
208 		control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
213 			control->i2c_address = EEPROM_I2C_MADDR_4;  in __get_eeprom_i2c_addr()
215 			control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
220 			control->i2c_address = EEPROM_I2C_MADDR_0;  in __get_eeprom_i2c_addr()
222 			control->i2c_address = EEPROM_I2C_MADDR_4;  in __get_eeprom_i2c_addr()
227 		control->i2c_address = EEPROM_I2C_MADDR_4;  in __get_eeprom_i2c_addr()
260 static int __write_table_header(struct amdgpu_ras_eeprom_control *control)  in __write_table_header()  argument
263 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __write_table_header()
267 	__encode_table_header_to_buf(&control->tbl_hdr, buf);  in __write_table_header()
272 				  control->i2c_address +  in __write_table_header()
273 				  control->ras_header_offset,  in __write_table_header()
316 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control)  in __write_table_ras_info()  argument
318 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __write_table_ras_info()
328 	__encode_table_ras_info_to_buf(&control->tbl_rai, buf);  in __write_table_ras_info()
333 				  control->i2c_address +  in __write_table_ras_info()
334 				  control->ras_info_offset,  in __write_table_ras_info()
353 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control)  in __calc_hdr_byte_sum()  argument
360 	sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum);  in __calc_hdr_byte_sum()
361 	pp = (u8 *) &control->tbl_hdr;  in __calc_hdr_byte_sum()
369 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control)  in __calc_ras_info_byte_sum()  argument
375 	sz = sizeof(control->tbl_rai);  in __calc_ras_info_byte_sum()
376 	pp = (u8 *) &control->tbl_rai;  in __calc_ras_info_byte_sum()
385 	struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_correct_header_tag()  argument
388 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_correct_header_tag()
400 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
403 	res = __write_table_header(control);  in amdgpu_ras_eeprom_correct_header_tag()
404 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_correct_header_tag()
409 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_set_eeprom_table_version()  argument
411 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_set_eeprom_table_version()
412 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_set_eeprom_table_version()
427  * @control: pointer to control structure
432 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_reset_table()  argument
434 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_reset_table()
435 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_reset_table()
436 	struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;  in amdgpu_ras_eeprom_reset_table()
441 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
444 	amdgpu_ras_set_eeprom_table_version(control);  in amdgpu_ras_eeprom_reset_table()
463 	csum = __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_reset_table()
465 		csum += __calc_ras_info_byte_sum(control);  in amdgpu_ras_eeprom_reset_table()
468 	res = __write_table_header(control);  in amdgpu_ras_eeprom_reset_table()
470 		res = __write_table_ras_info(control);  in amdgpu_ras_eeprom_reset_table()
472 	control->ras_num_recs = 0;  in amdgpu_ras_eeprom_reset_table()
473 	control->ras_num_bad_pages = 0;  in amdgpu_ras_eeprom_reset_table()
474 	control->ras_fri = 0;  in amdgpu_ras_eeprom_reset_table()
476 	amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages);  in amdgpu_ras_eeprom_reset_table()
478 	control->bad_channel_bitmap = 0;  in amdgpu_ras_eeprom_reset_table()
479 	amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap);  in amdgpu_ras_eeprom_reset_table()
482 	amdgpu_ras_debugfs_set_ret_size(control);  in amdgpu_ras_eeprom_reset_table()
484 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_reset_table()
490 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,  in __encode_table_record_to_buf()  argument
518 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,  in __decode_table_record_from_buf()  argument
580  * @control: pointer to control structure
585  * The caller must hold the table mutex in @control.
588 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control,  in __amdgpu_ras_eeprom_write()  argument
591 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __amdgpu_ras_eeprom_write()
599 				  control->i2c_address +  in __amdgpu_ras_eeprom_write()
600 				  RAS_INDEX_TO_OFFSET(control, fri),  in __amdgpu_ras_eeprom_write()
620 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_append_table()  argument
624 	struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control));  in amdgpu_ras_eeprom_append_table()
625 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_append_table()
638 		__encode_table_record_to_buf(control, &record[i], pp);  in amdgpu_ras_eeprom_append_table()
641 		if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&  in amdgpu_ras_eeprom_append_table()
642 		    !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {  in amdgpu_ras_eeprom_append_table()
643 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;  in amdgpu_ras_eeprom_append_table()
652 	 * Let N = control->ras_max_num_record_count, then we have,  in amdgpu_ras_eeprom_append_table()
675 	a = control->ras_fri + control->ras_num_recs;  in amdgpu_ras_eeprom_append_table()
677 	if (b < control->ras_max_record_count) {  in amdgpu_ras_eeprom_append_table()
678 		res = __amdgpu_ras_eeprom_write(control, buf, a, num);  in amdgpu_ras_eeprom_append_table()
679 	} else if (a < control->ras_max_record_count) {  in amdgpu_ras_eeprom_append_table()
682 		g0 = control->ras_max_record_count - a;  in amdgpu_ras_eeprom_append_table()
683 		g1 = b % control->ras_max_record_count + 1;  in amdgpu_ras_eeprom_append_table()
684 		res = __amdgpu_ras_eeprom_write(control, buf, a, g0);  in amdgpu_ras_eeprom_append_table()
687 		res = __amdgpu_ras_eeprom_write(control,  in amdgpu_ras_eeprom_append_table()
692 		if (g1 > control->ras_fri)  in amdgpu_ras_eeprom_append_table()
693 			control->ras_fri = g1 % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
695 		a %= control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
696 		b %= control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
700 			res = __amdgpu_ras_eeprom_write(control, buf, a, num);  in amdgpu_ras_eeprom_append_table()
703 			if (b >= control->ras_fri)  in amdgpu_ras_eeprom_append_table()
704 				control->ras_fri = (b + 1) % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
712 			g0 = control->ras_max_record_count - a;  in amdgpu_ras_eeprom_append_table()
714 			res = __amdgpu_ras_eeprom_write(control, buf, a, g0);  in amdgpu_ras_eeprom_append_table()
717 			res = __amdgpu_ras_eeprom_write(control,  in amdgpu_ras_eeprom_append_table()
722 			control->ras_fri = g1 % control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
725 	control->ras_num_recs = 1 + (control->ras_max_record_count + b  in amdgpu_ras_eeprom_append_table()
726 				     - control->ras_fri)  in amdgpu_ras_eeprom_append_table()
727 		% control->ras_max_record_count;  in amdgpu_ras_eeprom_append_table()
729 	if (control->rec_type == AMDGPU_RAS_EEPROM_REC_PA)  in amdgpu_ras_eeprom_append_table()
730 		control->ras_num_bad_pages = control->ras_num_recs;  in amdgpu_ras_eeprom_append_table()
732 		control->ras_num_bad_pages =  in amdgpu_ras_eeprom_append_table()
733 			control->ras_num_recs * adev->umc.retire_unit;  in amdgpu_ras_eeprom_append_table()
740 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_update_header()  argument
742 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_update_header()
751 	    control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) {  in amdgpu_ras_eeprom_update_header()
754 			control->ras_num_bad_pages, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_update_header()
755 		control->tbl_hdr.header = RAS_TABLE_HDR_BAD;  in amdgpu_ras_eeprom_update_header()
756 		if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1) {  in amdgpu_ras_eeprom_update_header()
757 			control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD;  in amdgpu_ras_eeprom_update_header()
758 			control->tbl_rai.health_percent = 0;  in amdgpu_ras_eeprom_update_header()
768 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)  in amdgpu_ras_eeprom_update_header()
769 		control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +  in amdgpu_ras_eeprom_update_header()
771 					    control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
773 		control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE +  in amdgpu_ras_eeprom_update_header()
774 					    control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
775 	control->tbl_hdr.checksum = 0;  in amdgpu_ras_eeprom_update_header()
777 	buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in amdgpu_ras_eeprom_update_header()
778 	buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);  in amdgpu_ras_eeprom_update_header()
781 			  control->tbl_hdr.tbl_size);  in amdgpu_ras_eeprom_update_header()
788 				 control->i2c_address +  in amdgpu_ras_eeprom_update_header()
789 				 control->ras_record_offset,  in amdgpu_ras_eeprom_update_header()
808 	    control->tbl_hdr.version == RAS_TABLE_VER_V2_1 &&  in amdgpu_ras_eeprom_update_header()
809 	    control->ras_num_bad_pages < ras->bad_page_cnt_threshold)  in amdgpu_ras_eeprom_update_header()
810 		control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold -  in amdgpu_ras_eeprom_update_header()
811 						   control->ras_num_bad_pages) * 100) /  in amdgpu_ras_eeprom_update_header()
820 	csum += __calc_hdr_byte_sum(control);  in amdgpu_ras_eeprom_update_header()
821 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)  in amdgpu_ras_eeprom_update_header()
822 		csum += __calc_ras_info_byte_sum(control);  in amdgpu_ras_eeprom_update_header()
825 	control->tbl_hdr.checksum = csum;  in amdgpu_ras_eeprom_update_header()
826 	res = __write_table_header(control);  in amdgpu_ras_eeprom_update_header()
827 	if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1)  in amdgpu_ras_eeprom_update_header()
828 		res = __write_table_ras_info(control);  in amdgpu_ras_eeprom_update_header()
836  * @control: pointer to control structure
842  * can be appended is between 1 and control->ras_max_record_count,
847 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_append()  argument
851 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_append()
860 	} else if (num > control->ras_max_record_count) {  in amdgpu_ras_eeprom_append()
862 			  num, control->ras_max_record_count);  in amdgpu_ras_eeprom_append()
870 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_append()
872 	res = amdgpu_ras_eeprom_append_table(control, record, num);  in amdgpu_ras_eeprom_append()
874 		res = amdgpu_ras_eeprom_update_header(control);  in amdgpu_ras_eeprom_append()
876 		amdgpu_ras_debugfs_set_ret_size(control);  in amdgpu_ras_eeprom_append()
878 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_append()
889  * @control: pointer to control structure
894  * The caller must hold the table mutex in @control.
897 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,  in __amdgpu_ras_eeprom_read()  argument
900 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __amdgpu_ras_eeprom_read()
908 				 control->i2c_address +  in __amdgpu_ras_eeprom_read()
909 				 RAS_INDEX_TO_OFFSET(control, fri),  in __amdgpu_ras_eeprom_read()
930  * @control: pointer to control structure
939 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,  in amdgpu_ras_eeprom_read()  argument
943 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_read()
955 	} else if (num > control->ras_num_recs) {  in amdgpu_ras_eeprom_read()
957 			  num, control->ras_num_recs);  in amdgpu_ras_eeprom_read()
985 	g0 = control->ras_fri + num - 1;  in amdgpu_ras_eeprom_read()
986 	g1 = g0 % control->ras_max_record_count;  in amdgpu_ras_eeprom_read()
987 	if (g0 < control->ras_max_record_count) {  in amdgpu_ras_eeprom_read()
991 		g0 = control->ras_max_record_count - control->ras_fri;  in amdgpu_ras_eeprom_read()
995 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_read()
996 	res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0);  in amdgpu_ras_eeprom_read()
1000 		res = __amdgpu_ras_eeprom_read(control,  in amdgpu_ras_eeprom_read()
1013 		__decode_table_record_from_buf(control, &record[i], pp);  in amdgpu_ras_eeprom_read()
1016 		if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) &&  in amdgpu_ras_eeprom_read()
1017 		    !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) {  in amdgpu_ras_eeprom_read()
1018 			control->bad_channel_bitmap |= 1 << record[i].mem_channel;  in amdgpu_ras_eeprom_read()
1024 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_read()
1029 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_max_record_count()  argument
1032 	amdgpu_ras_set_eeprom_table_version(control);  in amdgpu_ras_eeprom_max_record_count()
1034 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)  in amdgpu_ras_eeprom_max_record_count()
1046 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;  in amdgpu_ras_debugfs_eeprom_size_read()  local
1053 	if (!ras || !control) {  in amdgpu_ras_debugfs_eeprom_size_read()
1057 			       RAS_TBL_SIZE_BYTES, control->ras_max_record_count);  in amdgpu_ras_debugfs_eeprom_size_read()
1094 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_debugfs_table_size()  argument
1097 		strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;  in amdgpu_ras_debugfs_table_size()
1100 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_debugfs_set_ret_size()  argument
1102 	struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,  in amdgpu_ras_debugfs_set_ret_size()
1107 		d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);  in amdgpu_ras_debugfs_set_ret_size()
1115 	struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;  in amdgpu_ras_debugfs_table_read()  local
1120 	mutex_lock(&control->ras_tbl_mutex);  in amdgpu_ras_debugfs_table_read()
1142 			 control->tbl_hdr.header,  in amdgpu_ras_debugfs_table_read()
1143 			 control->tbl_hdr.version,  in amdgpu_ras_debugfs_table_read()
1144 			 control->tbl_hdr.first_rec_offset,  in amdgpu_ras_debugfs_table_read()
1145 			 control->tbl_hdr.tbl_size,  in amdgpu_ras_debugfs_table_read()
1146 			 control->tbl_hdr.checksum);  in amdgpu_ras_debugfs_table_read()
1172 	data_len = amdgpu_ras_debugfs_table_size(control);  in amdgpu_ras_debugfs_table_read()
1188 		for ( ; size > 0 && s < control->ras_num_recs; s++) {  in amdgpu_ras_debugfs_table_read()
1189 			u32 ai = RAS_RI_TO_AI(control, s);  in amdgpu_ras_debugfs_table_read()
1192 			res = __amdgpu_ras_eeprom_read(control, dare, ai, 1);  in amdgpu_ras_debugfs_table_read()
1195 			__decode_table_record_from_buf(control, &record, dare);  in amdgpu_ras_debugfs_table_read()
1198 				 RAS_INDEX_TO_OFFSET(control, ai),  in amdgpu_ras_debugfs_table_read()
1220 	mutex_unlock(&control->ras_tbl_mutex);  in amdgpu_ras_debugfs_table_read()
1230 	struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL;  in amdgpu_ras_debugfs_eeprom_table_read()  local
1237 	if (!ras || !control) {  in amdgpu_ras_debugfs_eeprom_table_read()
1265  * @control: pointer to control structure
1273 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control)  in __verify_ras_table_checksum()  argument
1275 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __verify_ras_table_checksum()
1279 	if (control->tbl_hdr.version == RAS_TABLE_VER_V2_1)  in __verify_ras_table_checksum()
1282 			   control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in __verify_ras_table_checksum()
1285 			   control->ras_num_recs * RAS_TABLE_RECORD_SIZE;  in __verify_ras_table_checksum()
1294 				 control->i2c_address +  in __verify_ras_table_checksum()
1295 				 control->ras_header_offset,  in __verify_ras_table_checksum()
1314 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control)  in __read_table_ras_info()  argument
1316 	struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai;  in __read_table_ras_info()
1317 	struct amdgpu_device *adev = to_amdgpu_device(control);  in __read_table_ras_info()
1332 				 control->i2c_address + control->ras_info_offset,  in __read_table_ras_info()
1347 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_init()  argument
1349 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_init()
1351 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_init()
1364 	if (!__get_eeprom_i2c_addr(adev, control))  in amdgpu_ras_eeprom_init()
1367 	control->ras_header_offset = RAS_HDR_START;  in amdgpu_ras_eeprom_init()
1368 	control->ras_info_offset = RAS_TABLE_V2_1_INFO_START;  in amdgpu_ras_eeprom_init()
1369 	mutex_init(&control->ras_tbl_mutex);  in amdgpu_ras_eeprom_init()
1373 				 control->i2c_address + control->ras_header_offset,  in amdgpu_ras_eeprom_init()
1383 		control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr);  in amdgpu_ras_eeprom_init()
1384 		control->ras_record_offset = RAS_RECORD_START_V2_1;  in amdgpu_ras_eeprom_init()
1385 		control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1;  in amdgpu_ras_eeprom_init()
1387 		control->ras_num_recs = RAS_NUM_RECS(hdr);  in amdgpu_ras_eeprom_init()
1388 		control->ras_record_offset = RAS_RECORD_START;  in amdgpu_ras_eeprom_init()
1389 		control->ras_max_record_count = RAS_MAX_RECORD_COUNT;  in amdgpu_ras_eeprom_init()
1391 	control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset);  in amdgpu_ras_eeprom_init()
1396 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control)  in amdgpu_ras_eeprom_check()  argument
1398 	struct amdgpu_device *adev = to_amdgpu_device(control);  in amdgpu_ras_eeprom_check()
1399 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;  in amdgpu_ras_eeprom_check()
1410 	if (!__get_eeprom_i2c_addr(adev, control))  in amdgpu_ras_eeprom_check()
1413 	if (control->rec_type == AMDGPU_RAS_EEPROM_REC_PA)  in amdgpu_ras_eeprom_check()
1414 		control->ras_num_bad_pages = control->ras_num_recs;  in amdgpu_ras_eeprom_check()
1416 		control->ras_num_bad_pages =  in amdgpu_ras_eeprom_check()
1417 			control->ras_num_recs * adev->umc.retire_unit;  in amdgpu_ras_eeprom_check()
1421 				 control->ras_num_bad_pages);  in amdgpu_ras_eeprom_check()
1424 			res = __read_table_ras_info(control);  in amdgpu_ras_eeprom_check()
1429 		res = __verify_ras_table_checksum(control);  in amdgpu_ras_eeprom_check()
1436 		if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold)  in amdgpu_ras_eeprom_check()
1438 					control->ras_num_bad_pages,  in amdgpu_ras_eeprom_check()
1443 			res = __read_table_ras_info(control);  in amdgpu_ras_eeprom_check()
1448 		res = __verify_ras_table_checksum(control);  in amdgpu_ras_eeprom_check()
1454 		if (ras->bad_page_cnt_threshold > control->ras_num_bad_pages) {  in amdgpu_ras_eeprom_check()
1457 			 * ras->bad_page_cnt_threshold - control->num_recs > 0,  in amdgpu_ras_eeprom_check()
1464 				 control->ras_num_bad_pages,  in amdgpu_ras_eeprom_check()
1466 			res = amdgpu_ras_eeprom_correct_header_tag(control,  in amdgpu_ras_eeprom_check()
1470 				control->ras_num_bad_pages, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_check()
1479 					control->ras_num_bad_pages, ras->bad_page_cnt_threshold);  in amdgpu_ras_eeprom_check()
1485 		res = amdgpu_ras_eeprom_reset_table(control);  in amdgpu_ras_eeprom_check()