Lines Matching defs:amdgpu_crtc

458 struct amdgpu_crtc {  struct
459 	struct drm_crtc base;
460 	int crtc_id;
461 	bool enabled;
462 	bool can_tile;
463 	uint32_t crtc_offset;
464 	struct drm_gem_object *cursor_bo;
465 	uint64_t cursor_addr;
466 	int cursor_x;
467 	int cursor_y;
468 	int cursor_hot_x;
469 	int cursor_hot_y;
470 	int cursor_width;
471 	int cursor_height;
472 	int max_cursor_width;
473 	int max_cursor_height;
474 	enum amdgpu_rmx_type rmx_type;
475 	u8 h_border;
476 	u8 v_border;
477 	fixed20_12 vsc;
478 	fixed20_12 hsc;
479 	struct drm_display_mode native_mode;
480 	u32 pll_id;
482 	struct amdgpu_flip_work *pflip_works;
483 	enum amdgpu_flip_status pflip_status;
484 	int deferred_flip_completion;
486 	struct dm_irq_params dm_irq_params;
488 	struct amdgpu_atom_ss ss;
489 	bool ss_enabled;
490 	u32 adjusted_clock;
491 	int bpc;
492 	u32 pll_reference_div;
493 	u32 pll_post_div;
494 	u32 pll_flags;
495 	struct drm_encoder *encoder;
496 	struct drm_connector *connector;
498 	u32 line_time;
499 	u32 wm_low;
500 	u32 wm_high;
501 	u32 lb_vblank_lead_lines;
502 	struct drm_display_mode hw_mode;
504 	struct hrtimer vblank_timer;
505 	enum amdgpu_interrupt_state vsync_timer_enabled;
507 	int otg_inst;
508 	struct drm_pending_vblank_event *event;
510 	bool wb_pending;
511 	bool wb_enabled;
512 	struct drm_writeback_connector *wb_conn;