Lines Matching +full:auto +full:- +full:pm
58 * - 3.0.0 - initial driver
59 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
60 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
62 * - 3.3.0 - Add VM support for UVD on supported hardware.
63 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
64 * - 3.5.0 - Add support for new UVD_NO_OP register.
65 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
66 * - 3.7.0 - Add support for VCE clock list packet
67 * - 3.8.0 - Add support raster config init in the kernel
68 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
69 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
70 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
71 * - 3.12.0 - Add query for double offchip LDS buffers
72 * - 3.13.0 - Add PRT support
73 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
74 * - 3.15.0 - Export more gpu info for gfx9
75 * - 3.16.0 - Add reserved vmid support
76 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
77 * - 3.18.0 - Export gpu always on cu bitmap
78 * - 3.19.0 - Add support for UVD MJPEG decode
79 * - 3.20.0 - Add support for local BOs
80 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
81 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
82 * - 3.23.0 - Add query for VRAM lost counter
83 * - 3.24.0 - Add high priority compute support for gfx9
84 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
85 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
86 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
87 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
88 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
89 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
90 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
91 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
92 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
93 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
94 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
95 * - 3.36.0 - Allow reading more status registers on si/cik
96 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
97 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
98 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
99 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
100 * - 3.41.0 - Add video codec query
101 * - 3.42.0 - Add 16bpc fixed point display support
102 * - 3.43.0 - Add device hot plug/unplug support
103 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
104 * - 3.45.0 - Add context ioctl stable pstate interface
105 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
106 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
107 * - 3.48.0 - Add IP discovery version info to HW INFO
108 * - 3.49.0 - Add gang submit into CS IOCTL
109 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
111 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
112 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
115 * 3.53.0 - Support for GFX11 CP GFX shadowing
116 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
117 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
118 * - 3.56.0 - Update IB start address and size alignment for decode and encode
119 * - 3.57.0 - Compute tunneling on GFX10+
120 * - 3.58.0 - Add GFX12 DCC support
121 * - 3.59.0 - Cleared VRAM
122 * - 3.60.0 - Add AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE (Vulkan requirement)
123 * - 3.61.0 - Contains fix for RV/PCO compute queues
143 int amdgpu_gart_size = -1; /* auto */
144 int amdgpu_gtt_size = -1; /* auto */
145 int amdgpu_moverate = -1; /* auto */
146 int amdgpu_audio = -1;
149 int amdgpu_pcie_gen2 = -1;
150 int amdgpu_msi = -1;
152 int amdgpu_dpm = -1;
153 int amdgpu_fw_load_type = -1;
154 int amdgpu_aspm = -1;
155 int amdgpu_runtime_pm = -1;
157 int amdgpu_bapm = -1;
159 int amdgpu_vm_size = -1;
160 int amdgpu_vm_fragment_size = -1;
161 int amdgpu_vm_block_size = -1;
163 int amdgpu_vm_update_mode = -1;
165 int amdgpu_dc = -1;
192 int amdgpu_lbpw = -1;
193 int amdgpu_compute_multipipe = -1;
194 int amdgpu_gpu_recovery = -1; /* auto */
197 int amdgpu_smu_pptable_id = -1;
201 * - With this, for multiple monitors in sync(e.g. with the same model),
212 int amdgpu_mcbp = -1;
213 int amdgpu_discovery = -1;
218 int amdgpu_noretry = -1;
219 int amdgpu_force_asic_type = -1;
220 int amdgpu_tmz = -1; /* auto */
222 int amdgpu_reset_method = -1; /* auto */
223 int amdgpu_num_kcq = -1;
227 int amdgpu_sg_display = -1; /* auto */
230 int amdgpu_seamless = -1; /* auto */
232 int amdgpu_agp = -1; /* auto */
233 int amdgpu_wbrf = -1;
234 int amdgpu_damage_clips = -1; /* auto */
252 int amdgpu_ras_enable = -1;
254 int amdgpu_bad_page_threshold = -1;
277 * The default is -1 (The size depends on asic).
279 MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
285 * The default is -1 (Use value specified by TTM).
287 MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
292 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
294 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disa…
299 …* Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to di…
301 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
306 …play Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto…
308 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
313 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
320 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
322 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
327 …gnaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
329 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
343 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
347 * - With one value specified, the setting will apply to all non-compute jobs.
348 * - With multiple values specified, the first one will be for GFX.
352 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
355 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-c…
356 …keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Comp…
364 * The default is -1 (auto).
366 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
373 * to -1 to select the default loading mode for the ASIC, as defined
374 * by the driver. The default is -1 (auto).
376 …if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
381 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
383 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
389 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
391 * Setting the value to -2 is auto enabled with power down when displays are attached.
393 …PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = dis…
409 * The default -1 (auto, enabled)
411 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
416 …* Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disa…
423 …* Override the size of the GPU's per client virtual address space in GiB. The default is -1 (auto…
430 …* Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for…
437 …le size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each…
452 …* is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, neve…
466 …* Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (a…
468 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
560 …oad Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
562 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)…
565 …_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
570 …* Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disable…
572 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)…
584 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
586 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (d…
668 …* It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default…
671 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
677 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
722 * do not support per-process XNACK this also disables retry page faults.
723 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
726 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
749 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
750 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
756 …"Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for de…
763 int hws_max_conc_proc = -1;
858 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
863 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
888 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
889 * default. Values 1-4 control the maximum allowable brightness reduction via
893 * Defaults to -1, or auto. Userspace can only override this level after
894 * boot if it's set to auto.
896 int amdgpu_dm_abm_level = -1;
898 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))");
901 int amdgpu_backlight = -1;
902 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
911 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected).
914 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))");
922 * The default value: 0 (off). TODO: change to auto till it is completed.
924 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
955 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
957 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = m…
966 …bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad pag…
986 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
1011 …"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft p…
1020 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
1040 MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
1047 * - 0x1: Debug VM handling
1048 * - 0x2: Enable simulating large-bar capability on non-large bar system. This
1051 * - 0x4: Disable GPU soft recovery, always do a full reset
1060 * are non-snooped, so they are only used for access to uncached memory.
1062 MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
1069 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
1071 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
1072 * on active list of frequencies in-use (to be avoided) as part of initial setting or
1073 * P-state transition. However, there may be potential performance impact with this
1075 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
1078 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
2172 /* 0 - GPU in amdgpu_get_secondary_funcs()
2173 * 1 - audio in amdgpu_get_secondary_funcs()
2174 * 2 - USB in amdgpu_get_secondary_funcs()
2175 * 3 - UCSI in amdgpu_get_secondary_funcs()
2178 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), in amdgpu_get_secondary_funcs()
2179 adev->pdev->bus->number, i); in amdgpu_get_secondary_funcs()
2181 pm_runtime_get_sync(&p->dev); in amdgpu_get_secondary_funcs()
2182 pm_runtime_mark_last_busy(&p->dev); in amdgpu_get_secondary_funcs()
2183 pm_runtime_put_autosuspend(&p->dev); in amdgpu_get_secondary_funcs()
2193 adev->debug_vm = true; in amdgpu_init_debug_options()
2197 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n"); in amdgpu_init_debug_options()
2198 adev->debug_largebar = true; in amdgpu_init_debug_options()
2203 adev->debug_disable_soft_recovery = true; in amdgpu_init_debug_options()
2208 adev->debug_use_vram_fw_buf = true; in amdgpu_init_debug_options()
2213 adev->debug_enable_ras_aca = true; in amdgpu_init_debug_options()
2218 adev->debug_exp_resets = true; in amdgpu_init_debug_options()
2227 if (pdev->device == asic_type_quirks[i].device && in amdgpu_fix_asic_type()
2228 pdev->revision == asic_type_quirks[i].revision) { in amdgpu_fix_asic_type()
2243 unsigned long flags = ent->driver_data; in amdgpu_pci_probe()
2249 if (amdgpu_unsupported_pciidlist[i] == pdev->device) in amdgpu_pci_probe()
2250 return -ENODEV; in amdgpu_pci_probe()
2253 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) in amdgpu_pci_probe()
2263 return -ENODEV; in amdgpu_pci_probe()
2274 dev_info(&pdev->dev, in amdgpu_pci_probe()
2276 return -ENOTSUPP; in amdgpu_pci_probe()
2287 dev_info(&pdev->dev, in amdgpu_pci_probe()
2289 dev_info(&pdev->dev, in amdgpu_pci_probe()
2292 return -ENODEV; in amdgpu_pci_probe()
2296 dev_info(&pdev->dev, "amdgpu is built without SI support.\n"); in amdgpu_pci_probe()
2297 return -ENODEV; in amdgpu_pci_probe()
2306 dev_info(&pdev->dev, in amdgpu_pci_probe()
2308 dev_info(&pdev->dev, in amdgpu_pci_probe()
2311 return -ENODEV; in amdgpu_pci_probe()
2315 dev_info(&pdev->dev, "amdgpu is built without CIK support.\n"); in amdgpu_pci_probe()
2316 return -ENODEV; in amdgpu_pci_probe()
2322 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); in amdgpu_pci_probe()
2326 adev->dev = &pdev->dev; in amdgpu_pci_probe()
2327 adev->pdev = pdev; in amdgpu_pci_probe()
2331 ddev->driver_features &= ~DRIVER_ATOMIC; in amdgpu_pci_probe()
2347 if (ret == -EAGAIN && ++retry <= 3) { in amdgpu_pci_probe()
2368 if (adev->mode_info.mode_config_initialized && in amdgpu_pci_probe()
2369 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { in amdgpu_pci_probe()
2373 if (adev->gmc.real_vram_size <= (32*1024*1024)) in amdgpu_pci_probe()
2385 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { in amdgpu_pci_probe()
2388 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); in amdgpu_pci_probe()
2391 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | in amdgpu_pci_probe()
2394 pm_runtime_use_autosuspend(ddev->dev); in amdgpu_pci_probe()
2395 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); in amdgpu_pci_probe()
2397 pm_runtime_allow(ddev->dev); in amdgpu_pci_probe()
2399 pm_runtime_mark_last_busy(ddev->dev); in amdgpu_pci_probe()
2400 pm_runtime_put_autosuspend(ddev->dev); in amdgpu_pci_probe()
2407 * - put ASIC into BACO state only when both video and in amdgpu_pci_probe()
2409 * - pull ASIC out of BACO state when either video or in amdgpu_pci_probe()
2416 * be no PMFW-aware D-state transition(D0->D3) on runpm in amdgpu_pci_probe()
2420 * into D0 state. Then there will be a PMFW-aware D-state in amdgpu_pci_probe()
2421 * transition(D0->D3) on runpm suspend. in amdgpu_pci_probe()
2424 !(adev->flags & AMD_IS_APU) && in amdgpu_pci_probe()
2425 (adev->asic_type >= CHIP_NAVI10)) in amdgpu_pci_probe()
2446 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { in amdgpu_pci_remove()
2447 pm_runtime_get_sync(dev->dev); in amdgpu_pci_remove()
2448 pm_runtime_forbid(dev->dev); in amdgpu_pci_remove()
2477 adev->mp1_state = PP_MP1_STATE_UNLOAD; in amdgpu_pci_shutdown()
2479 adev->mp1_state = PP_MP1_STATE_NONE; in amdgpu_pci_shutdown()
2515 adev->in_s0ix = true; in amdgpu_pmops_suspend()
2517 adev->in_s3 = true; in amdgpu_pmops_suspend()
2518 if (!adev->in_s0ix && !adev->in_s3) in amdgpu_pmops_suspend()
2540 if (!adev->in_s0ix && !adev->in_s3) in amdgpu_pmops_resume()
2544 if (!pci_device_is_present(adev->pdev)) in amdgpu_pmops_resume()
2545 adev->no_hw_access = true; in amdgpu_pmops_resume()
2549 adev->in_s0ix = false; in amdgpu_pmops_resume()
2551 adev->in_s3 = false; in amdgpu_pmops_resume()
2577 adev->in_s4 = false; in amdgpu_pmops_thaw()
2594 adev->in_s4 = false; in amdgpu_pmops_restore()
2605 if (adev->mode_info.num_crtc) { in amdgpu_runtime_idle_check_display()
2610 if (amdgpu_runtime_pm != -2) { in amdgpu_runtime_idle_check_display()
2616 mutex_lock(&drm_dev->mode_config.mutex); in amdgpu_runtime_idle_check_display()
2619 if (list_connector->status == connector_status_connected) { in amdgpu_runtime_idle_check_display()
2620 ret = -EBUSY; in amdgpu_runtime_idle_check_display()
2625 mutex_unlock(&drm_dev->mode_config.mutex); in amdgpu_runtime_idle_check_display()
2631 if (adev->dc_enabled) { in amdgpu_runtime_idle_check_display()
2635 drm_modeset_lock(&crtc->mutex, NULL); in amdgpu_runtime_idle_check_display()
2636 if (crtc->state->active) in amdgpu_runtime_idle_check_display()
2637 ret = -EBUSY; in amdgpu_runtime_idle_check_display()
2638 drm_modeset_unlock(&crtc->mutex); in amdgpu_runtime_idle_check_display()
2643 mutex_lock(&drm_dev->mode_config.mutex); in amdgpu_runtime_idle_check_display()
2644 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); in amdgpu_runtime_idle_check_display()
2648 if (list_connector->dpms == DRM_MODE_DPMS_ON) { in amdgpu_runtime_idle_check_display()
2649 ret = -EBUSY; in amdgpu_runtime_idle_check_display()
2656 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); in amdgpu_runtime_idle_check_display()
2657 mutex_unlock(&drm_dev->mode_config.mutex); in amdgpu_runtime_idle_check_display()
2673 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { in amdgpu_pmops_runtime_suspend()
2675 return -EBUSY; in amdgpu_pmops_runtime_suspend()
2684 struct amdgpu_ring *ring = adev->rings[i]; in amdgpu_pmops_runtime_suspend()
2686 if (ring && ring->sched.ready) { in amdgpu_pmops_runtime_suspend()
2689 return -EBUSY; in amdgpu_pmops_runtime_suspend()
2693 adev->in_runpm = true; in amdgpu_pmops_runtime_suspend()
2694 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) in amdgpu_pmops_runtime_suspend()
2695 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; in amdgpu_pmops_runtime_suspend()
2704 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) in amdgpu_pmops_runtime_suspend()
2705 adev->mp1_state = PP_MP1_STATE_UNLOAD; in amdgpu_pmops_runtime_suspend()
2712 adev->in_runpm = false; in amdgpu_pmops_runtime_suspend()
2713 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) in amdgpu_pmops_runtime_suspend()
2714 adev->mp1_state = PP_MP1_STATE_NONE; in amdgpu_pmops_runtime_suspend()
2718 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) in amdgpu_pmops_runtime_suspend()
2719 adev->mp1_state = PP_MP1_STATE_NONE; in amdgpu_pmops_runtime_suspend()
2721 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { in amdgpu_pmops_runtime_suspend()
2729 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; in amdgpu_pmops_runtime_suspend()
2730 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { in amdgpu_pmops_runtime_suspend()
2732 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || in amdgpu_pmops_runtime_suspend()
2733 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { in amdgpu_pmops_runtime_suspend()
2737 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); in amdgpu_pmops_runtime_suspend()
2749 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) in amdgpu_pmops_runtime_resume()
2750 return -EINVAL; in amdgpu_pmops_runtime_resume()
2753 if (!pci_device_is_present(adev->pdev)) in amdgpu_pmops_runtime_resume()
2754 adev->no_hw_access = true; in amdgpu_pmops_runtime_resume()
2756 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) { in amdgpu_pmops_runtime_resume()
2757 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; in amdgpu_pmops_runtime_resume()
2768 } else if (adev->pm.rpm_mode == AMDGPU_RUNPM_BOCO) { in amdgpu_pmops_runtime_resume()
2773 } else if ((adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) || in amdgpu_pmops_runtime_resume()
2774 (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)) { in amdgpu_pmops_runtime_resume()
2779 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) in amdgpu_pmops_runtime_resume()
2784 if (adev->pm.rpm_mode == AMDGPU_RUNPM_PX) in amdgpu_pmops_runtime_resume()
2785 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; in amdgpu_pmops_runtime_resume()
2786 adev->in_runpm = false; in amdgpu_pmops_runtime_resume()
2796 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { in amdgpu_pmops_runtime_idle()
2798 return -EBUSY; in amdgpu_pmops_runtime_idle()
2811 struct drm_file *file_priv = filp->private_data; in amdgpu_drm_ioctl()
2815 dev = file_priv->minor->dev; in amdgpu_drm_ioctl()
2816 ret = pm_runtime_get_sync(dev->dev); in amdgpu_drm_ioctl()
2822 pm_runtime_mark_last_busy(dev->dev); in amdgpu_drm_ioctl()
2824 pm_runtime_put_autosuspend(dev->dev); in amdgpu_drm_ioctl()
2845 struct drm_file *file_priv = f->private_data; in amdgpu_flush()
2846 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; in amdgpu_flush()
2849 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); in amdgpu_flush()
2850 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); in amdgpu_flush()
2878 return -EINVAL; in amdgpu_file_to_fpriv()
2880 if (filp->f_op != &amdgpu_driver_kms_fops) in amdgpu_file_to_fpriv()
2881 return -EINVAL; in amdgpu_file_to_fpriv()
2883 file = filp->private_data; in amdgpu_file_to_fpriv()
2884 *fpriv = file->driver_priv; in amdgpu_file_to_fpriv()
2979 .driver.pm = &amdgpu_pm_ops,
2989 return -EINVAL; in amdgpu_init()