Lines Matching +full:cc +full:- +full:debounce +full:- +full:time +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2022 NVIDIA Corporation
19 #include <dt-bindings/gpio/tegra186-gpio.h>
20 #include <dt-bindings/gpio/tegra194-gpio.h>
21 #include <dt-bindings/gpio/tegra234-gpio.h>
22 #include <dt-bindings/gpio/tegra241-gpio.h>
116 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_get_port()
117 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_get_port()
119 if (*pin >= start && *pin < start + port->pins) { in tegra186_gpio_get_port()
120 *pin -= start; in tegra186_gpio_get_port()
124 start += port->pins; in tegra186_gpio_get_port()
140 offset = port->bank * 0x1000 + port->port * 0x200; in tegra186_gpio_get_base()
142 return gpio->base + offset + pin * 0x20; in tegra186_gpio_get_base()
155 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; in tegra186_gpio_get_secure_base()
157 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; in tegra186_gpio_get_secure_base()
167 if (gpio->soc->has_vm_support) { in tegra186_gpio_is_accessible()
214 return -ENODEV; in tegra186_gpio_get_direction()
232 return -ENODEV; in tegra186_gpio_direction_input()
254 chip->set(chip, offset, level); in tegra186_gpio_direction_output()
258 return -EINVAL; in tegra186_gpio_direction_output()
283 return -EINVAL; in tegra186_gpio_en_hw_ts()
287 return -ENODEV; in tegra186_gpio_en_hw_ts()
291 return -EINVAL; in tegra186_gpio_en_hw_ts()
318 return -EINVAL; in tegra186_gpio_dis_hw_ts()
322 return -ENODEV; in tegra186_gpio_dis_hw_ts()
326 return -EINVAL; in tegra186_gpio_dis_hw_ts()
351 return -ENODEV; in tegra186_gpio_get()
387 u32 debounce, value; in tegra186_gpio_set_config() local
392 return -ENXIO; in tegra186_gpio_set_config()
395 return -ENOTSUPP; in tegra186_gpio_set_config()
397 debounce = pinconf_to_config_argument(config); in tegra186_gpio_set_config()
400 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce in tegra186_gpio_set_config()
401 * time. in tegra186_gpio_set_config()
403 if (debounce > 255000) in tegra186_gpio_set_config()
404 return -EINVAL; in tegra186_gpio_set_config()
406 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); in tegra186_gpio_set_config()
408 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); in tegra186_gpio_set_config()
426 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) in tegra186_gpio_add_pin_ranges()
429 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); in tegra186_gpio_add_pin_ranges()
431 return -ENODEV; in tegra186_gpio_add_pin_ranges()
436 return -EPROBE_DEFER; in tegra186_gpio_add_pin_ranges()
438 for (i = 0; i < gpio->soc->num_pin_ranges; i++) { in tegra186_gpio_add_pin_ranges()
439 unsigned int pin = gpio->soc->pin_ranges[i].offset, port; in tegra186_gpio_add_pin_ranges()
440 const char *group = gpio->soc->pin_ranges[i].group; in tegra186_gpio_add_pin_ranges()
445 if (port >= gpio->soc->num_ports) { in tegra186_gpio_add_pin_ranges()
446 dev_warn(chip->parent, "invalid port %u for %s\n", in tegra186_gpio_add_pin_ranges()
452 pin += gpio->soc->ports[j].pins; in tegra186_gpio_add_pin_ranges()
469 if (WARN_ON(chip->of_gpio_n_cells < 2)) in tegra186_gpio_of_xlate()
470 return -EINVAL; in tegra186_gpio_of_xlate()
472 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) in tegra186_gpio_of_xlate()
473 return -EINVAL; in tegra186_gpio_of_xlate()
475 port = spec->args[0] / 8; in tegra186_gpio_of_xlate()
476 pin = spec->args[0] % 8; in tegra186_gpio_of_xlate()
478 if (port >= gpio->soc->num_ports) { in tegra186_gpio_of_xlate()
479 dev_err(chip->parent, "invalid port number: %u\n", port); in tegra186_gpio_of_xlate()
480 return -EINVAL; in tegra186_gpio_of_xlate()
484 offset += gpio->soc->ports[i].pins; in tegra186_gpio_of_xlate()
487 *flags = spec->args[1]; in tegra186_gpio_of_xlate()
500 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_ack()
514 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_mask()
522 gpiochip_disable_irq(&gpio->gpio, data->hwirq); in tegra186_irq_mask()
532 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_unmask()
536 gpiochip_enable_irq(&gpio->gpio, data->hwirq); in tegra186_irq_unmask()
550 base = tegra186_gpio_get_base(gpio, data->hwirq); in tegra186_irq_set_type()
552 return -ENODEV; in tegra186_irq_set_type()
585 return -EINVAL; in tegra186_irq_set_type()
595 if (data->parent_data) in tegra186_irq_set_type()
603 if (data->parent_data) in tegra186_irq_set_wake()
613 seq_puts(p, dev_name(gc->parent)); in tegra186_irq_print_chip()
630 struct irq_domain *domain = gpio->gpio.irq.domain; in tegra186_gpio_irq()
637 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_irq()
638 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_irq()
643 base = gpio->base + port->bank * 0x1000 + port->port * 0x200; in tegra186_gpio_irq()
646 for (j = 0; j < gpio->num_irqs_per_bank; j++) { in tegra186_gpio_irq()
647 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j]) in tegra186_gpio_irq()
651 if (j == gpio->num_irqs_per_bank) in tegra186_gpio_irq()
656 for_each_set_bit(pin, &value, port->pins) { in tegra186_gpio_irq()
662 offset += port->pins; in tegra186_gpio_irq()
673 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); in tegra186_gpio_irq_domain_translate()
676 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) in tegra186_gpio_irq_domain_translate()
677 return -EINVAL; in tegra186_gpio_irq_domain_translate()
679 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) in tegra186_gpio_irq_domain_translate()
680 return -EINVAL; in tegra186_gpio_irq_domain_translate()
682 port = fwspec->param[0] / 8; in tegra186_gpio_irq_domain_translate()
683 pin = fwspec->param[0] % 8; in tegra186_gpio_irq_domain_translate()
685 if (port >= gpio->soc->num_ports) in tegra186_gpio_irq_domain_translate()
686 return -EINVAL; in tegra186_gpio_irq_domain_translate()
689 offset += gpio->soc->ports[i].pins; in tegra186_gpio_irq_domain_translate()
691 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; in tegra186_gpio_irq_domain_translate()
703 struct irq_fwspec *fwspec = &gfwspec->fwspec; in tegra186_gpio_populate_parent_fwspec()
705 fwspec->fwnode = chip->irq.parent_domain->fwnode; in tegra186_gpio_populate_parent_fwspec()
706 fwspec->param_count = 3; in tegra186_gpio_populate_parent_fwspec()
707 fwspec->param[0] = gpio->soc->instance; in tegra186_gpio_populate_parent_fwspec()
708 fwspec->param[1] = parent_hwirq; in tegra186_gpio_populate_parent_fwspec()
709 fwspec->param[2] = parent_type; in tegra186_gpio_populate_parent_fwspec()
720 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); in tegra186_gpio_child_to_parent_hwirq()
732 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_child_offset_to_irq()
733 if (offset < gpio->soc->ports[i].pins) in tegra186_gpio_child_offset_to_irq()
736 offset -= gpio->soc->ports[i].pins; in tegra186_gpio_child_offset_to_irq()
743 { .compatible = "nvidia,tegra186-pmc" },
744 { .compatible = "nvidia,tegra194-pmc" },
745 { .compatible = "nvidia,tegra234-pmc" },
751 struct device *dev = gpio->gpio.parent; in tegra186_gpio_init_route_mapping()
755 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_init_route_mapping()
756 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_init_route_mapping()
757 unsigned int offset, p = port->port; in tegra186_gpio_init_route_mapping()
760 base = gpio->secure + port->bank * 0x1000 + 0x800; in tegra186_gpio_init_route_mapping()
775 port->name); in tegra186_gpio_init_route_mapping()
789 value = BIT(port->pins) - 1; in tegra186_gpio_init_route_mapping()
797 struct device *dev = gpio->gpio.parent; in tegra186_gpio_irqs_per_bank()
799 if (gpio->num_irq > gpio->num_banks) { in tegra186_gpio_irqs_per_bank()
800 if (gpio->num_irq % gpio->num_banks != 0) in tegra186_gpio_irqs_per_bank()
804 if (gpio->num_irq < gpio->num_banks) in tegra186_gpio_irqs_per_bank()
807 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks; in tegra186_gpio_irqs_per_bank()
809 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank) in tegra186_gpio_irqs_per_bank()
816 gpio->num_irq, gpio->num_banks); in tegra186_gpio_irqs_per_bank()
817 return -EINVAL; in tegra186_gpio_irqs_per_bank()
830 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in tegra186_gpio_probe()
832 return -ENOMEM; in tegra186_gpio_probe()
834 gpio->soc = device_get_match_data(&pdev->dev); in tegra186_gpio_probe()
835 gpio->gpio.label = gpio->soc->name; in tegra186_gpio_probe()
836 gpio->gpio.parent = &pdev->dev; in tegra186_gpio_probe()
839 for (i = 0; i < gpio->soc->num_ports; i++) in tegra186_gpio_probe()
840 if (gpio->soc->ports[i].bank > gpio->num_banks) in tegra186_gpio_probe()
841 gpio->num_banks = gpio->soc->ports[i].bank; in tegra186_gpio_probe()
843 gpio->num_banks++; in tegra186_gpio_probe()
849 gpio->secure = devm_ioremap_resource(&pdev->dev, res); in tegra186_gpio_probe()
850 if (IS_ERR(gpio->secure)) in tegra186_gpio_probe()
851 return PTR_ERR(gpio->secure); in tegra186_gpio_probe()
856 gpio->base = devm_ioremap_resource(&pdev->dev, res); in tegra186_gpio_probe()
857 if (IS_ERR(gpio->base)) in tegra186_gpio_probe()
858 return PTR_ERR(gpio->base); in tegra186_gpio_probe()
864 gpio->num_irq = err; in tegra186_gpio_probe()
870 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), in tegra186_gpio_probe()
872 if (!gpio->irq) in tegra186_gpio_probe()
873 return -ENOMEM; in tegra186_gpio_probe()
875 for (i = 0; i < gpio->num_irq; i++) { in tegra186_gpio_probe()
880 gpio->irq[i] = err; in tegra186_gpio_probe()
883 gpio->gpio.request = gpiochip_generic_request; in tegra186_gpio_probe()
884 gpio->gpio.free = gpiochip_generic_free; in tegra186_gpio_probe()
885 gpio->gpio.get_direction = tegra186_gpio_get_direction; in tegra186_gpio_probe()
886 gpio->gpio.direction_input = tegra186_gpio_direction_input; in tegra186_gpio_probe()
887 gpio->gpio.direction_output = tegra186_gpio_direction_output; in tegra186_gpio_probe()
888 gpio->gpio.get = tegra186_gpio_get; in tegra186_gpio_probe()
889 gpio->gpio.set = tegra186_gpio_set; in tegra186_gpio_probe()
890 gpio->gpio.set_config = tegra186_gpio_set_config; in tegra186_gpio_probe()
891 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; in tegra186_gpio_probe()
892 gpio->gpio.init_valid_mask = tegra186_init_valid_mask; in tegra186_gpio_probe()
893 if (gpio->soc->has_gte) { in tegra186_gpio_probe()
894 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; in tegra186_gpio_probe()
895 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; in tegra186_gpio_probe()
898 gpio->gpio.base = -1; in tegra186_gpio_probe()
900 for (i = 0; i < gpio->soc->num_ports; i++) in tegra186_gpio_probe()
901 gpio->gpio.ngpio += gpio->soc->ports[i].pins; in tegra186_gpio_probe()
903 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, in tegra186_gpio_probe()
906 return -ENOMEM; in tegra186_gpio_probe()
908 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_probe()
909 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_probe()
912 for (j = 0; j < port->pins; j++) { in tegra186_gpio_probe()
913 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, in tegra186_gpio_probe()
914 "P%s.%02x", port->name, j); in tegra186_gpio_probe()
916 return -ENOMEM; in tegra186_gpio_probe()
921 offset += port->pins; in tegra186_gpio_probe()
924 gpio->gpio.names = (const char * const *)names; in tegra186_gpio_probe()
927 gpio->gpio.of_gpio_n_cells = 2; in tegra186_gpio_probe()
928 gpio->gpio.of_xlate = tegra186_gpio_of_xlate; in tegra186_gpio_probe()
931 irq = &gpio->gpio.irq; in tegra186_gpio_probe()
933 irq->fwnode = dev_fwnode(&pdev->dev); in tegra186_gpio_probe()
934 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; in tegra186_gpio_probe()
935 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; in tegra186_gpio_probe()
936 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; in tegra186_gpio_probe()
937 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; in tegra186_gpio_probe()
938 irq->handler = handle_simple_irq; in tegra186_gpio_probe()
939 irq->default_type = IRQ_TYPE_NONE; in tegra186_gpio_probe()
940 irq->parent_handler = tegra186_gpio_irq; in tegra186_gpio_probe()
941 irq->parent_handler_data = gpio; in tegra186_gpio_probe()
942 irq->num_parents = gpio->num_irq; in tegra186_gpio_probe()
951 if (gpio->num_irqs_per_bank > 1) { in tegra186_gpio_probe()
952 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks, in tegra186_gpio_probe()
953 sizeof(*irq->parents), GFP_KERNEL); in tegra186_gpio_probe()
954 if (!irq->parents) in tegra186_gpio_probe()
955 return -ENOMEM; in tegra186_gpio_probe()
957 for (i = 0; i < gpio->num_banks; i++) in tegra186_gpio_probe()
958 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank]; in tegra186_gpio_probe()
960 irq->num_parents = gpio->num_banks; in tegra186_gpio_probe()
962 irq->num_parents = gpio->num_irq; in tegra186_gpio_probe()
963 irq->parents = gpio->irq; in tegra186_gpio_probe()
966 if (gpio->soc->num_irqs_per_bank > 1) in tegra186_gpio_probe()
972 irq->parent_domain = irq_find_host(np); in tegra186_gpio_probe()
975 if (!irq->parent_domain) in tegra186_gpio_probe()
976 return -EPROBE_DEFER; in tegra186_gpio_probe()
982 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, in tegra186_gpio_probe()
983 sizeof(*irq->map), GFP_KERNEL); in tegra186_gpio_probe()
984 if (!irq->map) in tegra186_gpio_probe()
985 return -ENOMEM; in tegra186_gpio_probe()
987 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_probe()
988 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_probe()
990 for (j = 0; j < port->pins; j++) in tegra186_gpio_probe()
991 irq->map[offset + j] = irq->parents[port->bank]; in tegra186_gpio_probe()
993 offset += port->pins; in tegra186_gpio_probe()
996 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); in tegra186_gpio_probe()
1030 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
1036 .name = "tegra186-gpio",
1064 .name = "tegra186-gpio-aon",
1117 .name = "tegra194-gpio",
1122 .pinmux = "nvidia,tegra194-pinmux",
1137 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1145 .name = "tegra194-gpio-aon",
1191 .name = "tegra234-gpio",
1208 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1217 .name = "tegra234-gpio-aon",
1249 .name = "tegra241-gpio",
1271 .name = "tegra241-gpio-aon",
1279 .compatible = "nvidia,tegra186-gpio",
1282 .compatible = "nvidia,tegra186-gpio-aon",
1285 .compatible = "nvidia,tegra194-gpio",
1288 .compatible = "nvidia,tegra194-gpio-aon",
1291 .compatible = "nvidia,tegra234-gpio",
1294 .compatible = "nvidia,tegra234-gpio-aon",
1315 .name = "tegra186-gpio",