Lines Matching +full:ports +full:- +full:block +full:- +full:group +full:- +full:count
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
25 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/fpga/fpga-region.h>
32 /* maximum supported number of ports */
37 /* Reserved 0xfe for Header Group Register and 0xff for AFU */
90 #define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */
95 * 1'b1 = absolute (ARM or other non-PCIe use)
104 #define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */
106 #define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */
140 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
150 /* AFU MMIO access permission. 1 - VF, 0 - PF. */
213 * struct dfl_fpga_port_ops - port ops
236 * struct dfl_feature_id - dfl private feature id
245 * struct dfl_feature_driver - dfl private feature driver
256 * struct dfl_feature_irq_ctx - dfl private feature interrupt context
269 * struct dfl_feature - sub feature of the feature devices
303 #define FEATURE_DEV_ID_UNUSED (-1)
306 * struct dfl_feature_dev_data - dfl enumeration data for dfl feature dev.
316 * @disable_count: count for port disable.
318 * @open_count: count for feature device open.
345 * struct dfl_feature_platform_data - platform data for feature devices
359 if (fdata->excl_open) in dfl_feature_dev_use_begin()
360 return -EBUSY; in dfl_feature_dev_use_begin()
363 if (fdata->open_count) in dfl_feature_dev_use_begin()
364 return -EBUSY; in dfl_feature_dev_use_begin()
366 fdata->excl_open = true; in dfl_feature_dev_use_begin()
368 fdata->open_count++; in dfl_feature_dev_use_begin()
376 fdata->excl_open = false; in dfl_feature_dev_use_end()
378 if (WARN_ON(fdata->open_count <= 0)) in dfl_feature_dev_use_end()
381 fdata->open_count--; in dfl_feature_dev_use_end()
387 return fdata->open_count; in dfl_feature_dev_use_count()
394 fdata->private = private; in dfl_fpga_fdata_set_private()
400 return fdata->private; in dfl_fpga_fdata_get_private()
411 #define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
412 #define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
428 pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data, in dfl_fpga_inode_to_feature_dev_data()
430 return pdata->fdata; in dfl_fpga_inode_to_feature_dev_data()
434 for ((feature) = (fdata)->features; \
435 (feature) < (fdata)->features + (fdata)->num; (feature)++)
443 if (feature->id == id) in dfl_get_feature_by_id()
454 if (feature && feature->ioaddr) in dfl_get_feature_ioaddr_by_id()
455 return feature->ioaddr; in dfl_get_feature_ioaddr_by_id()
466 return pdata->fdata; in to_dfl_feature_dev_data()
472 return fdata->dev->dev.parent->parent; in dfl_fpga_fdata_to_parent()
497 * struct dfl_fpga_enum_info - DFL FPGA enumeration information
512 * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
532 * struct dfl_fpga_cdev - container device of DFL based FPGA
564 mutex_lock(&cdev->lock); in dfl_fpga_cdev_find_port_data()
566 mutex_unlock(&cdev->lock); in dfl_fpga_cdev_find_port_data()
576 unsigned int count, int32_t *fds);