Lines Matching +full:packet +full:- +full:processor
1 /* SPDX-License-Identifier: BSD-3-Clause */
7 * See: https://software-dl.ti.com/tisci/esd/latest/index.html for details
9 * Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/
61 /* PSI-L requests */
81 /* Processor Control requests */
90 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
111 * struct ti_sci_msg_resp_version - Response for a message
133 * struct ti_sci_msg_req_reboot - Reboot the SoC
144 * struct ti_sci_msg_resp_query_fw_caps - Response for query firmware caps
165 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
172 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
176 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
177 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
187 /* Additional hdr->flags options */
202 * struct ti_sci_msg_req_get_device_state - Request to get device.
215 * struct ti_sci_msg_resp_get_device_state - Response to get device request.
222 * - Uses the MSG_DEVICE_SW_* macros
239 * struct ti_sci_msg_req_set_device_resets - Set the desired resets
258 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
266 * is only applicable to clock inputs on the SoC pseudo-device.
295 /* Additional hdr->flags options */
310 * struct ti_sci_msg_req_get_clock_state - Request for clock state
332 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
351 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
377 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
397 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
413 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
435 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
452 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
486 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
499 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
524 * Calling set frequency on a clock input to the SoC pseudo-device will
528 * Calling set frequency on clock outputs from the SoC pseudo-device will
545 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
566 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
578 * struct tisci_msg_req_prepare_sleep - Request for TISCI_MSG_PREPARE_SLEEP.
582 * @ctx_lo Low 32-bits of physical pointer to address to use for context save.
583 * @ctx_hi High 32-bits of physical pointer to address to use for context save.
589 * easily shared from the application, as this is a non-secure message and
603 * struct tisci_msg_set_io_isolation_req - Request for TI_SCI_MSG_SET_IO_ISOLATION.
617 * struct ti_sci_msg_resp_lpm_wake_reason - Response for TI_SCI_MSG_LPM_WAKE_REASON.
639 * struct ti_sci_msg_req_lpm_set_device_constraint - Request for
651 * is a non-secure message and therefore can be sent by anyone. By setting a
665 * struct ti_sci_msg_req_lpm_set_latency_constraint - Request for
678 * from the application, as this is a non-secure message and therefore can be sent by
692 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
715 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
733 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route
740 * 0 - Valid bit for @dst_id
741 * 1 - Valid bit for @dst_host_irq
742 * 2 - Valid bit for @ia_id
743 * 3 - Valid bit for @vint
744 * 4 - Valid bit for @global_event
745 * 5 - Valid bit for @vint_status_bit_index
746 * 31 - Valid bit for @secondary_host
750 * IRQ controller or host processor ID.
789 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
791 * Configures the non-real-time registers of a Navigator Subsystem ring.
797 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
798 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
799 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
800 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
801 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
802 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
803 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid
804 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL
815 * the formula (log2(size_bytes) - 2), where size_bytes cannot be
838 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
841 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
843 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
849 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
850 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
868 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
871 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
873 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
878 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
879 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
896 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
901 * @flow_index: UDMAP receive flow index for non-optional configuration.
903 * @rx_einfo_present: UDMAP receive flow extended packet info present.
909 * @rx_sop_offset: UDMAP receive flow start of packet offset.
912 * 0 - end of packet descriptor
913 * 1 - Beginning of the data buffer
922 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue
960 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive
967 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0.
968 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1.
969 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2.
995 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
1006 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
1007 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
1008 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
1009 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
1010 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
1011 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
1012 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
1013 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
1014 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
1015 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
1016 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
1017 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
1018 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
1019 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
1020 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
1021 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
1022 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
1032 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
1048 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
1052 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
1089 * 0 - Return immediately
1090 * 1 - Wait for completion message from remote peer
1093 * 0 - the channel is split tx channel (tchan)
1094 * 1 - the channel is block copy channel (bchan)
1123 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
1135 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
1136 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
1137 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
1138 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
1139 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
1140 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
1141 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
1142 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
1143 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
1144 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
1145 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
1146 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
1147 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
1148 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
1154 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
1209 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1212 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1243 * Configuration does not include the flow registers which handle size-based
1255 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1256 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
1257 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
1258 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
1259 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
1260 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
1261 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
1262 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
1263 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
1264 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
1265 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
1266 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
1267 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
1268 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
1269 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
1270 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
1271 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
1272 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
1273 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
1278 * @flow_index: UDMAP receive flow index for non-optional configuration.
1281 * UDMAP receive flow extended packet info present configuration to be
1297 * UDMAP receive flow start of packet offset configuration to be programmed
1300 * this field are 0-255 bytes.
1412 * struct ti_sci_msg_req_proc_request - Request a processor
1414 * @processor_id: ID of processor being requested
1425 * struct ti_sci_msg_req_proc_release - Release a processor
1427 * @processor_id: ID of processor being released
1438 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
1440 * @processor_id: ID of processor being handed over
1458 * struct ti_sci_msg_req_set_config - Set Processor boot configuration
1460 * @processor_id: ID of processor being configured
1463 * @config_flags_set: Optional Processor specific Config Flags to set.
1466 * @config_flags_clear: Optional Processor specific Config Flags to clear.
1483 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags
1485 * @processor_id: ID of processor being configured
1486 * @control_flags_set: Optional Processor specific Control Flags to set.
1489 * @control_flags_clear:Optional Processor specific Control Flags to clear.
1504 * struct ti_sci_msg_req_get_status - Processor boot status request
1506 * @processor_id: ID of processor whose status is being requested
1517 * struct ti_sci_msg_resp_get_status - Processor boot status response
1519 * @processor_id: ID of processor whose status is returned
1522 * @config_flags: Optional Processor specific Config Flags set currently
1523 * @control_flags: Optional Processor specific Control Flags set currently
1524 * @status_flags: Optional Processor specific Status Flags set currently