228 	void __iomem *ddrmc_baseaddr;  member
255 	ddrmc_base = priv->ddrmc_baseaddr;  in get_ce_error_info()
287 	ddrmc_base = priv->ddrmc_baseaddr;  in get_ue_error_info()
318 	ddrmc_base = priv->ddrmc_baseaddr;  in get_error_info()
465 	regval = readl(priv->ddrmc_baseaddr + XDDR_ISR_OFFSET);  in err_callback()
478 	writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in err_callback()
481 	writel(regval, priv->ddrmc_baseaddr + XDDR_ISR_OFFSET);  in err_callback()
484 	writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in err_callback()
558 	regval = readl(priv->ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);  in get_memsize()
608 			dimm->dtype = get_dwidth(priv->ddrmc_baseaddr);  in init_csrows()
646 	writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in enable_intr()
650 	       priv->ddrmc_baseaddr + XDDR_IRQ_EN_OFFSET);  in enable_intr()
653 	       priv->ddrmc_baseaddr + XDDR_IRQ1_EN_OFFSET);  in enable_intr()
655 	writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in enable_intr()
661 	writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in disable_intr()
665 	       priv->ddrmc_baseaddr + XDDR_IRQ_DIS_OFFSET);  in disable_intr()
668 	writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in disable_intr()
719 		writel(0xFF, priv->ddrmc_baseaddr + ECCW1_FLIP_CTRL);  in poison_setup()
721 		writel(0xFF, priv->ddrmc_baseaddr + ECCW0_FLIP_CTRL);  in poison_setup()
757 	writel(ecc0_flip0, priv->ddrmc_baseaddr + ECCW0_FLIP0_OFFSET);  in xddr_inject_data_ce_store()
758 	writel(ecc1_flip0, priv->ddrmc_baseaddr + ECCW1_FLIP0_OFFSET);  in xddr_inject_data_ce_store()
759 	writel(ecc0_flip1, priv->ddrmc_baseaddr + ECCW0_FLIP1_OFFSET);  in xddr_inject_data_ce_store()
760 	writel(ecc1_flip1, priv->ddrmc_baseaddr + ECCW1_FLIP1_OFFSET);  in xddr_inject_data_ce_store()
798 	writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in inject_data_ce_store()
807 	writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in inject_data_ce_store()
823 	writel(val0, priv->ddrmc_baseaddr + ECCW0_FLIP0_OFFSET);  in xddr_inject_data_ue_store()
824 	writel(val0, priv->ddrmc_baseaddr + ECCW0_FLIP1_OFFSET);  in xddr_inject_data_ue_store()
825 	writel(val1, priv->ddrmc_baseaddr + ECCW1_FLIP1_OFFSET);  in xddr_inject_data_ue_store()
826 	writel(val1, priv->ddrmc_baseaddr + ECCW1_FLIP1_OFFSET);  in xddr_inject_data_ue_store()
894 	writel(PCSR_UNLOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in inject_data_ue_store()
903 	writel(PCSR_LOCK_VAL, priv->ddrmc_baseaddr + XDDR_PCSR_OFFSET);  in inject_data_ue_store()
1078 	void __iomem *ddrmc_baseaddr, *ddrmc_noc_baseaddr;  in mc_probe()  local
1086 	ddrmc_baseaddr = devm_platform_ioremap_resource_byname(pdev, "base");  in mc_probe()
1087 	if (IS_ERR(ddrmc_baseaddr))  in mc_probe()
1088 		return PTR_ERR(ddrmc_baseaddr);  in mc_probe()
1094 	if (!get_ecc_state(ddrmc_baseaddr))  in mc_probe()
1100 	regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET);  in mc_probe()
1125 	priv->ddrmc_baseaddr = ddrmc_baseaddr;  in mc_probe()