1 // SPDX-License-Identifier: GPL-2.0-only
3  * Intel E3-1200
6  * Support for the E3-1200 processor family. Heavily based on previous
12  * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
14  * 0108: Xeon E3-1200 Processor Family DRAM Controller
15  * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16  * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17  * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18  * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
19  * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20  * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
21  * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
22  * 590f: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
23  * 5918: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
24  * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
25  * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
29 …* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-dat…
30  * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
31 …ps://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-d…
32 …* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-dat…
33 …* https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-l…
34 …* https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datash…
38  * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
44  * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
53 #include <linux/io-64-nonatomic-lo-hi.h>
74 /* Coffee Lake-S */
101 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
119  *  9    LOCK to non-DRAM Memory Flag (LCKF)
123  *  1    Multi-bit DRAM ECC Error Flag (DMERR)
124  *  0    Single-bit DRAM ECC Error Flag (DSERR)
180 	(n << (28 + (2 * skl) - PAGE_SHIFT))
234 	/* check DDPCD - check if both channels are filled */  in how_many_channels()
265 	pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,  in ie31200_clear_error_info()
273 	struct ie31200_priv *priv = mci->pvt_info;  in ie31200_get_and_clear_error_info()
275 	pdev = to_pci_dev(mci->pdev);  in ie31200_get_and_clear_error_info()
282 	pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);  in ie31200_get_and_clear_error_info()
283 	if (!(info->errsts & IE31200_ERRSTS_BITS))  in ie31200_get_and_clear_error_info()
286 	info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
288 		info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);  in ie31200_get_and_clear_error_info()
290 	pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);  in ie31200_get_and_clear_error_info()
298 	if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {  in ie31200_get_and_clear_error_info()
299 		info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);  in ie31200_get_and_clear_error_info()
301 			info->eccerrlog[1] =  in ie31200_get_and_clear_error_info()
302 				lo_hi_readq(priv->c1errlog);  in ie31200_get_and_clear_error_info()
314 	if (!(info->errsts & IE31200_ERRSTS_BITS))  in ie31200_process_error_info()
317 	if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {  in ie31200_process_error_info()
319 				     -1, -1, -1, "UE overwrote CE", "");  in ie31200_process_error_info()
320 		info->errsts = info->errsts2;  in ie31200_process_error_info()
324 		log = info->eccerrlog[channel];  in ie31200_process_error_info()
329 					     channel, -1,  in ie31200_process_error_info()
336 					     channel, -1,  in ie31200_process_error_info()
382 	dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE_SKL;  in __skl_populate_dimm_info()
383 	dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;  in __skl_populate_dimm_info()
384 	dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>  in __skl_populate_dimm_info()
391 	dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;  in __populate_dimm_info()
392 	dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;  in __populate_dimm_info()
393 	dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;  in __populate_dimm_info()
417 	 * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit  in ie31200_probe1()
420 	bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device);  in ie31200_probe1()
426 		return -ENODEV;  in ie31200_probe1()
439 		return -ENOMEM;  in ie31200_probe1()
443 		ret = -ENODEV;  in ie31200_probe1()
448 	mci->pdev = &pdev->dev;  in ie31200_probe1()
450 		mci->mtype_cap = MEM_FLAG_DDR4;  in ie31200_probe1()
452 		mci->mtype_cap = MEM_FLAG_DDR3;  in ie31200_probe1()
453 	mci->edac_ctl_cap = EDAC_FLAG_SECDED;  in ie31200_probe1()
454 	mci->edac_cap = EDAC_FLAG_SECDED;  in ie31200_probe1()
455 	mci->mod_name = EDAC_MOD_STR;  in ie31200_probe1()
456 	mci->ctl_name = ie31200_devs[dev_idx].ctl_name;  in ie31200_probe1()
457 	mci->dev_name = pci_name(pdev);  in ie31200_probe1()
458 	mci->edac_check = ie31200_check;  in ie31200_probe1()
459 	mci->ctl_page_to_phys = NULL;  in ie31200_probe1()
460 	priv = mci->pvt_info;  in ie31200_probe1()
461 	priv->window = window;  in ie31200_probe1()
463 		priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;  in ie31200_probe1()
464 		priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;  in ie31200_probe1()
467 		priv->c0errlog = window + IE31200_C0ECCERRLOG;  in ie31200_probe1()
468 		priv->c1errlog = window + IE31200_C1ECCERRLOG;  in ie31200_probe1()
505 				dimm->nr_pages = nr_pages;  in ie31200_probe1()
507 				dimm->grain = 8; /* just a guess */  in ie31200_probe1()
509 					dimm->mtype = MEM_DDR4;  in ie31200_probe1()
511 					dimm->mtype = MEM_DDR3;  in ie31200_probe1()
512 				dimm->dtype = DEV_UNKNOWN;  in ie31200_probe1()
513 				dimm->edac_mode = EDAC_UNKNOWN;  in ie31200_probe1()
516 			dimm->nr_pages = nr_pages;  in ie31200_probe1()
518 			dimm->grain = 8; /* same guess */  in ie31200_probe1()
520 				dimm->mtype = MEM_DDR4;  in ie31200_probe1()
522 				dimm->mtype = MEM_DDR3;  in ie31200_probe1()
523 			dimm->dtype = DEV_UNKNOWN;  in ie31200_probe1()
524 			dimm->edac_mode = EDAC_UNKNOWN;  in ie31200_probe1()
532 		ret = -ENODEV;  in ie31200_probe1()
556 		return -EIO;  in ie31200_init_one()
557 	rc = ie31200_probe1(pdev, ent->driver_data);  in ie31200_init_one()
572 	mci = edac_mc_del_mc(&pdev->dev);  in ie31200_remove_one()
575 	priv = mci->pvt_info;  in ie31200_remove_one()
576 	iounmap(priv->window);  in ie31200_remove_one()
638 			pci_rc = -ENODEV;  in ie31200_init()
645 			pci_rc = -ENODEV;  in ie31200_init()