69 #define I3200_C0DRB	0x200	/* Channel 0 DRAM Rank Boundary (16b x 4)
72 		 *  9:0  Channel 0 DRAM Rank Boundary Address
74 #define I3200_C1DRB	0x600	/* Channel 1 DRAM Rank Boundary (16b x 4) */
83 		 * 28:27 Error Rank Address (ERRRANK)
137 	u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >>  in eccerrlog_row()  local
139 	return rank | (channel * I3200_RANKS_PER_CHANNEL);  in eccerrlog_row()
317 	int channel, int rank)  in drb_to_nr_pages()  argument
321 	n = drbs[channel][rank];  in drb_to_nr_pages()
325 	if (rank > 0)  in drb_to_nr_pages()
326 		n -= drbs[channel][rank - 1];  in drb_to_nr_pages()
328 	drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1])  in drb_to_nr_pages()
385 	 * The dram rank boundary (DRB) reg values are boundary addresses  in i3200_probe1()
386 	 * for each DRAM rank with a granularity of 64MB.  DRB regs are  in i3200_probe1()