Lines Matching +full:scrubber +full:- +full:done
1 // SPDX-License-Identifier: GPL-2.0-only
11 * cleared to prevent re-enabling the hardware by this driver.
20 if (!pvt->flags.zn_regs_v2) in get_umc_reg()
32 /* Per-node stuff */
39 * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing
40 * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching-
82 func, PCI_FUNC(pdev->devfn), offset); in __amd64_read_pci_cfg_dword()
95 func, PCI_FUNC(pdev->devfn), offset); in __amd64_write_pci_cfg_dword()
107 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct()
108 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct()
110 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct()
120 * DCT0 -> F2x040..
121 * DCT1 -> F2x140..
130 switch (pvt->fam) { in amd64_read_dct_pci_cfg()
133 return -EINVAL; in amd64_read_dct_pci_cfg()
155 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
161 return -EINVAL; in amd64_read_dct_pci_cfg()
167 return amd64_read_pci_cfg(pvt->F2, offset, val); in amd64_read_dct_pci_cfg()
171 * Memory scrubber control interface. For K8, memory scrubbing is handled by
180 * Currently, we only do dram scrubbing. If the scrubbing is done in software on
202 for (i = 0; i < ARRAY_SIZE(scrubrates) - 1; i++) { in __set_scrub_rate()
216 if (pvt->fam == 0x15 && pvt->model == 0x60) { in __set_scrub_rate()
218 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
220 pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
222 pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F); in __set_scrub_rate()
233 struct amd64_pvt *pvt = mci->pvt_info; in set_scrub_rate()
236 if (pvt->fam == 0xf) in set_scrub_rate()
239 if (pvt->fam == 0x15) { in set_scrub_rate()
241 if (pvt->model < 0x10) in set_scrub_rate()
244 if (pvt->model == 0x60) in set_scrub_rate()
252 struct amd64_pvt *pvt = mci->pvt_info; in get_scrub_rate()
253 int i, retval = -EINVAL; in get_scrub_rate()
256 if (pvt->fam == 0x15) { in get_scrub_rate()
258 if (pvt->model < 0x10) in get_scrub_rate()
261 if (pvt->model == 0x60) in get_scrub_rate()
262 amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval); in get_scrub_rate()
264 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
266 amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval); in get_scrub_rate()
288 /* The K8 treats this as a 40-bit value. However, bits 63-40 will be in base_limit_match()
290 * Here we discard bits 63-40. See section 3.4.2 of AMD publication in base_limit_match()
291 * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 in base_limit_match()
317 pvt = mci->pvt_info; in find_mc_by_sys_addr()
379 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in get_cs_base_and_mask()
380 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
381 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
390 } else if (pvt->fam == 0x16 || in get_cs_base_and_mask()
391 (pvt->fam == 0x15 && pvt->model >= 0x30)) { in get_cs_base_and_mask()
392 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
393 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
408 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
409 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
412 if (pvt->fam == 0x15) in get_cs_base_and_mask()
430 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
433 pvt->csels[dct].csbases[i]
436 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
439 for (i = 0; i < pvt->max_mcs; i++)
443 * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr).
451 pvt = mci->pvt_info; in input_addr_to_csrow()
464 pvt->mc_node_id); in input_addr_to_csrow()
470 (unsigned long)input_addr, pvt->mc_node_id); in input_addr_to_csrow()
472 return -1; in input_addr_to_csrow()
481 * - The revision of the node is not E or greater. In this case, the DRAM Hole
484 * - The DramHoleValid bit is cleared in the DRAM Hole Address Register,
488 * complete 32-bit values despite the fact that the bitfields in the DHAR
489 * only represent bits 31-24 of the base and offset values.
494 struct amd64_pvt *pvt = mci->pvt_info; in get_dram_hole_info()
497 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) { in get_dram_hole_info()
499 pvt->ext_model, pvt->mc_node_id); in get_dram_hole_info()
504 if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) { in get_dram_hole_info()
511 pvt->mc_node_id); in get_dram_hole_info()
517 /* +------------------+--------------------+--------------------+----- in get_dram_hole_info()
519 * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | in get_dram_hole_info()
523 * | | | (0xffffffff-x))] | in get_dram_hole_info()
524 * +------------------+--------------------+--------------------+----- in get_dram_hole_info()
534 *hole_size = (1ULL << 32) - *hole_base; in get_dram_hole_info()
536 *hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt) in get_dram_hole_info()
540 pvt->mc_node_id, (unsigned long)*hole_base, in get_dram_hole_info()
552 struct amd64_pvt *pvt = mci->pvt_info; \
554 return sprintf(data, "0x%016llx\n", (u64)pvt->reg); \
603 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_show()
604 return sprintf(buf, "0x%x\n", pvt->injection.section); in inject_section_show()
608 * store error injection section value which refers to one of 4 16-byte sections
609 * within a 64-byte cacheline
618 struct amd64_pvt *pvt = mci->pvt_info; in inject_section_store()
628 return -EINVAL; in inject_section_store()
631 pvt->injection.section = (u32) value; in inject_section_store()
639 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_show()
640 return sprintf(buf, "0x%x\n", pvt->injection.word); in inject_word_show()
644 * store error injection word value which refers to one of 9 16-bit word of the
645 * 16-byte (128-bit + ECC bits) section
654 struct amd64_pvt *pvt = mci->pvt_info; in inject_word_store()
664 return -EINVAL; in inject_word_store()
667 pvt->injection.word = (u32) value; in inject_word_store()
676 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_show()
677 return sprintf(buf, "0x%x\n", pvt->injection.bit_map); in inject_ecc_vector_show()
690 struct amd64_pvt *pvt = mci->pvt_info; in inject_ecc_vector_store()
700 return -EINVAL; in inject_ecc_vector_store()
703 pvt->injection.bit_map = (u32) value; in inject_ecc_vector_store()
716 struct amd64_pvt *pvt = mci->pvt_info; in inject_read_store()
725 /* Form value to choose 16-byte section of cacheline */ in inject_read_store()
726 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_read_store()
728 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_read_store()
730 word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection); in inject_read_store()
733 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_read_store()
749 struct amd64_pvt *pvt = mci->pvt_info; in inject_write_store()
758 /* Form value to choose 16-byte section of cacheline */ in inject_write_store()
759 section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section); in inject_write_store()
761 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section); in inject_write_store()
763 word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection); in inject_write_store()
772 amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits); in inject_write_store()
776 amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp); in inject_write_store()
812 struct amd64_pvt *pvt = mci->pvt_info; in inj_is_visible()
815 if (pvt->fam >= 0x10 && pvt->fam <= 0x16) in inj_is_visible()
816 return attr->mode; in inj_is_visible()
858 struct amd64_pvt *pvt = mci->pvt_info; in sys_addr_to_dram_addr()
862 dram_base = get_dram_base(pvt, pvt->mc_node_id); in sys_addr_to_dram_addr()
869 dram_addr = sys_addr - hole_offset; in sys_addr_to_dram_addr()
881 * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 in sys_addr_to_dram_addr()
882 * only deals with 40-bit values. Therefore we discard bits 63-40 of in sys_addr_to_dram_addr()
885 * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture in sys_addr_to_dram_addr()
888 dram_addr = (sys_addr & GENMASK_ULL(39, 0)) - dram_base; in sys_addr_to_dram_addr()
917 pvt = mci->pvt_info; in dram_addr_to_input_addr()
920 * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) in dram_addr_to_input_addr()
955 err->page = (u32) (error_address >> PAGE_SHIFT); in error_address_to_page_and_offset()
956 err->offset = ((u32) error_address) & ~PAGE_MASK; in error_address_to_page_and_offset()
964 * the error). Return the number of the csrow that sys_addr maps to, or -1 on
973 if (csrow == -1) in sys_addr_to_csrow()
1007 * Mapping of nodes from hardware-provided AMD Node ID to a in gpu_get_node_map()
1011 if (pvt->F3->device != PCI_DEVICE_ID_AMD_MI200_DF_F3) in gpu_get_node_map()
1015 * Node ID 0 is reserved for CPUs. Therefore, a non-zero Node ID in gpu_get_node_map()
1023 ret = -ENODEV; in gpu_get_node_map()
1044 u8 nid = (m->ipid >> 44) & 0xF; in fixup_node_id()
1046 if (smca_get_bank_type(m->extcpu, m->bank) != SMCA_UMC_V2) in fixup_node_id()
1053 /* Convert the hardware-provided AMD Node ID to a Linux logical one. */ in fixup_node_id()
1054 return nid - gpu_node_map.base_node_id + 1; in fixup_node_id()
1068 bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F) in dct_determine_edac_cap()
1072 if (pvt->dclr0 & BIT(bit)) in dct_determine_edac_cap()
1084 if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT)) in umc_determine_edac_cap()
1090 if (pvt->umc[i].umc_cfg & BIT(12)) in umc_determine_edac_cap()
1106 u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
1107 u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; in dct_debug_display_dimm_sizes()
1110 if (pvt->fam == 0xf) { in dct_debug_display_dimm_sizes()
1112 if (pvt->ext_model < K8_REV_F) in dct_debug_display_dimm_sizes()
1118 if (pvt->fam == 0x10) { in dct_debug_display_dimm_sizes()
1119 dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 in dct_debug_display_dimm_sizes()
1120 : pvt->dbam0; in dct_debug_display_dimm_sizes()
1122 pvt->csels[1].csbases : in dct_debug_display_dimm_sizes()
1123 pvt->csels[0].csbases; in dct_debug_display_dimm_sizes()
1125 dbam = pvt->dbam0; in dct_debug_display_dimm_sizes()
1126 dcsb = pvt->csels[1].csbases; in dct_debug_display_dimm_sizes()
1143 size0 = pvt->ops->dbam_to_cs(pvt, ctrl, in dct_debug_display_dimm_sizes()
1149 size1 = pvt->ops->dbam_to_cs(pvt, ctrl, in dct_debug_display_dimm_sizes()
1164 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
1165 u32 dcsm = pvt->csels[chan].csmasks[0]; in debug_dump_dramcfg_low()
1181 if (pvt->fam == 0x10) in debug_dump_dramcfg_low()
1212 /* Asymmetric dual-rank DIMM support. */ in umc_get_cs_mode()
1225 pvt->csels[ctrl].csmasks[0] == pvt->csels[ctrl].csmasks[1]) { in umc_get_cs_mode()
1251 msb = fls(addr_mask_orig) - 1; in __addr_mask_to_cs_size()
1253 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE); in __addr_mask_to_cs_size()
1256 addr_mask_deinterleaved = GENMASK_ULL(msb - num_zero_bits, 1); in __addr_mask_to_cs_size()
1292 * CS0 and CS1 -> MASK0 / DIMM0 in umc_addr_mask_to_cs_size()
1293 * CS2 and CS3 -> MASK1 / DIMM1 in umc_addr_mask_to_cs_size()
1298 * CS0 -> MASK0 -> DIMM0 in umc_addr_mask_to_cs_size()
1299 * CS1 -> MASK1 -> DIMM0 in umc_addr_mask_to_cs_size()
1300 * CS2 -> MASK2 -> DIMM1 in umc_addr_mask_to_cs_size()
1301 * CS3 -> MASK3 -> DIMM1 in umc_addr_mask_to_cs_size()
1308 if (!pvt->flags.zn_regs_v2) in umc_addr_mask_to_cs_size()
1311 /* Asymmetric dual-rank DIMM support. */ in umc_addr_mask_to_cs_size()
1313 addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1315 addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr]; in umc_addr_mask_to_cs_size()
1347 umc = &pvt->umc[i]; in umc_dump_misc_regs()
1349 edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg); in umc_dump_misc_regs()
1350 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); in umc_dump_misc_regs()
1351 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); in umc_dump_misc_regs()
1352 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in umc_dump_misc_regs()
1353 edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi); in umc_dump_misc_regs()
1356 i, (umc->umc_cap_hi & BIT(30)) ? "yes" : "no", in umc_dump_misc_regs()
1357 (umc->umc_cap_hi & BIT(31)) ? "yes" : "no"); in umc_dump_misc_regs()
1359 i, (umc->umc_cfg & BIT(12)) ? "yes" : "no"); in umc_dump_misc_regs()
1361 i, (umc->dimm_cfg & BIT(6)) ? "yes" : "no"); in umc_dump_misc_regs()
1363 i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no"); in umc_dump_misc_regs()
1371 edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); in dct_dump_misc_regs()
1374 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no"); in dct_dump_misc_regs()
1377 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no", in dct_dump_misc_regs()
1378 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no"); in dct_dump_misc_regs()
1380 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in dct_dump_misc_regs()
1382 edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); in dct_dump_misc_regs()
1385 pvt->dhar, dhar_base(pvt), in dct_dump_misc_regs()
1386 (pvt->fam == 0xf) ? k8_dhar_offset(pvt) in dct_dump_misc_regs()
1392 if (pvt->fam == 0xf) in dct_dump_misc_regs()
1399 debug_dump_dramcfg_low(pvt, pvt->dclr1, 1); in dct_dump_misc_regs()
1403 amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); in dct_dump_misc_regs()
1411 if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) { in dct_prep_chip_selects()
1412 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in dct_prep_chip_selects()
1413 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8; in dct_prep_chip_selects()
1414 } else if (pvt->fam == 0x15 && pvt->model == 0x30) { in dct_prep_chip_selects()
1415 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4; in dct_prep_chip_selects()
1416 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2; in dct_prep_chip_selects()
1418 pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8; in dct_prep_chip_selects()
1419 pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4; in dct_prep_chip_selects()
1428 pvt->csels[umc].b_cnt = 4; in umc_prep_chip_selects()
1429 pvt->csels[umc].m_cnt = pvt->flags.zn_regs_v2 ? 4 : 2; in umc_prep_chip_selects()
1449 base = &pvt->csels[umc].csbases[cs]; in umc_read_base_mask()
1450 base_sec = &pvt->csels[umc].csbases_sec[cs]; in umc_read_base_mask()
1455 if (!amd_smn_read(pvt->mc_node_id, base_reg, &tmp)) { in umc_read_base_mask()
1461 if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, &tmp)) { in umc_read_base_mask()
1472 mask = &pvt->csels[umc].csmasks[cs]; in umc_read_base_mask()
1473 mask_sec = &pvt->csels[umc].csmasks_sec[cs]; in umc_read_base_mask()
1478 if (!amd_smn_read(pvt->mc_node_id, mask_reg, &tmp)) { in umc_read_base_mask()
1484 if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, &tmp)) { in umc_read_base_mask()
1503 u32 *base0 = &pvt->csels[0].csbases[cs]; in dct_read_base_mask()
1504 u32 *base1 = &pvt->csels[1].csbases[cs]; in dct_read_base_mask()
1510 if (pvt->fam == 0xf) in dct_read_base_mask()
1515 cs, *base1, (pvt->fam == 0x10) ? reg1 in dct_read_base_mask()
1522 u32 *mask0 = &pvt->csels[0].csmasks[cs]; in dct_read_base_mask()
1523 u32 *mask1 = &pvt->csels[1].csmasks[cs]; in dct_read_base_mask()
1529 if (pvt->fam == 0xf) in dct_read_base_mask()
1534 cs, *mask1, (pvt->fam == 0x10) ? reg1 in dct_read_base_mask()
1545 umc = &pvt->umc[i]; in umc_determine_memory_type()
1547 if (!(umc->sdp_ctrl & UMC_SDP_INIT)) { in umc_determine_memory_type()
1548 umc->dram_type = MEM_EMPTY; in umc_determine_memory_type()
1556 if (pvt->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) { in umc_determine_memory_type()
1557 if (umc->dimm_cfg & BIT(5)) in umc_determine_memory_type()
1558 umc->dram_type = MEM_LRDDR5; in umc_determine_memory_type()
1559 else if (umc->dimm_cfg & BIT(4)) in umc_determine_memory_type()
1560 umc->dram_type = MEM_RDDR5; in umc_determine_memory_type()
1562 umc->dram_type = MEM_DDR5; in umc_determine_memory_type()
1564 if (umc->dimm_cfg & BIT(5)) in umc_determine_memory_type()
1565 umc->dram_type = MEM_LRDDR4; in umc_determine_memory_type()
1566 else if (umc->dimm_cfg & BIT(4)) in umc_determine_memory_type()
1567 umc->dram_type = MEM_RDDR4; in umc_determine_memory_type()
1569 umc->dram_type = MEM_DDR4; in umc_determine_memory_type()
1572 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]); in umc_determine_memory_type()
1580 switch (pvt->fam) { in dct_determine_memory_type()
1582 if (pvt->ext_model >= K8_REV_F) in dct_determine_memory_type()
1585 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in dct_determine_memory_type()
1589 if (pvt->dchr0 & DDR3_MODE) in dct_determine_memory_type()
1592 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in dct_determine_memory_type()
1596 if (pvt->model < 0x60) in dct_determine_memory_type()
1609 dcsm = pvt->csels[0].csmasks[0]; in dct_determine_memory_type()
1612 pvt->dram_type = MEM_DDR4; in dct_determine_memory_type()
1613 else if (pvt->dclr0 & BIT(16)) in dct_determine_memory_type()
1614 pvt->dram_type = MEM_DDR3; in dct_determine_memory_type()
1616 pvt->dram_type = MEM_LRDDR3; in dct_determine_memory_type()
1618 pvt->dram_type = MEM_RDDR3; in dct_determine_memory_type()
1626 WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); in dct_determine_memory_type()
1627 pvt->dram_type = MEM_EMPTY; in dct_determine_memory_type()
1630 edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); in dct_determine_memory_type()
1634 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in dct_determine_memory_type()
1640 u16 mce_nid = topology_amd_node_id(m->extcpu); in get_error_address()
1650 pvt = mci->pvt_info; in get_error_address()
1652 if (pvt->fam == 0xf) { in get_error_address()
1657 addr = m->addr & GENMASK_ULL(end_bit, start_bit); in get_error_address()
1662 if (pvt->fam == 0x15) { in get_error_address()
1671 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp); in get_error_address()
1686 amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp); in get_error_address()
1710 if (pci_domain_nr(dev->bus) == pci_domain_nr(related->bus) && in pci_get_related_function()
1711 (dev->bus->number == related->bus->number) && in pci_get_related_function()
1712 (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) in pci_get_related_function()
1727 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off, &pvt->ranges[range].base.lo); in read_dram_base_limit_regs()
1728 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo); in read_dram_base_limit_regs()
1730 if (pvt->fam == 0xf) in read_dram_base_limit_regs()
1736 amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off, &pvt->ranges[range].base.hi); in read_dram_base_limit_regs()
1737 amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi); in read_dram_base_limit_regs()
1740 if (pvt->fam != 0x15) in read_dram_base_limit_regs()
1747 if (pvt->model == 0x60) in read_dram_base_limit_regs()
1749 else if (pvt->model == 0x30) in read_dram_base_limit_regs()
1754 f1 = pci_get_related_function(nb->misc->vendor, pci_func, nb->misc); in read_dram_base_limit_regs()
1760 pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0); in read_dram_base_limit_regs()
1763 pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16; in read_dram_base_limit_regs()
1765 pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0); in read_dram_base_limit_regs()
1768 pvt->ranges[range].lim.hi |= llim >> 13; in read_dram_base_limit_regs()
1776 struct amd64_pvt *pvt = mci->pvt_info; in k8_map_sysaddr_to_csrow()
1784 err->src_mci = find_mc_by_sys_addr(mci, sys_addr); in k8_map_sysaddr_to_csrow()
1785 if (!err->src_mci) { in k8_map_sysaddr_to_csrow()
1788 err->err_code = ERR_NODE; in k8_map_sysaddr_to_csrow()
1793 err->csrow = sys_addr_to_csrow(err->src_mci, sys_addr); in k8_map_sysaddr_to_csrow()
1794 if (err->csrow < 0) { in k8_map_sysaddr_to_csrow()
1795 err->err_code = ERR_CSROW; in k8_map_sysaddr_to_csrow()
1800 if (pvt->nbcfg & NBCFG_CHIPKILL) { in k8_map_sysaddr_to_csrow()
1801 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); in k8_map_sysaddr_to_csrow()
1802 if (err->channel < 0) { in k8_map_sysaddr_to_csrow()
1808 amd64_mc_warn(err->src_mci, "unknown syndrome 0x%04x - " in k8_map_sysaddr_to_csrow()
1810 err->syndrome); in k8_map_sysaddr_to_csrow()
1811 err->err_code = ERR_CHANNEL; in k8_map_sysaddr_to_csrow()
1816 * non-chipkill ecc mode in k8_map_sysaddr_to_csrow()
1819 * channel number when using non-chipkill memory. This method in k8_map_sysaddr_to_csrow()
1821 * (Wish the email was placed in this comment - norsk) in k8_map_sysaddr_to_csrow()
1823 err->channel = ((sys_addr & BIT(3)) != 0); in k8_map_sysaddr_to_csrow()
1844 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1846 if (pvt->ext_model >= K8_REV_F) { in k8_dbam_to_chip_select()
1850 else if (pvt->ext_model >= K8_REV_D) { in k8_dbam_to_chip_select()
1880 return 32 << (cs_mode - diff); in k8_dbam_to_chip_select()
1894 cs_size = -1; in ddr3_cs_size()
1904 if (cs_size != -1) in ddr3_cs_size()
1916 cs_size = -1; in ddr3_lrdimm_cs_size()
1924 if (cs_size != -1) in ddr3_lrdimm_cs_size()
1935 cs_size = -1; in ddr4_cs_size()
1948 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1952 if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE) in f10_dbam_to_chip_select()
1974 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
1978 if (pvt->dram_type == MEM_DDR4) { in f15_m60h_dbam_to_chip_select()
1980 return -1; in f15_m60h_dbam_to_chip_select()
1983 } else if (pvt->dram_type == MEM_LRDDR3) { in f15_m60h_dbam_to_chip_select()
1992 return -1; in f15_m60h_dbam_to_chip_select()
2010 return -1; in f16_dbam_to_chip_select()
2018 if (pvt->fam == 0xf) in read_dram_ctl_register()
2021 if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) { in read_dram_ctl_register()
2023 pvt->dct_sel_lo, dct_sel_baseaddr(pvt)); in read_dram_ctl_register()
2042 amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi); in read_dram_ctl_register()
2083 u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1; in f1x_determine_channel()
2092 * see F2x110[DctSelIntLvAddr] - channel interleave mode in f1x_determine_channel()
2131 u64 dct_sel_base_off = (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16; in f1x_get_norm_dct_addr()
2168 return (sys_addr & GENMASK_ULL(47,6)) - (chan_off & GENMASK_ULL(47,23)); in f1x_get_norm_dct_addr()
2197 * -EINVAL: NOT FOUND
2198 * 0..csrow = Chip-Select Row
2205 int cs_found = -EINVAL; in f1x_lookup_addr_in_dct()
2212 pvt = mci->pvt_info; in f1x_lookup_addr_in_dct()
2231 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in f1x_lookup_addr_in_dct()
2245 * See F2x10C. Non-interleaved graphics framebuffer memory under the 16G is
2253 if (pvt->fam == 0x10) { in f1x_swap_interleaved_region()
2255 if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3)) in f1x_swap_interleaved_region()
2259 amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg); in f1x_swap_interleaved_region()
2282 int cs_found = -EINVAL; in f1x_match_to_this_node()
2300 return -EINVAL; in f1x_match_to_this_node()
2304 return -EINVAL; in f1x_match_to_this_node()
2362 int cs_found = -EINVAL; in f15_m30h_match_to_this_node()
2374 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg); in f15_m30h_match_to_this_node()
2375 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg); in f15_m30h_match_to_this_node()
2385 return -EINVAL; in f15_m30h_match_to_this_node()
2392 return -EINVAL; in f15_m30h_match_to_this_node()
2402 return -EINVAL; in f15_m30h_match_to_this_node()
2408 return -EINVAL; in f15_m30h_match_to_this_node()
2410 if (pvt->model >= 0x60) in f15_m30h_match_to_this_node()
2418 return -EINVAL; in f15_m30h_match_to_this_node()
2428 chan_addr = sys_addr - chan_offset; in f15_m30h_match_to_this_node()
2439 return -EINVAL; in f15_m30h_match_to_this_node()
2449 return -EINVAL; in f15_m30h_match_to_this_node()
2453 amd64_read_pci_cfg(pvt->F1, in f15_m30h_match_to_this_node()
2468 * pvt->csels[1]. So we need to use '1' here to get correct info. in f15_m30h_match_to_this_node()
2485 int cs_found = -EINVAL; in f1x_translate_sysaddr_to_cs()
2492 if (pvt->fam == 0x15 && pvt->model >= 0x30) in f1x_translate_sysaddr_to_cs()
2518 struct amd64_pvt *pvt = mci->pvt_info; in f1x_map_sysaddr_to_csrow()
2522 err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel); in f1x_map_sysaddr_to_csrow()
2523 if (err->csrow < 0) { in f1x_map_sysaddr_to_csrow()
2524 err->err_code = ERR_CSROW; in f1x_map_sysaddr_to_csrow()
2534 err->channel = get_channel_from_ecc_syndrome(mci, err->syndrome); in f1x_map_sysaddr_to_csrow()
2638 return -1; in decode_syndrome()
2661 return -1; in map_err_sym_to_channel()
2669 return -1; in map_err_sym_to_channel()
2674 struct amd64_pvt *pvt = mci->pvt_info; in get_channel_from_ecc_syndrome()
2675 int err_sym = -1; in get_channel_from_ecc_syndrome()
2677 if (pvt->ecc_sym_sz == 8) in get_channel_from_ecc_syndrome()
2680 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2681 else if (pvt->ecc_sym_sz == 4) in get_channel_from_ecc_syndrome()
2684 pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2686 amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2690 return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz); in get_channel_from_ecc_syndrome()
2710 switch (err->err_code) { in __log_ecc_error()
2721 string = "Unknown syndrome - possible error reporting race"; in __log_ecc_error()
2724 string = "MCA_SYND not valid - unknown syndrome and csrow"; in __log_ecc_error()
2735 err->page, err->offset, err->syndrome, in __log_ecc_error()
2736 err->csrow, err->channel, -1, in __log_ecc_error()
2744 u8 ecc_type = (m->status >> 45) & 0x3; in decode_bus_error()
2745 u8 xec = XEC(m->status, 0x1f); in decode_bus_error()
2746 u16 ec = EC(m->status); in decode_bus_error()
2754 pvt = mci->pvt_info; in decode_bus_error()
2769 err.syndrome = extract_syndrome(m->status); in decode_bus_error()
2771 pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err); in decode_bus_error()
2790 err->channel = (m->ipid & GENMASK(31, 0)) >> 20; in umc_get_err_info()
2791 err->csrow = m->synd & 0x7; in umc_get_err_info()
2796 u8 ecc_type = (m->status >> 45) & 0x3; in decode_umc_error()
2809 pvt = mci->pvt_info; in decode_umc_error()
2813 if (m->status & MCI_STATUS_DEFERRED) in decode_umc_error()
2816 if (!(m->status & MCI_STATUS_SYNDV)) { in decode_umc_error()
2822 u8 length = (m->synd >> 18) & 0x3f; in decode_umc_error()
2825 err.syndrome = (m->synd >> 32) & GENMASK(length - 1, 0); in decode_umc_error()
2830 pvt->ops->get_err_info(m, &err); in decode_umc_error()
2832 a_err.addr = m->addr; in decode_umc_error()
2833 a_err.ipid = m->ipid; in decode_umc_error()
2834 a_err.cpu = m->extcpu; in decode_umc_error()
2849 * Use pvt->F3 which contains the F3 CPU PCI device to get the related
2856 pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3); in reserve_mc_sibling_devs()
2857 if (!pvt->F1) { in reserve_mc_sibling_devs()
2859 return -ENODEV; in reserve_mc_sibling_devs()
2863 pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3); in reserve_mc_sibling_devs()
2864 if (!pvt->F2) { in reserve_mc_sibling_devs()
2865 pci_dev_put(pvt->F1); in reserve_mc_sibling_devs()
2866 pvt->F1 = NULL; in reserve_mc_sibling_devs()
2869 return -ENODEV; in reserve_mc_sibling_devs()
2873 pci_ctl_dev = &pvt->F2->dev; in reserve_mc_sibling_devs()
2875 edac_dbg(1, "F1: %s\n", pci_name(pvt->F1)); in reserve_mc_sibling_devs()
2876 edac_dbg(1, "F2: %s\n", pci_name(pvt->F2)); in reserve_mc_sibling_devs()
2877 edac_dbg(1, "F3: %s\n", pci_name(pvt->F3)); in reserve_mc_sibling_devs()
2884 pvt->ecc_sym_sz = 4; in determine_ecc_sym_sz()
2886 if (pvt->fam >= 0x10) { in determine_ecc_sym_sz()
2889 amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp); in determine_ecc_sym_sz()
2891 if (pvt->fam != 0x16) in determine_ecc_sym_sz()
2892 amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1); in determine_ecc_sym_sz()
2895 if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25)) in determine_ecc_sym_sz()
2896 pvt->ecc_sym_sz = 8; in determine_ecc_sym_sz()
2905 u8 nid = pvt->mc_node_id; in umc_read_mc_regs()
2913 umc = &pvt->umc[i]; in umc_read_mc_regs()
2916 umc->dimm_cfg = tmp; in umc_read_mc_regs()
2919 umc->umc_cfg = tmp; in umc_read_mc_regs()
2922 umc->sdp_ctrl = tmp; in umc_read_mc_regs()
2925 umc->ecc_ctrl = tmp; in umc_read_mc_regs()
2928 umc->umc_cap_hi = tmp; in umc_read_mc_regs()
2943 * those are Read-As-Zero. in dct_read_mc_regs()
2945 rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); in dct_read_mc_regs()
2946 edac_dbg(0, " TOP_MEM: 0x%016llx\n", pvt->top_mem); in dct_read_mc_regs()
2951 rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); in dct_read_mc_regs()
2952 edac_dbg(0, " TOP_MEM2: 0x%016llx\n", pvt->top_mem2); in dct_read_mc_regs()
2957 amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); in dct_read_mc_regs()
2978 (rw & 0x1) ? "R" : "-", in dct_read_mc_regs()
2979 (rw & 0x2) ? "W" : "-", in dct_read_mc_regs()
2984 amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar); in dct_read_mc_regs()
2985 amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0); in dct_read_mc_regs()
2987 amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare); in dct_read_mc_regs()
2989 amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0); in dct_read_mc_regs()
2990 amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0); in dct_read_mc_regs()
2993 amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1); in dct_read_mc_regs()
2994 amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); in dct_read_mc_regs()
3004 * @csrow_nr ChipSelect Row Number (0..NUM_CHIPSELECTS-1)
3005 * k8 private pointer to -->
3013 * 0-3 CSROWs 0 and 1
3014 * 4-7 CSROWs 2 and 3
3015 * 8-11 CSROWs 4 and 5
3016 * 12-15 CSROWs 6 and 7
3019 * The meaning of the values depends on CPU revision and dual-channel state,
3036 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in dct_get_csrow_nr_pages()
3042 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in dct_get_csrow_nr_pages()
3043 nr_pages <<= 20 - PAGE_SHIFT; in dct_get_csrow_nr_pages()
3060 nr_pages <<= 20 - PAGE_SHIFT; in umc_get_csrow_nr_pages()
3071 struct amd64_pvt *pvt = mci->pvt_info; in umc_init_csrows()
3077 if (mci->edac_ctl_cap & EDAC_FLAG_S16ECD16ED) { in umc_init_csrows()
3080 } else if (mci->edac_ctl_cap & EDAC_FLAG_S8ECD8ED) { in umc_init_csrows()
3083 } else if (mci->edac_ctl_cap & EDAC_FLAG_S4ECD4ED) { in umc_init_csrows()
3086 } else if (mci->edac_ctl_cap & EDAC_FLAG_SECDED) { in umc_init_csrows()
3095 dimm = mci->csrows[cs]->channels[umc]->dimm; in umc_init_csrows()
3098 pvt->mc_node_id, cs); in umc_init_csrows()
3100 dimm->nr_pages = umc_get_csrow_nr_pages(pvt, umc, cs); in umc_init_csrows()
3101 dimm->mtype = pvt->umc[umc].dram_type; in umc_init_csrows()
3102 dimm->edac_mode = edac_mode; in umc_init_csrows()
3103 dimm->dtype = dev_type; in umc_init_csrows()
3104 dimm->grain = 64; in umc_init_csrows()
3115 struct amd64_pvt *pvt = mci->pvt_info; in dct_init_csrows()
3123 amd64_read_pci_cfg(pvt->F3, NBCFG, &val); in dct_init_csrows()
3125 pvt->nbcfg = val; in dct_init_csrows()
3128 pvt->mc_node_id, val, in dct_init_csrows()
3138 if (pvt->fam != 0xf) in dct_init_csrows()
3144 csrow = mci->csrows[i]; in dct_init_csrows()
3147 pvt->mc_node_id, i); in dct_init_csrows()
3151 csrow->channels[0]->dimm->nr_pages = nr_pages; in dct_init_csrows()
3155 if (pvt->fam != 0xf && row_dct1) { in dct_init_csrows()
3158 csrow->channels[1]->dimm->nr_pages = row_dct1_pages; in dct_init_csrows()
3165 if (pvt->nbcfg & NBCFG_ECC_ENABLE) { in dct_init_csrows()
3166 edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL) in dct_init_csrows()
3171 for (j = 0; j < pvt->max_mcs; j++) { in dct_init_csrows()
3172 dimm = csrow->channels[j]->dimm; in dct_init_csrows()
3173 dimm->mtype = pvt->dram_type; in dct_init_csrows()
3174 dimm->edac_mode = edac_mode; in dct_init_csrows()
3175 dimm->grain = 64; in dct_init_csrows()
3208 nbe = reg->l & MSR_MCGCTL_NBE; in nb_mce_bank_enabled_on_node()
3211 cpu, reg->q, in nb_mce_bank_enabled_on_node()
3231 return -ENOMEM; in toggle_ecc_err_reporting()
3243 if (reg->l & MSR_MCGCTL_NBE) in toggle_ecc_err_reporting()
3244 s->flags.nb_mce_enable = 1; in toggle_ecc_err_reporting()
3246 reg->l |= MSR_MCGCTL_NBE; in toggle_ecc_err_reporting()
3251 if (!s->flags.nb_mce_enable) in toggle_ecc_err_reporting()
3252 reg->l &= ~MSR_MCGCTL_NBE; in toggle_ecc_err_reporting()
3275 s->old_nbctl = value & mask; in enable_ecc_error_reporting()
3276 s->nbctl_valid = true; in enable_ecc_error_reporting()
3289 s->flags.nb_ecc_prev = 0; in enable_ecc_error_reporting()
3305 s->flags.nb_ecc_prev = 1; in enable_ecc_error_reporting()
3319 if (!s->nbctl_valid) in restore_ecc_error_reporting()
3324 value |= s->old_nbctl; in restore_ecc_error_reporting()
3328 /* restore previous BIOS DRAM ECC "off" setting we force-enabled */ in restore_ecc_error_reporting()
3329 if (!s->flags.nb_ecc_prev) { in restore_ecc_error_reporting()
3342 u16 nid = pvt->mc_node_id; in dct_ecc_enabled()
3347 amd64_read_pci_cfg(pvt->F3, NBCFG, &value); in dct_ecc_enabled()
3372 umc = &pvt->umc[i]; in umc_ecc_enabled()
3374 if (umc->sdp_ctrl & UMC_SDP_INIT && in umc_ecc_enabled()
3375 umc->umc_cap_hi & UMC_ECC_ENABLED) { in umc_ecc_enabled()
3381 edac_dbg(3, "Node %d: DRAM ECC %s.\n", pvt->mc_node_id, (ecc_en ? "enabled" : "disabled")); in umc_ecc_enabled()
3392 if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) { in umc_determine_edac_ctl_cap()
3393 ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED); in umc_determine_edac_ctl_cap()
3394 cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP); in umc_determine_edac_ctl_cap()
3396 dev_x4 &= !!(pvt->umc[i].dimm_cfg & BIT(6)); in umc_determine_edac_ctl_cap()
3397 dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7)); in umc_determine_edac_ctl_cap()
3403 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; in umc_determine_edac_ctl_cap()
3409 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; in umc_determine_edac_ctl_cap()
3411 mci->edac_ctl_cap |= EDAC_FLAG_S16ECD16ED; in umc_determine_edac_ctl_cap()
3413 mci->edac_ctl_cap |= EDAC_FLAG_S8ECD8ED; in umc_determine_edac_ctl_cap()
3419 struct amd64_pvt *pvt = mci->pvt_info; in dct_setup_mci_misc_attrs()
3421 mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; in dct_setup_mci_misc_attrs()
3422 mci->edac_ctl_cap = EDAC_FLAG_NONE; in dct_setup_mci_misc_attrs()
3424 if (pvt->nbcap & NBCAP_SECDED) in dct_setup_mci_misc_attrs()
3425 mci->edac_ctl_cap |= EDAC_FLAG_SECDED; in dct_setup_mci_misc_attrs()
3427 if (pvt->nbcap & NBCAP_CHIPKILL) in dct_setup_mci_misc_attrs()
3428 mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; in dct_setup_mci_misc_attrs()
3430 mci->edac_cap = dct_determine_edac_cap(pvt); in dct_setup_mci_misc_attrs()
3431 mci->mod_name = EDAC_MOD_STR; in dct_setup_mci_misc_attrs()
3432 mci->ctl_name = pvt->ctl_name; in dct_setup_mci_misc_attrs()
3433 mci->dev_name = pci_name(pvt->F3); in dct_setup_mci_misc_attrs()
3434 mci->ctl_page_to_phys = NULL; in dct_setup_mci_misc_attrs()
3436 /* memory scrubber interface */ in dct_setup_mci_misc_attrs()
3437 mci->set_sdram_scrub_rate = set_scrub_rate; in dct_setup_mci_misc_attrs()
3438 mci->get_sdram_scrub_rate = get_scrub_rate; in dct_setup_mci_misc_attrs()
3445 struct amd64_pvt *pvt = mci->pvt_info; in umc_setup_mci_misc_attrs()
3447 mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4; in umc_setup_mci_misc_attrs()
3448 mci->edac_ctl_cap = EDAC_FLAG_NONE; in umc_setup_mci_misc_attrs()
3452 mci->edac_cap = umc_determine_edac_cap(pvt); in umc_setup_mci_misc_attrs()
3453 mci->mod_name = EDAC_MOD_STR; in umc_setup_mci_misc_attrs()
3454 mci->ctl_name = pvt->ctl_name; in umc_setup_mci_misc_attrs()
3455 mci->dev_name = pci_name(pvt->F3); in umc_setup_mci_misc_attrs()
3456 mci->ctl_page_to_phys = NULL; in umc_setup_mci_misc_attrs()
3463 int ret = reserve_mc_sibling_devs(pvt, pvt->f1_id, pvt->f2_id); in dct_hw_info_get()
3478 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in umc_hw_info_get()
3479 if (!pvt->umc) in umc_hw_info_get()
3480 return -ENOMEM; in umc_hw_info_get()
3509 u8 ch = (m->ipid & GENMASK(31, 0)) >> 20; in gpu_get_err_info()
3510 u8 phy = ((m->ipid >> 12) & 0xf); in gpu_get_err_info()
3512 err->channel = ch % 2 ? phy + 4 : phy; in gpu_get_err_info()
3513 err->csrow = phy; in gpu_get_err_info()
3519 u32 addr_mask_orig = pvt->csels[umc].csmasks[csrow_nr]; in gpu_addr_mask_to_cs_size()
3544 umc = &pvt->umc[i]; in gpu_dump_misc_regs()
3546 edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg); in gpu_dump_misc_regs()
3547 edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl); in gpu_dump_misc_regs()
3548 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in gpu_dump_misc_regs()
3561 nr_pages <<= 20 - PAGE_SHIFT; in gpu_get_csrow_nr_pages()
3571 struct amd64_pvt *pvt = mci->pvt_info; in gpu_init_csrows()
3580 dimm = mci->csrows[umc]->channels[cs]->dimm; in gpu_init_csrows()
3583 pvt->mc_node_id, cs); in gpu_init_csrows()
3585 dimm->nr_pages = gpu_get_csrow_nr_pages(pvt, umc, cs); in gpu_init_csrows()
3586 dimm->edac_mode = EDAC_SECDED; in gpu_init_csrows()
3587 dimm->mtype = pvt->dram_type; in gpu_init_csrows()
3588 dimm->dtype = DEV_X16; in gpu_init_csrows()
3589 dimm->grain = 64; in gpu_init_csrows()
3596 struct amd64_pvt *pvt = mci->pvt_info; in gpu_setup_mci_misc_attrs()
3598 mci->mtype_cap = MEM_FLAG_HBM2; in gpu_setup_mci_misc_attrs()
3599 mci->edac_ctl_cap = EDAC_FLAG_SECDED; in gpu_setup_mci_misc_attrs()
3601 mci->edac_cap = EDAC_FLAG_EC; in gpu_setup_mci_misc_attrs()
3602 mci->mod_name = EDAC_MOD_STR; in gpu_setup_mci_misc_attrs()
3603 mci->ctl_name = pvt->ctl_name; in gpu_setup_mci_misc_attrs()
3604 mci->dev_name = pci_name(pvt->F3); in gpu_setup_mci_misc_attrs()
3605 mci->ctl_page_to_phys = NULL; in gpu_setup_mci_misc_attrs()
3638 return pvt->gpu_umc_base + (umc << 20) + ((channel % 4) << 12); in gpu_get_umc_base()
3643 u8 nid = pvt->mc_node_id; in gpu_read_mc_regs()
3650 umc = &pvt->umc[i]; in gpu_read_mc_regs()
3653 umc->umc_cfg = tmp; in gpu_read_mc_regs()
3656 umc->sdp_ctrl = tmp; in gpu_read_mc_regs()
3659 umc->ecc_ctrl = tmp; in gpu_read_mc_regs()
3672 base = &pvt->csels[umc].csbases[cs]; in gpu_read_base_mask()
3674 if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) { in gpu_read_base_mask()
3680 mask = &pvt->csels[umc].csmasks[cs]; in gpu_read_base_mask()
3682 if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) { in gpu_read_base_mask()
3695 pvt->csels[umc].b_cnt = 8; in gpu_prep_chip_selects()
3696 pvt->csels[umc].m_cnt = 8; in gpu_prep_chip_selects()
3708 pvt->umc = kcalloc(pvt->max_mcs, sizeof(struct amd64_umc), GFP_KERNEL); in gpu_hw_info_get()
3709 if (!pvt->umc) in gpu_hw_info_get()
3710 return -ENOMEM; in gpu_hw_info_get()
3721 pci_dev_put(pvt->F1); in hw_info_put()
3722 pci_dev_put(pvt->F2); in hw_info_put()
3723 kfree(pvt->umc); in hw_info_put()
3754 pvt->ext_model = boot_cpu_data.x86_model >> 4; in per_family_init()
3755 pvt->stepping = boot_cpu_data.x86_stepping; in per_family_init()
3756 pvt->model = boot_cpu_data.x86_model; in per_family_init()
3757 pvt->fam = boot_cpu_data.x86; in per_family_init()
3758 pvt->max_mcs = 2; in per_family_init()
3764 if (pvt->fam >= 0x17) in per_family_init()
3765 pvt->ops = &umc_ops; in per_family_init()
3767 pvt->ops = &dct_ops; in per_family_init()
3769 switch (pvt->fam) { in per_family_init()
3771 pvt->ctl_name = (pvt->ext_model >= K8_REV_F) ? in per_family_init()
3773 pvt->f1_id = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP; in per_family_init()
3774 pvt->f2_id = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL; in per_family_init()
3775 pvt->ops->map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow; in per_family_init()
3776 pvt->ops->dbam_to_cs = k8_dbam_to_chip_select; in per_family_init()
3780 pvt->ctl_name = "F10h"; in per_family_init()
3781 pvt->f1_id = PCI_DEVICE_ID_AMD_10H_NB_MAP; in per_family_init()
3782 pvt->f2_id = PCI_DEVICE_ID_AMD_10H_NB_DRAM; in per_family_init()
3783 pvt->ops->dbam_to_cs = f10_dbam_to_chip_select; in per_family_init()
3787 switch (pvt->model) { in per_family_init()
3789 pvt->ctl_name = "F15h_M30h"; in per_family_init()
3790 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F1; in per_family_init()
3791 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M30H_NB_F2; in per_family_init()
3794 pvt->ctl_name = "F15h_M60h"; in per_family_init()
3795 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F1; in per_family_init()
3796 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_M60H_NB_F2; in per_family_init()
3797 pvt->ops->dbam_to_cs = f15_m60h_dbam_to_chip_select; in per_family_init()
3801 return -ENODEV; in per_family_init()
3803 pvt->ctl_name = "F15h"; in per_family_init()
3804 pvt->f1_id = PCI_DEVICE_ID_AMD_15H_NB_F1; in per_family_init()
3805 pvt->f2_id = PCI_DEVICE_ID_AMD_15H_NB_F2; in per_family_init()
3806 pvt->ops->dbam_to_cs = f15_dbam_to_chip_select; in per_family_init()
3812 switch (pvt->model) { in per_family_init()
3814 pvt->ctl_name = "F16h_M30h"; in per_family_init()
3815 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F1; in per_family_init()
3816 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_M30H_NB_F2; in per_family_init()
3819 pvt->ctl_name = "F16h"; in per_family_init()
3820 pvt->f1_id = PCI_DEVICE_ID_AMD_16H_NB_F1; in per_family_init()
3821 pvt->f2_id = PCI_DEVICE_ID_AMD_16H_NB_F2; in per_family_init()
3827 switch (pvt->model) { in per_family_init()
3829 pvt->ctl_name = "F17h_M10h"; in per_family_init()
3832 pvt->ctl_name = "F17h_M30h"; in per_family_init()
3833 pvt->max_mcs = 8; in per_family_init()
3836 pvt->ctl_name = "F17h_M60h"; in per_family_init()
3839 pvt->ctl_name = "F17h_M70h"; in per_family_init()
3842 pvt->ctl_name = "F17h"; in per_family_init()
3848 pvt->ctl_name = "F18h"; in per_family_init()
3852 switch (pvt->model) { in per_family_init()
3854 pvt->ctl_name = "F19h"; in per_family_init()
3855 pvt->max_mcs = 8; in per_family_init()
3858 pvt->ctl_name = "F19h_M10h"; in per_family_init()
3859 pvt->max_mcs = 12; in per_family_init()
3860 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3863 pvt->ctl_name = "F19h_M20h"; in per_family_init()
3866 if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) { in per_family_init()
3867 pvt->ctl_name = "MI200"; in per_family_init()
3868 pvt->max_mcs = 4; in per_family_init()
3869 pvt->dram_type = MEM_HBM2; in per_family_init()
3870 pvt->gpu_umc_base = 0x50000; in per_family_init()
3871 pvt->ops = &gpu_ops; in per_family_init()
3873 pvt->ctl_name = "F19h_M30h"; in per_family_init()
3874 pvt->max_mcs = 8; in per_family_init()
3878 pvt->ctl_name = "F19h_M50h"; in per_family_init()
3881 pvt->ctl_name = "F19h_M60h"; in per_family_init()
3882 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3885 pvt->ctl_name = "F19h_M70h"; in per_family_init()
3886 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3889 pvt->ctl_name = "F19h_M90h"; in per_family_init()
3890 pvt->max_mcs = 4; in per_family_init()
3891 pvt->dram_type = MEM_HBM3; in per_family_init()
3892 pvt->gpu_umc_base = 0x90000; in per_family_init()
3893 pvt->ops = &gpu_ops; in per_family_init()
3896 pvt->ctl_name = "F19h_MA0h"; in per_family_init()
3897 pvt->max_mcs = 12; in per_family_init()
3898 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3904 switch (pvt->model) { in per_family_init()
3906 pvt->ctl_name = "F1Ah"; in per_family_init()
3907 pvt->max_mcs = 12; in per_family_init()
3908 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3911 pvt->ctl_name = "F1Ah_M40h"; in per_family_init()
3912 pvt->flags.zn_regs_v2 = 1; in per_family_init()
3919 return -ENODEV; in per_family_init()
3939 bool is_gpu = (pvt->ops == &gpu_ops); in get_layer_size()
3942 return is_gpu ? pvt->max_mcs in get_layer_size()
3943 : pvt->csels[0].b_cnt; in get_layer_size()
3945 return is_gpu ? pvt->csels[0].b_cnt in get_layer_size()
3946 : pvt->max_mcs; in get_layer_size()
3953 int ret = -ENOMEM; in init_one_instance()
3962 mci = edac_mc_alloc(pvt->mc_node_id, ARRAY_SIZE(layers), layers, 0); in init_one_instance()
3966 mci->pvt_info = pvt; in init_one_instance()
3967 mci->pdev = &pvt->F3->dev; in init_one_instance()
3969 pvt->ops->setup_mci_misc_attrs(mci); in init_one_instance()
3971 ret = -ENODEV; in init_one_instance()
3986 for (dct = 0; dct < pvt->max_mcs; dct++) { in instance_has_memory()
3996 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; in probe_one_instance()
4001 ret = -ENOMEM; in probe_one_instance()
4012 pvt->mc_node_id = nid; in probe_one_instance()
4013 pvt->F3 = F3; in probe_one_instance()
4019 ret = pvt->ops->hw_info_get(pvt); in probe_one_instance()
4029 if (!pvt->ops->ecc_enabled(pvt)) { in probe_one_instance()
4030 ret = -ENODEV; in probe_one_instance()
4055 amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); in probe_one_instance()
4058 pvt->ops->dump_misc_regs(pvt); in probe_one_instance()
4076 struct pci_dev *F3 = node_to_amd_nb(nid)->misc; in remove_one_instance()
4082 mci = edac_mc_del_mc(&F3->dev); in remove_one_instance()
4086 pvt = mci->pvt_info; in remove_one_instance()
4094 mci->pvt_info = NULL; in remove_one_instance()
4129 int err = -ENODEV; in amd64_edac_init()
4133 return -EBUSY; in amd64_edac_init()
4137 return -EBUSY; in amd64_edac_init()
4140 return -ENODEV; in amd64_edac_init()
4143 return -ENODEV; in amd64_edac_init()
4147 err = -ENOMEM; in amd64_edac_init()
4160 while (--i >= 0) in amd64_edac_init()
4168 err = -ENODEV; in amd64_edac_init()
4181 amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR); in amd64_edac_init()