Lines Matching +full:error +full:- +full:correction
13 tristate "EDAC (Error Detection And Correction) reporting"
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-[email protected].
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
84 Support for error detection and correction of DRAM ECC errors on
87 When EDAC_DEBUG is enabled, hardware error injection facilities
91 Error Injection into the ECC detection circuits. The amd64_edac
98 - inject_section (0..3, 16-byte section of 64-byte cacheline),
99 - inject_word (0..8, 16-bit word of 16-byte section),
100 - inject_ecc_vector (hex ecc vector: select bits of inject word)
109 Support for error detection and correction for Amazon's Annapurna
110 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
116 Support for error detection and correction on the AMD 76x
123 Support for error detection and correction on the Intel
130 Support for error detection and correction on the Intel
138 Support for error detection and correction on the Intel
145 Support for error detection and correction on the Intel
152 Support for error detection and correction on the Intel
159 Support for error detection and correction on the Intel
166 Support for error detection and correction on the Intel
173 Support for error detection and correction on the Intel
174 E3-1200 based DRAM controllers.
180 Support for error detection and correction on the Intel
187 Support for error detection and correction the Intel
194 Support for error detection and correction the Intel
203 Support for error detection and correction on the Intel
210 Support for error detection and correction on the Radisys
218 Support for error detection and correction the Intel
225 Support for error detection and correction the Intel
232 Support for error detection and correction the Intel
236 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
239 Support for error detection and correction the Intel
249 Support for error detection and correction the Intel
251 system has non-volatile DIMMs you should also manually
261 Support for error detection and correction the Intel
263 system has non-volatile DIMMs you should also manually
271 Support for error detection and correction on the Intel
274 micro-server but may appear on others in the future.
281 Support for error detection and correction on the Intel
282 client SoC Integrated Memory Controller using In-Band ECC IP.
283 This In-Band ECC is first used on the Elkhart Lake SoC but
290 Support for error detection and correction on the Freescale
297 Support for error detection and correction on Freescale memory
304 Support for error detection and correction on PA Semi
311 Support for error detection and correction on the
320 Support for error detection and correction on the
327 Support for error detection and correction on the
334 Support for error detection and correction on the primary caches of
341 Support for error detection and correction on the
348 Support for error detection and correction on the
355 Support for error detection and correction on the
363 Support for error detection and correction on the
372 Support for error detection and correction on the
380 Support for error detection and correction on the
389 Support for error detection and correction on the
394 bool "Altera On-Chip RAM ECC"
397 Support for error detection and correction on the
398 Altera On-Chip RAM Memory for Altera SoCs.
404 Support for error detection and correction on the
411 Support for error detection and correction on the
418 Support for error detection and correction on the
425 Support for error detection and correction on the
432 Support for error detection and correction on the
439 Support for error detection and correction on the
446 Support for error detection and correction on the SiFive SoCs.
452 Support for error correction and detection on the Marvell Aramada XP
459 Support for error detection and correction on the Synopsys DDR
463 tristate "APM X-Gene SoC"
466 Support for error detection and correction on the
467 APM X-Gene family of SOCs.
473 Support for error detection and correction on the TI SoCs.
479 Support for error detection and correction on the
483 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
493 Support for error detection and correction on the Aspeed AST BMC SoC.
496 will expose error counters via the EDAC kernel framework.
502 Support for error detection and correction on the
506 tristate "ARM DMC-520 ECC"
509 Support for error detection and correction on the
510 SoCs with ARM DMC-520 DRAM controller.
516 This driver supports error detection and correction for the
524 Support for error detection and correction on the Nuvoton NPCM DDR
527 The memory controller supports single bit error correction, double bit
528 error detection (in-line ECC in which a section 1/8th of the memory
535 Support for error detection and correction on the Xilinx Versal DDR
546 Support for error detection and correction on the Loongson
548 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000