Lines Matching +full:armada +full:- +full:xp +full:- +full:sdram +full:- +full:controller
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-[email protected].
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
95 When enabled, in each of the respective memory controller directories
98 - inject_section (0..3, 16-byte section of 64-byte cacheline),
99 - inject_word (0..8, 16-bit word of 16-byte section),
100 - inject_ecc_vector (hex ecc vector: select bits of inject word)
106 tristate "Amazon's Annapurna Lab Memory Controller"
174 E3-1200 based DRAM controllers.
195 i7 Core (Nehalem) Integrated Memory Controller that exists on
236 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
251 system has non-volatile DIMMs you should also manually
263 system has non-volatile DIMMs you should also manually
272 Pondicherry2 Integrated Memory Controller. This SoC IP is
274 micro-server but may appear on others in the future.
282 client SoC Integrated Memory Controller using In-Band ECC IP.
283 This In-Band ECC is first used on the Elkhart Lake SoC but
308 tristate "IBM CPC925 Memory Controller (PPC970FX)"
312 IBM CPC925 Bridge and Memory Controller, which is
317 tristate "Highbank Memory Controller"
321 Calxeda Highbank memory controller.
328 Calxeda Highbank memory controller.
345 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
352 tristate "Cavium Octeon PCI Controller"
377 bool "Altera SDRAM ECC"
381 Altera SDRAM Memory for Altera SoCs. Note that the
382 preloader must initialize the SDRAM before loading
394 bool "Altera On-Chip RAM ECC"
398 Altera On-Chip RAM Memory for Altera SoCs.
449 bool "Marvell Armada XP DDR and L2 Cache ECC"
452 Support for error correction and detection on the Marvell Aramada XP
456 tristate "Synopsys DDR Memory Controller"
460 memory controller.
463 tristate "APM X-Gene SoC"
467 APM X-Gene family of SOCs.
470 tristate "Texas Instruments DDR3 ECC Controller"
476 tristate "QCOM EDAC Controller"
483 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
506 tristate "ARM DMC-520 ECC"
510 SoCs with ARM DMC-520 DRAM controller.
513 tristate "Xilinx ZynqMP OCM Controller"
517 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
521 tristate "Nuvoton NPCM DDR Memory Controller"
525 memory controller.
527 The memory controller supports single bit error correction, double bit
528 error detection (in-line ECC in which a section 1/8th of the memory
532 tristate "Xilinx Versal DDR Memory Controller"
536 memory controller.
543 tristate "Loongson Memory Controller"
547 family memory controller. This driver reports single bit
548 errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000