188 	struct tegra_dma	*tdma;  member
230 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)  in tdma_write()  argument
232 	writel(val, tdma->base_addr + reg);  in tdma_write()
348 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_global_pause()  local
350 	spin_lock(&tdma->global_lock);  in tegra_dma_global_pause()
352 	if (tdc->tdma->global_pause_count == 0) {  in tegra_dma_global_pause()
353 		tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);  in tegra_dma_global_pause()
358 	tdc->tdma->global_pause_count++;  in tegra_dma_global_pause()
360 	spin_unlock(&tdma->global_lock);  in tegra_dma_global_pause()
365 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_global_resume()  local
367 	spin_lock(&tdma->global_lock);  in tegra_dma_global_resume()
369 	if (WARN_ON(tdc->tdma->global_pause_count == 0))  in tegra_dma_global_resume()
372 	if (--tdc->tdma->global_pause_count == 0)  in tegra_dma_global_resume()
373 		tdma_write(tdma, TEGRA_APBDMA_GENERAL,  in tegra_dma_global_resume()
377 	spin_unlock(&tdma->global_lock);  in tegra_dma_global_resume()
383 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_pause()  local
385 	if (tdma->chip_data->support_channel_pause) {  in tegra_dma_pause()
397 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_resume()  local
399 	if (tdma->chip_data->support_channel_pause)  in tegra_dma_resume()
437 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_start()
478 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_configure_for_next()
557 		pm_runtime_put(tdc->tdma->dev);  in handle_continuous_head_request()
597 		pm_runtime_put(tdc->tdma->dev);  in handle_once_dma_done()
714 		err = pm_runtime_resume_and_get(tdc->tdma->dev);  in tegra_dma_issue_pending()
759 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_terminate_all()
775 	pm_runtime_put(tdc->tdma->dev);  in tegra_dma_terminate_all()
809 	err = pm_runtime_resume_and_get(tdc->tdma->dev);  in tegra_dma_synchronize()
824 	pm_runtime_put(tdc->tdma->dev);  in tegra_dma_synchronize()
835 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_sg_bytes_xferred()
840 	if (!tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_sg_bytes_xferred()
1028 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_prep_wcount()
1108 		    len > tdc->tdma->chip_data->max_dma_count) {  in tegra_dma_prep_slave_sg()
1208 	    len > tdc->tdma->chip_data->max_dma_count) {  in tegra_dma_prep_dma_cyclic()
1348 	struct tegra_dma *tdma = ofdma->of_dma_data;  in tegra_dma_of_xlate()  local
1353 		dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);  in tegra_dma_of_xlate()
1357 	chan = dma_get_any_slave_channel(&tdma->dma_dev);  in tegra_dma_of_xlate()
1403 static int tegra_dma_init_hw(struct tegra_dma *tdma)  in tegra_dma_init_hw()  argument
1407 	err = reset_control_assert(tdma->rst);  in tegra_dma_init_hw()
1409 		dev_err(tdma->dev, "failed to assert reset: %d\n", err);  in tegra_dma_init_hw()
1413 	err = clk_enable(tdma->dma_clk);  in tegra_dma_init_hw()
1415 		dev_err(tdma->dev, "failed to enable clk: %d\n", err);  in tegra_dma_init_hw()
1421 	reset_control_deassert(tdma->rst);  in tegra_dma_init_hw()
1424 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);  in tegra_dma_init_hw()
1425 	tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);  in tegra_dma_init_hw()
1426 	tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFF);  in tegra_dma_init_hw()
1428 	clk_disable(tdma->dma_clk);  in tegra_dma_init_hw()
1436 	struct tegra_dma *tdma;  in tegra_dma_probe()  local
1442 	size = struct_size(tdma, channels, cdata->nr_channels);  in tegra_dma_probe()
1444 	tdma = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);  in tegra_dma_probe()
1445 	if (!tdma)  in tegra_dma_probe()
1448 	tdma->dev = &pdev->dev;  in tegra_dma_probe()
1449 	tdma->chip_data = cdata;  in tegra_dma_probe()
1450 	platform_set_drvdata(pdev, tdma);  in tegra_dma_probe()
1452 	tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);  in tegra_dma_probe()
1453 	if (IS_ERR(tdma->base_addr))  in tegra_dma_probe()
1454 		return PTR_ERR(tdma->base_addr);  in tegra_dma_probe()
1456 	tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);  in tegra_dma_probe()
1457 	if (IS_ERR(tdma->dma_clk)) {  in tegra_dma_probe()
1459 		return PTR_ERR(tdma->dma_clk);  in tegra_dma_probe()
1462 	tdma->rst = devm_reset_control_get(&pdev->dev, "dma");  in tegra_dma_probe()
1463 	if (IS_ERR(tdma->rst)) {  in tegra_dma_probe()
1465 		return PTR_ERR(tdma->rst);  in tegra_dma_probe()
1468 	spin_lock_init(&tdma->global_lock);  in tegra_dma_probe()
1470 	ret = clk_prepare(tdma->dma_clk);  in tegra_dma_probe()
1474 	ret = tegra_dma_init_hw(tdma);  in tegra_dma_probe()
1481 	INIT_LIST_HEAD(&tdma->dma_dev.channels);  in tegra_dma_probe()
1483 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_probe()
1486 		tdc->chan_addr = tdma->base_addr +  in tegra_dma_probe()
1506 		tdc->dma_chan.device = &tdma->dma_dev;  in tegra_dma_probe()
1509 			      &tdma->dma_dev.channels);  in tegra_dma_probe()
1510 		tdc->tdma = tdma;  in tegra_dma_probe()
1524 	dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1525 	dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1526 	dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1528 	tdma->global_pause_count = 0;  in tegra_dma_probe()
1529 	tdma->dma_dev.dev = &pdev->dev;  in tegra_dma_probe()
1530 	tdma->dma_dev.device_alloc_chan_resources =  in tegra_dma_probe()
1532 	tdma->dma_dev.device_free_chan_resources =  in tegra_dma_probe()
1534 	tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;  in tegra_dma_probe()
1535 	tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;  in tegra_dma_probe()
1536 	tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |  in tegra_dma_probe()
1540 	tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |  in tegra_dma_probe()
1544 	tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);  in tegra_dma_probe()
1545 	tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;  in tegra_dma_probe()
1546 	tdma->dma_dev.device_config = tegra_dma_slave_config;  in tegra_dma_probe()
1547 	tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;  in tegra_dma_probe()
1548 	tdma->dma_dev.device_synchronize = tegra_dma_synchronize;  in tegra_dma_probe()
1549 	tdma->dma_dev.device_tx_status = tegra_dma_tx_status;  in tegra_dma_probe()
1550 	tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;  in tegra_dma_probe()
1552 	ret = dma_async_device_register(&tdma->dma_dev);  in tegra_dma_probe()
1560 					 tegra_dma_of_xlate, tdma);  in tegra_dma_probe()
1573 	dma_async_device_unregister(&tdma->dma_dev);  in tegra_dma_probe()
1579 	clk_unprepare(tdma->dma_clk);  in tegra_dma_probe()
1586 	struct tegra_dma *tdma = platform_get_drvdata(pdev);  in tegra_dma_remove()  local
1589 	dma_async_device_unregister(&tdma->dma_dev);  in tegra_dma_remove()
1591 	clk_unprepare(tdma->dma_clk);  in tegra_dma_remove()
1596 	struct tegra_dma *tdma = dev_get_drvdata(dev);  in tegra_dma_runtime_suspend()  local
1598 	clk_disable(tdma->dma_clk);  in tegra_dma_runtime_suspend()
1605 	struct tegra_dma *tdma = dev_get_drvdata(dev);  in tegra_dma_runtime_resume()  local
1607 	return clk_enable(tdma->dma_clk);  in tegra_dma_runtime_resume()
1612 	struct tegra_dma *tdma = dev_get_drvdata(dev);  in tegra_dma_dev_suspend()  local
1617 	for (i = 0; i < tdma->chip_data->nr_channels; i++) {  in tegra_dma_dev_suspend()
1618 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_dev_suspend()
1627 			dev_err(tdma->dev, "channel %u busy\n", i);  in tegra_dma_dev_suspend()
1637 	struct tegra_dma *tdma = dev_get_drvdata(dev);  in tegra_dma_dev_resume()  local
1640 	err = tegra_dma_init_hw(tdma);  in tegra_dma_dev_resume()