Lines Matching +full:mc +full:- +full:sid
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/dma-mapping.h>
21 #include <dt-bindings/memory/tegra186-mc.h>
22 #include "virt-dma.h"
87 /* MC sequence register */
118 (GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT)
158 * on-flight burst and update DMA status register.
203 * sub-transfer as per requester details and hw support. This sub transfer
264 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_write()
269 return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_read()
284 return tdc->vc.chan.device->dev; in tdc2dev()
290 tdc->id, tdc->name); in tegra_dma_dump_chan_regs()
312 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_reserve()
313 int sid = tdc->slave_id; in tegra_dma_sid_reserve() local
320 if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) { in tegra_dma_sid_reserve()
321 dev_err(tdma->dev, "slave id already in use\n"); in tegra_dma_sid_reserve()
322 return -EINVAL; in tegra_dma_sid_reserve()
326 if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) { in tegra_dma_sid_reserve()
327 dev_err(tdma->dev, "slave id already in use\n"); in tegra_dma_sid_reserve()
328 return -EINVAL; in tegra_dma_sid_reserve()
335 tdc->sid_dir = direction; in tegra_dma_sid_reserve()
342 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_free()
343 int sid = tdc->slave_id; in tegra_dma_sid_free() local
345 switch (tdc->sid_dir) { in tegra_dma_sid_free()
347 clear_bit(sid, &tdma->sid_m2d_reserved); in tegra_dma_sid_free()
350 clear_bit(sid, &tdma->sid_d2m_reserved); in tegra_dma_sid_free()
356 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_sid_free()
369 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
370 tdc->config_init = true; in tegra_dma_slave_config()
384 /* Wait until busy bit is de-asserted */ in tegra_dma_pause()
385 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_pause()
386 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_pause()
397 tdc->status = DMA_PAUSED; in tegra_dma_pause()
408 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_pause()
409 return -ENOSYS; in tegra_dma_device_pause()
411 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_pause()
413 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_pause()
426 tdc->status = DMA_IN_PROGRESS; in tegra_dma_resume()
434 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_resume()
435 return -ENOSYS; in tegra_dma_device_resume()
437 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_resume()
439 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_resume()
478 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_configure_next_sg()
483 dma_desc->sg_idx++; in tegra_dma_configure_next_sg()
486 if (dma_desc->sg_idx == dma_desc->sg_count) in tegra_dma_configure_next_sg()
487 dma_desc->sg_idx = 0; in tegra_dma_configure_next_sg()
490 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_configure_next_sg()
491 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_configure_next_sg()
498 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; in tegra_dma_configure_next_sg()
500 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_configure_next_sg()
501 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_configure_next_sg()
502 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_configure_next_sg()
503 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_configure_next_sg()
507 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_configure_next_sg()
512 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_start()
517 vdesc = vchan_next_desc(&tdc->vc); in tegra_dma_start()
522 list_del(&vdesc->node); in tegra_dma_start()
523 dma_desc->tdc = tdc; in tegra_dma_start()
524 tdc->dma_desc = dma_desc; in tegra_dma_start()
529 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; in tegra_dma_start()
531 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
533 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_start()
534 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_start()
535 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_start()
536 tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); in tegra_dma_start()
537 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); in tegra_dma_start()
538 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); in tegra_dma_start()
539 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
543 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_start()
548 vchan_cookie_complete(&tdc->dma_desc->vd); in tegra_dma_xfer_complete()
551 tdc->dma_desc = NULL; in tegra_dma_xfer_complete()
552 tdc->status = DMA_COMPLETE; in tegra_dma_xfer_complete()
560 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
561 "GPCDMA CH%d bm fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
565 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
566 "GPCDMA CH%d peripheral fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
570 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
571 "GPCDMA CH%d illegal peripheral id\n", tdc->id); in tegra_dma_chan_decode_error()
575 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
576 "GPCDMA CH%d illegal stream id\n", tdc->id); in tegra_dma_chan_decode_error()
580 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
581 "GPCDMA CH%d mc slave error\n", tdc->id); in tegra_dma_chan_decode_error()
585 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
586 "GPCDMA CH%d mmio slave error\n", tdc->id); in tegra_dma_chan_decode_error()
590 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
591 "GPCDMA CH%d security violation %x\n", tdc->id, in tegra_dma_chan_decode_error()
599 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_isr()
611 spin_lock(&tdc->vc.lock); in tegra_dma_isr()
622 sg_req = dma_desc->sg_req; in tegra_dma_isr()
623 dma_desc->bytes_xfer += sg_req[dma_desc->sg_idx].len; in tegra_dma_isr()
625 if (dma_desc->cyclic) { in tegra_dma_isr()
626 vchan_cyclic_callback(&dma_desc->vd); in tegra_dma_isr()
629 dma_desc->sg_idx++; in tegra_dma_isr()
630 if (dma_desc->sg_idx == dma_desc->sg_count) in tegra_dma_isr()
637 spin_unlock(&tdc->vc.lock); in tegra_dma_isr()
646 if (tdc->dma_desc) in tegra_dma_issue_pending()
649 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
650 if (vchan_issue_pending(&tdc->vc)) in tegra_dma_issue_pending()
660 if (tdc->dma_desc && tdc->dma_desc->cyclic) in tegra_dma_issue_pending()
663 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
688 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_stop_client()
689 tdc->chan_base_offset + in tegra_dma_stop_client()
711 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
713 if (tdc->dma_desc) { in tegra_dma_terminate_all()
714 err = tdc->tdma->chip_data->terminate(tdc); in tegra_dma_terminate_all()
716 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
720 vchan_terminate_vdesc(&tdc->dma_desc->vd); in tegra_dma_terminate_all()
722 tdc->dma_desc = NULL; in tegra_dma_terminate_all()
725 tdc->status = DMA_COMPLETE; in tegra_dma_terminate_all()
727 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_dma_terminate_all()
728 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
730 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_dma_terminate_all()
737 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_get_residual()
738 struct tegra_dma_sg_req *sg_req = dma_desc->sg_req; in tegra_dma_get_residual()
753 bytes_xfer = dma_desc->bytes_xfer + in tegra_dma_get_residual()
754 sg_req[dma_desc->sg_idx].len - (wcount * 4); in tegra_dma_get_residual()
756 if (dma_desc->bytes_req == bytes_xfer) in tegra_dma_get_residual()
759 residual = dma_desc->bytes_req - (bytes_xfer % dma_desc->bytes_req); in tegra_dma_get_residual()
779 if (tdc->status == DMA_PAUSED) in tegra_dma_tx_status()
782 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_tx_status()
783 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_dma_tx_status()
786 residual = dma_desc->bytes_req; in tegra_dma_tx_status()
788 } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) { in tegra_dma_tx_status()
794 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_tx_status()
811 return -EINVAL; in get_bus_width()
848 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
849 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
850 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
851 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
855 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
856 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
857 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
858 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
865 return -EINVAL; in get_transfer_param()
873 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memset()
897 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_memset()
906 /* Program outstanding MC requests */ in tegra_dma_prep_dma_memset()
915 dma_desc->bytes_req = len; in tegra_dma_prep_dma_memset()
916 dma_desc->sg_count = 1; in tegra_dma_prep_dma_memset()
917 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_memset()
925 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_memset()
931 dma_desc->cyclic = false; in tegra_dma_prep_dma_memset()
932 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memset()
945 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memcpy()
965 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_memcpy()
975 /* Program outstanding MC requests */ in tegra_dma_prep_dma_memcpy()
984 dma_desc->bytes_req = len; in tegra_dma_prep_dma_memcpy()
985 dma_desc->sg_count = 1; in tegra_dma_prep_dma_memcpy()
986 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_memcpy()
995 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_memcpy()
1001 dma_desc->cyclic = false; in tegra_dma_prep_dma_memcpy()
1002 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memcpy()
1011 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_slave_sg()
1021 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
1042 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_slave_sg()
1053 /* retain stream-id and clean rest */ in tegra_dma_prep_slave_sg()
1056 /* Set the address wrapping on both MC and MMIO side */ in tegra_dma_prep_slave_sg()
1064 /* Program 2 MC outstanding requests by default. */ in tegra_dma_prep_slave_sg()
1067 /* Setting MC burst size depending on MMIO burst size */ in tegra_dma_prep_slave_sg()
1077 dma_desc->sg_count = sg_len; in tegra_dma_prep_slave_sg()
1078 sg_req = dma_desc->sg_req; in tegra_dma_prep_slave_sg()
1096 dma_desc->bytes_req += len; in tegra_dma_prep_slave_sg()
1114 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_slave_sg()
1121 dma_desc->cyclic = false; in tegra_dma_prep_slave_sg()
1122 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_slave_sg()
1144 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1163 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_cyclic()
1177 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_dma_cyclic()
1190 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_cyclic()
1193 /* Set the address wrapping on both MC and MMIO side */ in tegra_dma_prep_dma_cyclic()
1199 /* Program 2 MC outstanding requests by default. */ in tegra_dma_prep_dma_cyclic()
1201 /* Setting MC burst size depending on MMIO burst size */ in tegra_dma_prep_dma_cyclic()
1213 dma_desc->bytes_req = buf_len; in tegra_dma_prep_dma_cyclic()
1214 dma_desc->sg_count = period_count; in tegra_dma_prep_dma_cyclic()
1215 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_cyclic()
1235 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_cyclic()
1244 dma_desc->cyclic = true; in tegra_dma_prep_dma_cyclic()
1246 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_cyclic()
1254 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc); in tegra_dma_alloc_chan_resources()
1256 dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name); in tegra_dma_alloc_chan_resources()
1260 dma_cookie_init(&tdc->vc.chan); in tegra_dma_alloc_chan_resources()
1261 tdc->config_init = false; in tegra_dma_alloc_chan_resources()
1269 synchronize_irq(tdc->irq); in tegra_dma_chan_synchronize()
1270 vchan_synchronize(&tdc->vc); in tegra_dma_chan_synchronize()
1277 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1280 synchronize_irq(tdc->irq); in tegra_dma_free_chan_resources()
1282 tasklet_kill(&tdc->vc.task); in tegra_dma_free_chan_resources()
1283 tdc->config_init = false; in tegra_dma_free_chan_resources()
1284 tdc->slave_id = -1; in tegra_dma_free_chan_resources()
1285 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_free_chan_resources()
1286 free_irq(tdc->irq, tdc); in tegra_dma_free_chan_resources()
1288 vchan_free_chan_resources(&tdc->vc); in tegra_dma_free_chan_resources()
1294 struct tegra_dma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
1298 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
1303 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1334 .compatible = "nvidia,tegra186-gpcdma",
1337 .compatible = "nvidia,tegra194-gpcdma",
1340 .compatible = "nvidia,tegra234-gpcdma",
1369 cdata = of_device_get_match_data(&pdev->dev); in tegra_dma_probe()
1371 tdma = devm_kzalloc(&pdev->dev, in tegra_dma_probe()
1372 struct_size(tdma, channels, cdata->nr_channels), in tegra_dma_probe()
1375 return -ENOMEM; in tegra_dma_probe()
1377 tdma->dev = &pdev->dev; in tegra_dma_probe()
1378 tdma->chip_data = cdata; in tegra_dma_probe()
1381 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); in tegra_dma_probe()
1382 if (IS_ERR(tdma->base_addr)) in tegra_dma_probe()
1383 return PTR_ERR(tdma->base_addr); in tegra_dma_probe()
1385 tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma"); in tegra_dma_probe()
1386 if (IS_ERR(tdma->rst)) { in tegra_dma_probe()
1387 return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst), in tegra_dma_probe()
1390 reset_control_reset(tdma->rst); in tegra_dma_probe()
1392 tdma->dma_dev.dev = &pdev->dev; in tegra_dma_probe()
1394 if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { in tegra_dma_probe()
1395 dev_err(&pdev->dev, "Missing iommu stream-id\n"); in tegra_dma_probe()
1396 return -EINVAL; in tegra_dma_probe()
1399 ret = device_property_read_u32(&pdev->dev, "dma-channel-mask", in tegra_dma_probe()
1400 &tdma->chan_mask); in tegra_dma_probe()
1402 dev_warn(&pdev->dev, in tegra_dma_probe()
1403 "Missing dma-channel-mask property, using default channel mask %#x\n", in tegra_dma_probe()
1405 tdma->chan_mask = TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK; in tegra_dma_probe()
1408 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_dma_probe()
1409 for (i = 0; i < cdata->nr_channels; i++) { in tegra_dma_probe()
1410 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe()
1413 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_probe()
1416 tdc->irq = platform_get_irq(pdev, i); in tegra_dma_probe()
1417 if (tdc->irq < 0) in tegra_dma_probe()
1418 return tdc->irq; in tegra_dma_probe()
1420 tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET + in tegra_dma_probe()
1421 i * cdata->channel_reg_size; in tegra_dma_probe()
1422 snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); in tegra_dma_probe()
1423 tdc->tdma = tdma; in tegra_dma_probe()
1424 tdc->id = i; in tegra_dma_probe()
1425 tdc->slave_id = -1; in tegra_dma_probe()
1427 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_dma_probe()
1428 tdc->vc.desc_free = tegra_dma_desc_free; in tegra_dma_probe()
1430 /* program stream-id for this channel */ in tegra_dma_probe()
1432 tdc->stream_id = stream_id; in tegra_dma_probe()
1435 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1436 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1437 dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1438 dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1439 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1445 tdma->dma_dev.copy_align = 2; in tegra_dma_probe()
1446 tdma->dma_dev.fill_align = 2; in tegra_dma_probe()
1447 tdma->dma_dev.device_alloc_chan_resources = in tegra_dma_probe()
1449 tdma->dma_dev.device_free_chan_resources = in tegra_dma_probe()
1451 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg; in tegra_dma_probe()
1452 tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy; in tegra_dma_probe()
1453 tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset; in tegra_dma_probe()
1454 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; in tegra_dma_probe()
1455 tdma->dma_dev.device_config = tegra_dma_slave_config; in tegra_dma_probe()
1456 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all; in tegra_dma_probe()
1457 tdma->dma_dev.device_tx_status = tegra_dma_tx_status; in tegra_dma_probe()
1458 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; in tegra_dma_probe()
1459 tdma->dma_dev.device_pause = tegra_dma_device_pause; in tegra_dma_probe()
1460 tdma->dma_dev.device_resume = tegra_dma_device_resume; in tegra_dma_probe()
1461 tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize; in tegra_dma_probe()
1462 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in tegra_dma_probe()
1464 ret = dma_async_device_register(&tdma->dma_dev); in tegra_dma_probe()
1466 dev_err_probe(&pdev->dev, ret, in tegra_dma_probe()
1471 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_dma_probe()
1474 dev_err_probe(&pdev->dev, ret, in tegra_dma_probe()
1477 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_probe()
1481 dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n", in tegra_dma_probe()
1482 hweight_long(tdma->chan_mask)); in tegra_dma_probe()
1491 of_dma_controller_free(pdev->dev.of_node); in tegra_dma_remove()
1492 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_remove()
1500 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_suspend()
1501 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_suspend()
1503 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_pm_suspend()
1506 if (tdc->dma_desc) { in tegra_dma_pm_suspend()
1507 dev_err(tdma->dev, "channel %u busy\n", i); in tegra_dma_pm_suspend()
1508 return -EBUSY; in tegra_dma_pm_suspend()
1520 reset_control_reset(tdma->rst); in tegra_dma_pm_resume()
1522 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_resume()
1523 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_resume()
1525 if (!(tdma->chan_mask & BIT(i))) in tegra_dma_pm_resume()
1528 tegra_dma_program_sid(tdc, tdc->stream_id); in tegra_dma_pm_resume()
1540 .name = "tegra-gpcdma",