26 #define STM32_DMA3_SECCFGR		0x00
27 #define STM32_DMA3_PRIVCFGR		0x04
28 #define STM32_DMA3_RCFGLOCKR		0x08
29 #define STM32_DMA3_MISR			0x0c
30 #define STM32_DMA3_SMISR		0x10
32 #define STM32_DMA3_CLBAR(x)		(0x50 + 0x80 * (x))
33 #define STM32_DMA3_CCIDCFGR(x)		(0x54 + 0x80 * (x))
34 #define STM32_DMA3_CSEMCR(x)		(0x58 + 0x80 * (x))
35 #define STM32_DMA3_CFCR(x)		(0x5c + 0x80 * (x))
36 #define STM32_DMA3_CSR(x)		(0x60 + 0x80 * (x))
37 #define STM32_DMA3_CCR(x)		(0x64 + 0x80 * (x))
38 #define STM32_DMA3_CTR1(x)		(0x90 + 0x80 * (x))
39 #define STM32_DMA3_CTR2(x)		(0x94 + 0x80 * (x))
40 #define STM32_DMA3_CBR1(x)		(0x98 + 0x80 * (x))
41 #define STM32_DMA3_CSAR(x)		(0x9c + 0x80 * (x))
42 #define STM32_DMA3_CDAR(x)		(0xa0 + 0x80 * (x))
43 #define STM32_DMA3_CLLR(x)		(0xcc + 0x80 * (x))
45 #define STM32_DMA3_HWCFGR13		0xfc0 /* G_PER_CTRL(X) x=8..15 */
46 #define STM32_DMA3_HWCFGR12		0xfc4 /* G_PER_CTRL(X) x=0..7 */
47 #define STM32_DMA3_HWCFGR4		0xfe4 /* G_FIFO_SIZE(X) x=8..15 */
48 #define STM32_DMA3_HWCFGR3		0xfe8 /* G_FIFO_SIZE(X) x=0..7 */
49 #define STM32_DMA3_HWCFGR2		0xfec /* G_MAX_REQ_ID */
50 #define STM32_DMA3_HWCFGR1		0xff0 /* G_MASTER_PORTS, G_NUM_CHANNELS, G_Mx_DATA_WIDTH */
51 #define STM32_DMA3_VERR			0xff4
63 #define CCIDCFGR_CFEN			BIT(0)
77 #define CSEMCR_SEM_MUTEX		BIT(0)
89 #define CSR_IDLEF			BIT(0)
100 #define CCR_EN				BIT(0)
126 #define CTR1_SDW_LOG2			GENMASK(1, 0)
140 	CTR1_PAM_0S_LT,		/* if DDW > SDW, padded with 0s else left-truncated */
146 #define CTR2_REQSEL			GENMASK(7, 0)
161 #define CBR1_BNDT			GENMASK(15, 0)
173 /* HWCFGR12 DMA hardware configuration register 12 x=0..7 */
174 #define G_PER_CTRL(x)			(ULL(0x1) << (4 * (x)))
177 /* HWCFGR3 DMA hardware configuration register 3 x=0..7 */
178 #define G_FIFO_SIZE(x)			(ULL(0x7) << (4 * (x)))
183 #define G_MAX_REQ_ID			GENMASK(7, 0)
186 #define G_MASTER_PORTS			GENMASK(2, 0)
192 	AXI64,		/* 1x AXI: 64-bit port 0 */
193 	AHB32,		/* 1x AHB: 32-bit port 0 */
194 	AHB32_AHB32,	/* 2x AHB: 32-bit port 0 and 32-bit port 1 */
195 	AXI64_AHB32,	/* 1x AXI 64-bit port 0 and 1x AHB 32-bit port 1 */
196 	AXI64_AXI64,	/* 2x AXI: 64-bit port 0 and 64-bit port 1 */
197 	AXI128_AHB32,	/* 1x AXI 128-bit port 0 and 1x AHB 32-bit port 1 */
208 #define VERR_MINREV			GENMASK(3, 0)
214 #define STM32_DMA3_DT_PRIO		GENMASK(1, 0) /* CCR_PRIO */
217 #define STM32_DMA3_DT_SINC		BIT(0) /* CTR1_SINC */
228 #define STM32_DMA3_CFG_SET_DT		BIT(0)
342 	dev_dbg(dev, "SECCFGR(0x%03x): %08x\n", offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
344 	dev_dbg(dev, "PRIVCFGR(0x%03x): %08x\n", offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
346 	dev_dbg(dev, "C%dCIDCFGR(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
348 	dev_dbg(dev, "C%dSEMCR(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
350 	dev_dbg(dev, "C%dSR(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
352 	dev_dbg(dev, "C%dCR(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
354 	dev_dbg(dev, "C%dTR1(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
356 	dev_dbg(dev, "C%dTR2(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
358 	dev_dbg(dev, "C%dBR1(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
360 	dev_dbg(dev, "C%dSAR(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
362 	dev_dbg(dev, "C%dDAR(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
364 	dev_dbg(dev, "C%dLLR(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
366 	dev_dbg(dev, "C%dLBAR(0x%03x): %08x\n", id, offset, readl_relaxed(ddata->base + offset));  in stm32_dma3_chan_dump_reg()
375 	for (i = 0; i < swdesc->lli_size; i++) {  in stm32_dma3_chan_dump_hwdesc()
390 		dev_dbg(chan2dev(chan), "-->[0]@%pad\n", &swdesc->lli[0].hwdesc_addr);  in stm32_dma3_chan_dump_hwdesc()
417 	for (i = 0; i < count; i++) {  in stm32_dma3_chan_desc_alloc()
423 	swdesc->ccr = 0;  in stm32_dma3_chan_desc_alloc()
426 	writel_relaxed(swdesc->lli[0].hwdesc_addr & CLBAR_LBA,  in stm32_dma3_chan_desc_alloc()
436 	while (--i >= 0)  in stm32_dma3_chan_desc_alloc()
448 	for (i = 0; i < swdesc->lli_size; i++)  in stm32_dma3_chan_desc_free()
511 			next_lli = swdesc->lli[0].hwdesc_addr;  in stm32_dma3_chan_prep_hwdesc()
513 			next_lli = 0;  in stm32_dma3_chan_prep_hwdesc()
518 	hwdesc->cllr = 0;  in stm32_dma3_chan_prep_hwdesc()
570 	u32 _ctr1 = 0, _ctr2 = 0;  in stm32_dma3_chan_prep_hw()
761 	return 0;  in stm32_dma3_chan_prep_hw()
780 	hwdesc = chan->swdesc->lli[0].hwdesc;  in stm32_dma3_chan_start()
811 	int ret = 0;  in stm32_dma3_chan_suspend()
849 	if (swdesc->cyclic && next_lli_offset == (swdesc->lli[0].hwdesc_addr & CLLR_LA))  in stm32_dma3_chan_get_curr_hwdesc()
853 	for (i = swdesc->lli_size - 1; i > 0; i--) {  in stm32_dma3_chan_get_curr_hwdesc()
917 	if (ret < 0) {  in stm32_dma3_chan_set_residue()
948 		if (bytes_read > 0)  in stm32_dma3_chan_set_residue()
972 	int ret = 0;  in stm32_dma3_chan_stop()
1074 	if (ret < 0)  in stm32_dma3_alloc_chan_resources()
1104 		dev_dbg(chan2dev(chan), "Under CID1 control (semcr=0x%08x)\n", csemcr);  in stm32_dma3_alloc_chan_resources()
1107 	return 0;  in stm32_dma3_alloc_chan_resources()
1138 		writel_relaxed(0, ddata->base + STM32_DMA3_CSEMCR(chan->id));  in stm32_dma3_free_chan_resources()
1143 	memset(&chan->dt_config, 0, sizeof(chan->dt_config));  in stm32_dma3_free_chan_resources()
1144 	memset(&chan->dma_config, 0, sizeof(chan->dma_config));  in stm32_dma3_free_chan_resources()
1145 	chan->config_set = 0;  in stm32_dma3_free_chan_resources()
1164 	if (len > 0)  in stm32_dma3_get_ll_count()
1174 	u32 dw = get_chan_max_dw(ddata->ports_max_dw[0], chan->max_burst); /* port 0 by default */  in stm32_dma3_init_chan_config_for_memcpy()
1216 	for (i = 0, offset = 0; offset < len; i++, offset += next_size) {  in stm32_dma3_prep_dma_memcpy()
1267 	count = 0;  in stm32_dma3_prep_slave_sg()
1276 	j = 0;  in stm32_dma3_prep_slave_sg()
1388 	for (i = 0; i < count; i++) {  in stm32_dma3_prep_dma_cyclic()
1421 		caps->max_burst = 0;  in stm32_dma3_caps()
1441 	return 0;  in stm32_dma3_config()
1457 	return 0;  in stm32_dma3_pause()
1470 	return 0;  in stm32_dma3_resume()
1495 	return 0;  in stm32_dma3_terminate_all()
1569 	if (ret < 0)  in stm32_dma3_filter_fn()
1598 	conf.req_line = dma_spec->args[0];  in stm32_dma3_of_xlate()
1623 	u32 chan_reserved, mask = 0, i, ccidcfgr, invalid_cid = 0;  in stm32_dma3_check_rif()
1637 	for (i = 0; i < ddata->dma_channels; i++) {  in stm32_dma3_check_rif()
1697 	ddata->base = devm_platform_ioremap_resource(pdev, 0);  in stm32_dma3_probe()
1770 	ddata->ports_max_dw[0] = FIELD_GET(G_M0_DATA_WIDTH_ENC, hwcfgr);  in stm32_dma3_probe()
1795 	if (chan_reserved == GENMASK(ddata->dma_channels - 1, 0)) {  in stm32_dma3_probe()
1801 	/* G_FIFO_SIZE x=0..7 in HWCFGR3 and G_FIFO_SIZE x=8..15 in HWCFGR4 */  in stm32_dma3_probe()
1805 	for (i = 0; i < ddata->dma_channels; i++) {  in stm32_dma3_probe()
1812 		/* If chan->fifo_size > 0 then half of the fifo size, else no burst when no FIFO */  in stm32_dma3_probe()
1813 		chan->max_burst = (chan->fifo_size) ? (1 << (chan->fifo_size + 1)) / 2 : 0;  in stm32_dma3_probe()
1820 	for (i = 0; i < ddata->dma_channels; i++) {  in stm32_dma3_probe()
1839 		if (ret < 0)  in stm32_dma3_probe()
1843 		ret = devm_request_irq(&pdev->dev, chan->irq, stm32_dma3_chan_irq, 0,  in stm32_dma3_probe()
1868 	return 0;  in stm32_dma3_probe()
1887 	return 0;  in stm32_dma3_runtime_suspend()