Lines Matching +full:burst +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
28 #include "virt-dma.h"
60 * 001: +1 (Burst=0), +4 (Burst=1)
61 * 010: +2 (Burst=0), +8 (Burst=1)
62 * 011: +4 (Burst=0), +16 (Burst=1)
63 * 101: -1 (Burst=0), -4 (Burst=1)
64 * 110: -2 (Burst=0), -8 (Burst=1)
65 * 111: -4 (Burst=0), -16 (Burst=1)
86 * e.g. MMC must always request channels where dma_slave_config->slave_id is 5.
89 * 1-15: Request / Grant signal
159 return &chan->dev->device; in chan2dev()
187 spin_lock_irqsave(&ch->vc.lock, flags); in moxart_terminate_all()
189 if (ch->desc) { in moxart_terminate_all()
190 moxart_dma_desc_free(&ch->desc->vd); in moxart_terminate_all()
191 ch->desc = NULL; in moxart_terminate_all()
194 ctrl = readl(ch->base + REG_OFF_CTRL); in moxart_terminate_all()
196 writel(ctrl, ch->base + REG_OFF_CTRL); in moxart_terminate_all()
198 vchan_get_all_descriptors(&ch->vc, &head); in moxart_terminate_all()
199 spin_unlock_irqrestore(&ch->vc.lock, flags); in moxart_terminate_all()
200 vchan_dma_desc_free_list(&ch->vc, &head); in moxart_terminate_all()
211 ch->cfg = *cfg; in moxart_slave_config()
213 ctrl = readl(ch->base + REG_OFF_CTRL); in moxart_slave_config()
218 switch (ch->cfg.src_addr_width) { in moxart_slave_config()
221 if (ch->cfg.direction != DMA_MEM_TO_DEV) in moxart_slave_config()
228 if (ch->cfg.direction != DMA_MEM_TO_DEV) in moxart_slave_config()
235 if (ch->cfg.direction != DMA_MEM_TO_DEV) in moxart_slave_config()
241 return -EINVAL; in moxart_slave_config()
244 if (ch->cfg.direction == DMA_MEM_TO_DEV) { in moxart_slave_config()
247 ctrl |= (ch->line_reqno << 16 & in moxart_slave_config()
252 ctrl |= (ch->line_reqno << 24 & in moxart_slave_config()
256 writel(ctrl, ch->base + REG_OFF_CTRL); in moxart_slave_config()
281 dev_addr = ch->cfg.src_addr; in moxart_prep_slave_sg()
282 dev_width = ch->cfg.src_addr_width; in moxart_prep_slave_sg()
284 dev_addr = ch->cfg.dst_addr; in moxart_prep_slave_sg()
285 dev_width = ch->cfg.dst_addr_width; in moxart_prep_slave_sg()
307 d->sglen = sg_len; in moxart_prep_slave_sg()
309 d->dma_dir = dir; in moxart_prep_slave_sg()
310 d->dev_addr = dev_addr; in moxart_prep_slave_sg()
311 d->es = es; in moxart_prep_slave_sg()
314 d->sg[i].addr = sg_dma_address(sgent); in moxart_prep_slave_sg()
315 d->sg[i].len = sg_dma_len(sgent); in moxart_prep_slave_sg()
318 ch->error = 0; in moxart_prep_slave_sg()
320 return vchan_tx_prep(&ch->vc, &d->vd, tx_flags); in moxart_prep_slave_sg()
326 struct moxart_dmadev *mdc = ofdma->of_dma_data; in moxart_of_xlate()
330 chan = dma_get_any_slave_channel(&mdc->dma_slave); in moxart_of_xlate()
335 ch->line_reqno = dma_spec->args[0]; in moxart_of_xlate()
345 __func__, ch->ch_num); in moxart_alloc_chan_resources()
346 ch->allocated = 1; in moxart_alloc_chan_resources()
355 vchan_free_chan_resources(&ch->vc); in moxart_free_chan_resources()
358 __func__, ch->ch_num); in moxart_free_chan_resources()
359 ch->allocated = 0; in moxart_free_chan_resources()
365 writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE); in moxart_dma_set_params()
366 writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST); in moxart_dma_set_params()
371 struct moxart_desc *d = ch->desc; in moxart_set_transfer_params()
372 unsigned int sglen_div = es_bytes[d->es]; in moxart_set_transfer_params()
374 d->dma_cycles = len >> sglen_div; in moxart_set_transfer_params()
380 writel(d->dma_cycles, ch->base + REG_OFF_CYCLES); in moxart_set_transfer_params()
382 dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n", in moxart_set_transfer_params()
383 __func__, d->dma_cycles, len); in moxart_set_transfer_params()
390 ctrl = readl(ch->base + REG_OFF_CTRL); in moxart_start_dma()
392 writel(ctrl, ch->base + REG_OFF_CTRL); in moxart_start_dma()
397 struct moxart_desc *d = ch->desc; in moxart_dma_start_sg()
398 struct moxart_sg *sg = ch->desc->sg + idx; in moxart_dma_start_sg()
400 if (ch->desc->dma_dir == DMA_MEM_TO_DEV) in moxart_dma_start_sg()
401 moxart_dma_set_params(ch, sg->addr, d->dev_addr); in moxart_dma_start_sg()
402 else if (ch->desc->dma_dir == DMA_DEV_TO_MEM) in moxart_dma_start_sg()
403 moxart_dma_set_params(ch, d->dev_addr, sg->addr); in moxart_dma_start_sg()
405 moxart_set_transfer_params(ch, sg->len); in moxart_dma_start_sg()
415 vd = vchan_next_desc(&ch->vc); in moxart_dma_start_desc()
418 ch->desc = NULL; in moxart_dma_start_desc()
422 list_del(&vd->node); in moxart_dma_start_desc()
424 ch->desc = to_moxart_dma_desc(&vd->tx); in moxart_dma_start_desc()
425 ch->sgidx = 0; in moxart_dma_start_desc()
435 spin_lock_irqsave(&ch->vc.lock, flags); in moxart_issue_pending()
436 if (vchan_issue_pending(&ch->vc) && !ch->desc) in moxart_issue_pending()
438 spin_unlock_irqrestore(&ch->vc.lock, flags); in moxart_issue_pending()
445 size_t size; in moxart_dma_desc_size() local
447 for (size = i = completed_sgs; i < d->sglen; i++) in moxart_dma_desc_size()
448 size += d->sg[i].len; in moxart_dma_desc_size()
450 return size; in moxart_dma_desc_size()
455 size_t size; in moxart_dma_desc_size_in_flight() local
458 size = moxart_dma_desc_size(ch->desc, ch->sgidx); in moxart_dma_desc_size_in_flight()
459 cycles = readl(ch->base + REG_OFF_CYCLES); in moxart_dma_desc_size_in_flight()
460 completed_cycles = (ch->desc->dma_cycles - cycles); in moxart_dma_desc_size_in_flight()
461 size -= completed_cycles << es_bytes[ch->desc->es]; in moxart_dma_desc_size_in_flight()
463 dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size); in moxart_dma_desc_size_in_flight()
465 return size; in moxart_dma_desc_size_in_flight()
483 spin_lock_irqsave(&ch->vc.lock, flags); in moxart_tx_status()
484 vd = vchan_find_desc(&ch->vc, cookie); in moxart_tx_status()
486 d = to_moxart_dma_desc(&vd->tx); in moxart_tx_status()
487 txstate->residue = moxart_dma_desc_size(d, 0); in moxart_tx_status()
488 } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) { in moxart_tx_status()
489 txstate->residue = moxart_dma_desc_size_in_flight(ch); in moxart_tx_status()
491 spin_unlock_irqrestore(&ch->vc.lock, flags); in moxart_tx_status()
493 if (ch->error) in moxart_tx_status()
501 dma->device_prep_slave_sg = moxart_prep_slave_sg; in moxart_dma_init()
502 dma->device_alloc_chan_resources = moxart_alloc_chan_resources; in moxart_dma_init()
503 dma->device_free_chan_resources = moxart_free_chan_resources; in moxart_dma_init()
504 dma->device_issue_pending = moxart_issue_pending; in moxart_dma_init()
505 dma->device_tx_status = moxart_tx_status; in moxart_dma_init()
506 dma->device_config = moxart_slave_config; in moxart_dma_init()
507 dma->device_terminate_all = moxart_terminate_all; in moxart_dma_init()
508 dma->dev = dev; in moxart_dma_init()
510 INIT_LIST_HEAD(&dma->channels); in moxart_dma_init()
516 struct moxart_chan *ch = &mc->slave_chans[0]; in moxart_dma_interrupt()
520 dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__); in moxart_dma_interrupt()
523 if (!ch->allocated) in moxart_dma_interrupt()
526 ctrl = readl(ch->base + REG_OFF_CTRL); in moxart_dma_interrupt()
528 dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n", in moxart_dma_interrupt()
529 __func__, ch, ch->base, ctrl); in moxart_dma_interrupt()
533 if (ch->desc) { in moxart_dma_interrupt()
534 spin_lock(&ch->vc.lock); in moxart_dma_interrupt()
535 if (++ch->sgidx < ch->desc->sglen) { in moxart_dma_interrupt()
536 moxart_dma_start_sg(ch, ch->sgidx); in moxart_dma_interrupt()
538 vchan_cookie_complete(&ch->desc->vd); in moxart_dma_interrupt()
539 moxart_dma_start_desc(&ch->vc.chan); in moxart_dma_interrupt()
541 spin_unlock(&ch->vc.lock); in moxart_dma_interrupt()
547 ch->error = 1; in moxart_dma_interrupt()
550 writel(ctrl, ch->base + REG_OFF_CTRL); in moxart_dma_interrupt()
558 struct device *dev = &pdev->dev; in moxart_probe()
559 struct device_node *node = dev->of_node; in moxart_probe()
568 return -ENOMEM; in moxart_probe()
573 return -EINVAL; in moxart_probe()
580 dma_cap_zero(mdc->dma_slave.cap_mask); in moxart_probe()
581 dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask); in moxart_probe()
582 dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask); in moxart_probe()
584 moxart_dma_init(&mdc->dma_slave, dev); in moxart_probe()
586 ch = &mdc->slave_chans[0]; in moxart_probe()
588 ch->ch_num = i; in moxart_probe()
589 ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE; in moxart_probe()
590 ch->allocated = 0; in moxart_probe()
592 ch->vc.desc_free = moxart_dma_desc_free; in moxart_probe()
593 vchan_init(&ch->vc, &mdc->dma_slave); in moxart_probe()
595 dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n", in moxart_probe()
596 __func__, i, ch->ch_num, ch->base); in moxart_probe()
602 "moxart-dma-engine", mdc); in moxart_probe()
607 mdc->irq = irq; in moxart_probe()
609 ret = dma_async_device_register(&mdc->dma_slave); in moxart_probe()
618 dma_async_device_unregister(&mdc->dma_slave); in moxart_probe()
631 devm_free_irq(&pdev->dev, m->irq, m); in moxart_remove()
633 dma_async_device_unregister(&m->dma_slave); in moxart_remove()
635 if (pdev->dev.of_node) in moxart_remove()
636 of_dma_controller_free(pdev->dev.of_node); in moxart_remove()
640 { .compatible = "moxa,moxart-dma" },
649 .name = "moxart-dma-engine",