1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define GET_IDXD_VER_MAJOR(x)		(((x) & IDXD_VER_MAJOR_MASK) >> 4)
42 		u64 max_batch_shift:4;
47 	u64 bits;  member
55 		u64 wqcfg_size:4;
67 	u64 bits;  member
81 	u64 bits;  member
90 	u64 bits;  member
99 	u64 bits[4];  member
116 	u64 bits[2];  member
125 		u32 rsvd:4;
130 	u32 bits;  member
141 	u32 bits;  member
151 	u32 bits;  member
185 	u32 bits;  member
215 	u32 bits;  member
276 		u64 rsvd3:4;
286 	u64 bits[4];  member
305 	u64 bits;  member
322 	u64 bits[2];  member
336 	u32 bits;  member
346 		u64 rsvd2:4;
348 		u64 rsvd3:4;
354 	u64 bits;  member
358 	u64 wqs[4];
365 		/* bytes 0-3 */
369 		/* bytes 4-7 */
373 		/* bytes 8-11 */
378 		u32 priority:4;
384 		/* bytes 12-15 */
386 		u32 max_batch_shift:4;
389 		/* bytes 16-19 */
394 		/* bytes 20-23 */
399 		/* bytes 24-27 */
406 		/* bytes 28-31 */
409 		/* bytes 32-63 */
410 		u64 op_config[4];
412 	u32 bits[16];  member
423  * idxd - struct idxd *
424  * n - wq id
425  * ofs - the index of the 32b dword for the config register
429  * Each register is 32bits. The ofs gives us the number of register to access.
434 	(__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs);	\
437 #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32))
440 #define GRPWQCFG_STRIDES	4
444  * idxd - struct idxd *
445  * n - group id
446  * ofs - the index of the 64b qword for the config register
448  * The GRPCFG register block is divided into three sub-registers, which
450  * to the register block that contains the three sub-registers.
451  * Each register block is 64bits. And the ofs gives us the offset
454 #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
456 #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32)
457 #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40)
466 		u64 num_event_category:4;
476 	u64 bits;  member
485 	u64 bits;  member
491 			u32 event_category:4;
504 			u32 num_events:4;
530 		u64 event_category:4;
533 		u64 rsvd3:4;
550 		u64 event_cat:4;
560 		u64 pg_sz:4;
582 	u64 bits;  member
600 	u64 rsvd2:4;
632 	u64 rsvd[4];