1 /* SPDX-License-Identifier: GPL-2.0 */
47 	u64 bits;  member
53 		u64 total_wq_size:16;
67 	u64 bits;  member
81 	u64 bits;  member
90 	u64 bits;  member
99 	u64 bits[4];  member
109 		u64 grpcfg:16;
110 		u64 wqcfg:16;
111 		u64 msix_perm:16;
112 		u64 ims:16;
113 		u64 perfmon:16;
116 	u64 bits[2];  member
130 	u32 bits;  member
141 	u32 bits;  member
151 	u32 bits;  member
185 	u32 bits;  member
215 	u32 bits;  member
278 		u64 batch_idx:16;
279 		u64 rsvd4:16;
286 	u64 bits[4];  member
305 	u64 bits;  member
318 		u64 size:16;
322 	u64 bits[2];  member
336 	u32 bits;  member
354 	u64 bits;  member
365 		/* bytes 0-3 */
369 		/* bytes 4-7 */
373 		/* bytes 8-11 */
384 		/* bytes 12-15 */
389 		/* bytes 16-19 */
394 		/* bytes 20-23 */
399 		/* bytes 24-27 */
406 		/* bytes 28-31 */
409 		/* bytes 32-63 */
412 	u32 bits[16];  member
423  * idxd - struct idxd *
424  * n - wq id
425  * ofs - the index of the 32b dword for the config register
429  * Each register is 32bits. The ofs gives us the number of register to access.
434 	(__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs);	\
437 #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32))
444  * idxd - struct idxd *
445  * n - group id
446  * ofs - the index of the 64b qword for the config register
448  * The GRPCFG register block is divided into three sub-registers, which
450  * to the register block that contains the three sub-registers.
451  * Each register block is 64bits. And the ofs gives us the offset
454 #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
456 #define GRPENGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 32)
457 #define GRPFLGCFG_OFFSET(idxd_dev, n) ((idxd_dev)->grpcfg_offset + (n) * GRPCFG_SIZE + 40)
467 		u64 global_event_category:16;
476 	u64 bits;  member
485 	u64 bits;  member
571 		u32 head:16;
572 		u32 rsvd:16;
573 		u32 tail:16;
582 	u64 bits;  member