Lines Matching +full:break +full:- +full:control
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
11 #include <linux/io-64-nonatomic-lo-hi.h>
13 #include "dw-edma-core.h"
14 #include "dw-edma-v0-core.h"
15 #include "dw-edma-v0-regs.h"
16 #include "dw-edma-v0-debugfs.h"
30 return dw->chip->reg_base; in __dw_regs()
34 writel(value, &(__dw_regs(dw)->name))
37 readl(&(__dw_regs(dw)->name))
59 writeq(value, &(__dw_regs(dw)->name))
62 readq(&(__dw_regs(dw)->name))
84 writel(value, &(__dw_regs(dw)->type.unroll.name))
97 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) in __dw_ch_regs()
98 return &(__dw_regs(dw)->type.legacy.ch); in __dw_ch_regs()
101 return &__dw_regs(dw)->type.unroll.ch[ch].wr; in __dw_ch_regs()
103 return &__dw_regs(dw)->type.unroll.ch[ch].rd; in __dw_ch_regs()
109 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) { in writel_ch()
113 raw_spin_lock_irqsave(&dw->lock, flags); in writel_ch()
120 &(__dw_regs(dw)->type.legacy.viewport_sel)); in writel_ch()
123 raw_spin_unlock_irqrestore(&dw->lock, flags); in writel_ch()
134 if (dw->chip->mf == EDMA_MF_EDMA_LEGACY) { in readl_ch()
138 raw_spin_lock_irqsave(&dw->lock, flags); in readl_ch()
145 &(__dw_regs(dw)->type.legacy.viewport_sel)); in readl_ch()
148 raw_spin_unlock_irqrestore(&dw->lock, flags); in readl_ch()
157 writel_ch(dw, dir, ch, value, &(__dw_ch_regs(dw, dir, ch)->name))
160 readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
191 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_ch_status()
195 GET_CH_32(dw, chan->dir, chan->id, ch_control1)); in dw_edma_v0_core_ch_status()
207 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_clear_done_int()
209 SET_RW_32(dw, chan->dir, int_clear, in dw_edma_v0_core_clear_done_int()
210 FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id))); in dw_edma_v0_core_clear_done_int()
215 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_clear_abort_int()
217 SET_RW_32(dw, chan->dir, int_clear, in dw_edma_v0_core_clear_abort_int()
218 FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id))); in dw_edma_v0_core_clear_abort_int()
237 struct dw_edma *dw = dw_irq->dw; in dw_edma_v0_core_handle_int()
245 total = dw->wr_ch_cnt; in dw_edma_v0_core_handle_int()
247 mask = dw_irq->wr_mask; in dw_edma_v0_core_handle_int()
249 total = dw->rd_ch_cnt; in dw_edma_v0_core_handle_int()
250 off = dw->wr_ch_cnt; in dw_edma_v0_core_handle_int()
251 mask = dw_irq->rd_mask; in dw_edma_v0_core_handle_int()
257 chan = &dw->chan[pos + off]; in dw_edma_v0_core_handle_int()
268 chan = &dw->chan[pos + off]; in dw_edma_v0_core_handle_int()
280 u32 control, u32 size, u64 sar, u64 dar) in dw_edma_v0_write_ll_data() argument
284 if (chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { in dw_edma_v0_write_ll_data()
285 struct dw_edma_v0_lli *lli = chunk->ll_region.vaddr.mem + ofs; in dw_edma_v0_write_ll_data()
287 lli->control = control; in dw_edma_v0_write_ll_data()
288 lli->transfer_size = size; in dw_edma_v0_write_ll_data()
289 lli->sar.reg = sar; in dw_edma_v0_write_ll_data()
290 lli->dar.reg = dar; in dw_edma_v0_write_ll_data()
292 struct dw_edma_v0_lli __iomem *lli = chunk->ll_region.vaddr.io + ofs; in dw_edma_v0_write_ll_data()
294 writel(control, &lli->control); in dw_edma_v0_write_ll_data()
295 writel(size, &lli->transfer_size); in dw_edma_v0_write_ll_data()
296 writeq(sar, &lli->sar.reg); in dw_edma_v0_write_ll_data()
297 writeq(dar, &lli->dar.reg); in dw_edma_v0_write_ll_data()
302 int i, u32 control, u64 pointer) in dw_edma_v0_write_ll_link() argument
306 if (chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL) { in dw_edma_v0_write_ll_link()
307 struct dw_edma_v0_llp *llp = chunk->ll_region.vaddr.mem + ofs; in dw_edma_v0_write_ll_link()
309 llp->control = control; in dw_edma_v0_write_ll_link()
310 llp->llp.reg = pointer; in dw_edma_v0_write_ll_link()
312 struct dw_edma_v0_llp __iomem *llp = chunk->ll_region.vaddr.io + ofs; in dw_edma_v0_write_ll_link()
314 writel(control, &llp->control); in dw_edma_v0_write_ll_link()
315 writeq(pointer, &llp->llp.reg); in dw_edma_v0_write_ll_link()
322 struct dw_edma_chan *chan = chunk->chan; in dw_edma_v0_core_write_chunk()
323 u32 control = 0, i = 0; in dw_edma_v0_core_write_chunk() local
326 if (chunk->cb) in dw_edma_v0_core_write_chunk()
327 control = DW_EDMA_V0_CB; in dw_edma_v0_core_write_chunk()
329 j = chunk->bursts_alloc; in dw_edma_v0_core_write_chunk()
330 list_for_each_entry(child, &chunk->burst->list, list) { in dw_edma_v0_core_write_chunk()
331 j--; in dw_edma_v0_core_write_chunk()
333 control |= DW_EDMA_V0_LIE; in dw_edma_v0_core_write_chunk()
334 if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) in dw_edma_v0_core_write_chunk()
335 control |= DW_EDMA_V0_RIE; in dw_edma_v0_core_write_chunk()
338 dw_edma_v0_write_ll_data(chunk, i++, control, child->sz, in dw_edma_v0_core_write_chunk()
339 child->sar, child->dar); in dw_edma_v0_core_write_chunk()
342 control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB; in dw_edma_v0_core_write_chunk()
343 if (!chunk->cb) in dw_edma_v0_core_write_chunk()
344 control |= DW_EDMA_V0_CB; in dw_edma_v0_core_write_chunk()
346 dw_edma_v0_write_ll_link(chunk, i, control, chunk->ll_region.paddr); in dw_edma_v0_core_write_chunk()
354 * over different buses. Ensure LL-data reaches the memory before the in dw_edma_v0_sync_ll_data()
355 * doorbell register is toggled by issuing the dummy-read from the remote in dw_edma_v0_sync_ll_data()
359 if (!(chunk->chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) in dw_edma_v0_sync_ll_data()
360 readl(chunk->ll_region.vaddr.io); in dw_edma_v0_sync_ll_data()
365 struct dw_edma_chan *chan = chunk->chan; in dw_edma_v0_core_start()
366 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_start()
373 SET_RW_32(dw, chan->dir, engine_en, BIT(0)); in dw_edma_v0_core_start()
374 if (dw->chip->mf == EDMA_MF_HDMA_COMPAT) { in dw_edma_v0_core_start()
375 switch (chan->id) { in dw_edma_v0_core_start()
377 SET_RW_COMPAT(dw, chan->dir, ch0_pwr_en, in dw_edma_v0_core_start()
379 break; in dw_edma_v0_core_start()
381 SET_RW_COMPAT(dw, chan->dir, ch1_pwr_en, in dw_edma_v0_core_start()
383 break; in dw_edma_v0_core_start()
385 SET_RW_COMPAT(dw, chan->dir, ch2_pwr_en, in dw_edma_v0_core_start()
387 break; in dw_edma_v0_core_start()
389 SET_RW_COMPAT(dw, chan->dir, ch3_pwr_en, in dw_edma_v0_core_start()
391 break; in dw_edma_v0_core_start()
393 SET_RW_COMPAT(dw, chan->dir, ch4_pwr_en, in dw_edma_v0_core_start()
395 break; in dw_edma_v0_core_start()
397 SET_RW_COMPAT(dw, chan->dir, ch5_pwr_en, in dw_edma_v0_core_start()
399 break; in dw_edma_v0_core_start()
401 SET_RW_COMPAT(dw, chan->dir, ch6_pwr_en, in dw_edma_v0_core_start()
403 break; in dw_edma_v0_core_start()
405 SET_RW_COMPAT(dw, chan->dir, ch7_pwr_en, in dw_edma_v0_core_start()
407 break; in dw_edma_v0_core_start()
410 /* Interrupt unmask - done, abort */ in dw_edma_v0_core_start()
411 tmp = GET_RW_32(dw, chan->dir, int_mask); in dw_edma_v0_core_start()
412 tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); in dw_edma_v0_core_start()
413 tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); in dw_edma_v0_core_start()
414 SET_RW_32(dw, chan->dir, int_mask, tmp); in dw_edma_v0_core_start()
416 tmp = GET_RW_32(dw, chan->dir, linked_list_err_en); in dw_edma_v0_core_start()
417 tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id)); in dw_edma_v0_core_start()
418 SET_RW_32(dw, chan->dir, linked_list_err_en, tmp); in dw_edma_v0_core_start()
419 /* Channel control */ in dw_edma_v0_core_start()
420 SET_CH_32(dw, chan->dir, chan->id, ch_control1, in dw_edma_v0_core_start()
423 /* llp is not aligned on 64bit -> keep 32bit accesses */ in dw_edma_v0_core_start()
424 SET_CH_32(dw, chan->dir, chan->id, llp.lsb, in dw_edma_v0_core_start()
425 lower_32_bits(chunk->ll_region.paddr)); in dw_edma_v0_core_start()
426 SET_CH_32(dw, chan->dir, chan->id, llp.msb, in dw_edma_v0_core_start()
427 upper_32_bits(chunk->ll_region.paddr)); in dw_edma_v0_core_start()
433 SET_RW_32(dw, chan->dir, doorbell, in dw_edma_v0_core_start()
434 FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id)); in dw_edma_v0_core_start()
439 struct dw_edma *dw = chan->dw; in dw_edma_v0_core_ch_config()
442 /* MSI done addr - low, high */ in dw_edma_v0_core_ch_config()
443 SET_RW_32(dw, chan->dir, done_imwr.lsb, chan->msi.address_lo); in dw_edma_v0_core_ch_config()
444 SET_RW_32(dw, chan->dir, done_imwr.msb, chan->msi.address_hi); in dw_edma_v0_core_ch_config()
445 /* MSI abort addr - low, high */ in dw_edma_v0_core_ch_config()
446 SET_RW_32(dw, chan->dir, abort_imwr.lsb, chan->msi.address_lo); in dw_edma_v0_core_ch_config()
447 SET_RW_32(dw, chan->dir, abort_imwr.msb, chan->msi.address_hi); in dw_edma_v0_core_ch_config()
448 /* MSI data - low, high */ in dw_edma_v0_core_ch_config()
449 switch (chan->id) { in dw_edma_v0_core_ch_config()
452 tmp = GET_RW_32(dw, chan->dir, ch01_imwr_data); in dw_edma_v0_core_ch_config()
453 break; in dw_edma_v0_core_ch_config()
457 tmp = GET_RW_32(dw, chan->dir, ch23_imwr_data); in dw_edma_v0_core_ch_config()
458 break; in dw_edma_v0_core_ch_config()
462 tmp = GET_RW_32(dw, chan->dir, ch45_imwr_data); in dw_edma_v0_core_ch_config()
463 break; in dw_edma_v0_core_ch_config()
467 tmp = GET_RW_32(dw, chan->dir, ch67_imwr_data); in dw_edma_v0_core_ch_config()
468 break; in dw_edma_v0_core_ch_config()
471 if (chan->id & BIT(0)) { in dw_edma_v0_core_ch_config()
475 chan->msi.data); in dw_edma_v0_core_ch_config()
480 chan->msi.data); in dw_edma_v0_core_ch_config()
483 switch (chan->id) { in dw_edma_v0_core_ch_config()
486 SET_RW_32(dw, chan->dir, ch01_imwr_data, tmp); in dw_edma_v0_core_ch_config()
487 break; in dw_edma_v0_core_ch_config()
491 SET_RW_32(dw, chan->dir, ch23_imwr_data, tmp); in dw_edma_v0_core_ch_config()
492 break; in dw_edma_v0_core_ch_config()
496 SET_RW_32(dw, chan->dir, ch45_imwr_data, tmp); in dw_edma_v0_core_ch_config()
497 break; in dw_edma_v0_core_ch_config()
501 SET_RW_32(dw, chan->dir, ch67_imwr_data, tmp); in dw_edma_v0_core_ch_config()
502 break; in dw_edma_v0_core_ch_config()
524 dw->core = &dw_edma_v0_core; in dw_edma_v0_core_register()